[llvm-branch-commits] [llvm] release/18.x: [RISCV] Add test for aliasing miscompile fixed by #83017. NFC (PR #83856)

tstellar wrote: There is a problem with the ABI check CI test, but I believe this patch will change the C++ ABI, because it changes the signature of `computeAliasing` Is it possible to add a function with the old signature that wraps and calls the new signature?

[llvm-branch-commits] [llvm] fcc33dc - [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes

Author: Simon Pilgrim Date: 2024-03-12T22:30:11-07:00 New Revision: fcc33dca02d1f22d3dad5c4558ddff4926aef9d9 URL: https://github.com/llvm/llvm-project/commit/fcc33dca02d1f22d3dad5c4558ddff4926aef9d9 DIFF: https://github.com/llvm/llvm-project/commit/fcc33dca02d1f22d3dad5c4558ddff4926aef9d9.diff

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84698 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84698 >From fcc33dca02d1f22d3dad5c4558ddff4926aef9d9 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 10 Mar 2024 16:23:51 + Subject: [PATCH] [X86] combineAndShuffleNot - ensure the type is legal before

[llvm-branch-commits] [llvm] release/18.x: [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157) (PR #84946)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84946 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 39e3ba8 - [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157)

Author: Florian Hahn Date: 2024-03-12T22:28:32-07:00 New Revision: 39e3ba8a383e05af376d613594373c482f72bb3e URL: https://github.com/llvm/llvm-project/commit/39e3ba8a383e05af376d613594373c482f72bb3e DIFF: https://github.com/llvm/llvm-project/commit/39e3ba8a383e05af376d613594373c482f72bb3e.diff

[llvm-branch-commits] [llvm] release/18.x: [DSE] Remove malloc from EarliestEscapeInfo before removing. (#84157) (PR #84946)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84946 >From 39e3ba8a383e05af376d613594373c482f72bb3e Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 6 Mar 2024 20:08:00 + Subject: [PATCH] [DSE] Remove malloc from EarliestEscapeInfo before removing.

[llvm-branch-commits] [llvm] Backport PR83993 to 18.x (PR #84298)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 3f8711f - [InstCombine] Fix miscompilation in PR83947 (#83993)

Author: Yingwei Zheng Date: 2024-03-12T22:05:53-07:00 New Revision: 3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d URL: https://github.com/llvm/llvm-project/commit/3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d DIFF: https://github.com/llvm/llvm-project/commit/3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d.diff

[llvm-branch-commits] [llvm] Backport PR83993 to 18.x (PR #84298)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/84298 >From 3f8711fc5e01685f0a751ef296d16cf9a1f4fd4d Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Tue, 5 Mar 2024 22:34:04 +0800 Subject: [PATCH] [InstCombine] Fix miscompilation in PR83947 (#83993)

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] a9ba36c - [Clang][LoongArch] Precommit test for fix wrong return value type of __iocsrrd_h. NFC

Author: wanglei Date: 2024-03-12T22:01:13-07:00 New Revision: a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef URL: https://github.com/llvm/llvm-project/commit/a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef DIFF: https://github.com/llvm/llvm-project/commit/a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef.diff LOG:

[llvm-branch-commits] [clang] 9b9aee1 - [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100)

Author: wanglei Date: 2024-03-12T22:01:13-07:00 New Revision: 9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44 URL: https://github.com/llvm/llvm-project/commit/9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44 DIFF: https://github.com/llvm/llvm-project/commit/9b9aee16d4dcf1b4af49988ebd7918fa4ce77e44.diff LOG:

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84715 >From a9ba36c7e7d7fa076f201843e3b826b6c6d7f5ef Mon Sep 17 00:00:00 2001 From: wanglei Date: Tue, 5 Mar 2024 19:44:28 +0800 Subject: [PATCH 1/2] [Clang][LoongArch] Precommit test for fix wrong return value type

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] d77c5c3 - [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454)

Author: wanglei Date: 2024-03-12T21:55:37-07:00 New Revision: d77c5c3830d925b3795e2f1535a6568399fe6626 URL: https://github.com/llvm/llvm-project/commit/d77c5c3830d925b3795e2f1535a6568399fe6626 DIFF: https://github.com/llvm/llvm-project/commit/d77c5c3830d925b3795e2f1535a6568399fe6626.diff LOG:

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84716 >From d77c5c3830d925b3795e2f1535a6568399fe6626 Mon Sep 17 00:00:00 2001 From: wanglei Date: Mon, 11 Mar 2024 08:59:17 +0800 Subject: [PATCH] [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the

[llvm-branch-commits] [clang] [analyzer] Backport deducing "this" crash fix (PR #84194)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] 1de8ea7 - [analyzer] Fix crash on dereference invalid return value of getAdjustedParameterIndex() (#83585)

Author: Exile Date: 2024-03-12T21:53:55-07:00 New Revision: 1de8ea75d9b309fd14e9f1be86ea5079d9a53d69 URL: https://github.com/llvm/llvm-project/commit/1de8ea75d9b309fd14e9f1be86ea5079d9a53d69 DIFF: https://github.com/llvm/llvm-project/commit/1de8ea75d9b309fd14e9f1be86ea5079d9a53d69.diff LOG:

[llvm-branch-commits] [clang] [analyzer] Backport deducing "this" crash fix (PR #84194)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/84194 >From 1de8ea75d9b309fd14e9f1be86ea5079d9a53d69 Mon Sep 17 00:00:00 2001 From: Exile <2094247...@qq.com> Date: Thu, 7 Mar 2024 00:01:30 +0800 Subject: [PATCH] [analyzer] Fix crash on dereference invalid return

[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

tstellar wrote: > Do we have any ABI stability guarantees for LLVM C++ APIs? I would think that > a lot of back ports can break the C++ ABI of LLVM in general? Yes, we always try to keep the C++ API stable in point releases. https://github.com/llvm/llvm-project/pull/83971

[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

joker-eph wrote: Do we have any ABI stability guarantees for LLVM C++ APIs? I would think that a lot of back ports can break the C++ ABI of LLVM in general? (I was assuming we'd care about the LLVM C API, libclang, ...) https://github.com/llvm/llvm-project/pull/83971

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/84404 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -1246,32 +1244,16 @@ Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> , Type *Ty) { return nullptr; } -Value *HWAddressSanitizer::getPC(IRBuilder<> ) { - if (TargetTriple.getArch() == Triple::aarch64) -return readRegister(IRB, "pc"); - return

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -236,5 +238,37 @@ void alignAndPadAlloca(memtag::AllocaInfo , llvm::Align Alignment) { Info.AI = NewAI; } +Value *readRegister(IRBuilder<> , StringRef Name) { + Module *M = IRB.GetInsertBlock()->getParent()->getParent(); + Function *ReadRegister =

[llvm-branch-commits] [libcxx] release/18.x: [libc++] Enable availability based on the compiler instead of __has_extension (#84065) (PR #84374)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84374 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libcxx] c14bf0a - [libc++] Enable availability based on the compiler instead of __has_extension (#84065)

Author: Louis Dionne Date: 2024-03-12T18:38:24-07:00 New Revision: c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3 URL: https://github.com/llvm/llvm-project/commit/c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3 DIFF: https://github.com/llvm/llvm-project/commit/c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3.diff

[llvm-branch-commits] [libcxx] release/18.x: [libc++] Enable availability based on the compiler instead of __has_extension (#84065) (PR #84374)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84374 >From c14bf0a13d426b0b8fc2bc395bf450d9a6982fe3 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Thu, 7 Mar 2024 15:12:21 -0500 Subject: [PATCH] [libc++] Enable availability based on the compiler instead of

[llvm-branch-commits] [clang][ubsan] Switch UBSAN optimization to `llvm.experimental.hot` (PR #84858)

@@ -100,9 +100,9 @@ using namespace llvm; namespace llvm { extern cl::opt PrintPipelinePasses; -cl::opt ClRemoveTraps("clang-remove-traps", cl::Optional, -cl::desc("Insert remove-traps pass."), -cl::init(false)); +static

[llvm-branch-commits] [llvm] Backport #83980 to 18.x (PR #84023)

tstellar wrote: Merged: 55193c2ba53f4156481b63b5956eaadd8edb0877 https://github.com/llvm/llvm-project/pull/84023 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] Backport #83980 to 18.x (PR #84023)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84023 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 55193c2 - [InstCombine] Handle scalable splat in `getFlippedStrictnessPredicateAndConstant`

Author: Yingwei Zheng Date: 2024-03-12T18:19:15-07:00 New Revision: 55193c2ba53f4156481b63b5956eaadd8edb0877 URL: https://github.com/llvm/llvm-project/commit/55193c2ba53f4156481b63b5956eaadd8edb0877 DIFF: https://github.com/llvm/llvm-project/commit/55193c2ba53f4156481b63b5956eaadd8edb0877.diff

[llvm-branch-commits] Rename `remove-traps` to `lower-builtin-hot` (PR #84853)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84853 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Rename `remove-traps` to `lower-builtin-hot` (PR #84853)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84853 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang][CodeGen] Remove SimplifyCFGPass preceding RemoveTrapsPass (PR #84852)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84852 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang][CodeGen] Remove SimplifyCFGPass preceding RemoveTrapsPass (PR #84852)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84852 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang][ubsan] Switch UBSAN optimization to `llvm.experimental.hot` (PR #84858)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang][ubsan] Switch UBSAN optimization to `llvm.experimental.hot` (PR #84858)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Lld mac fix (PR #84764)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/84764 >From 2ddb32b50752ca91ca9946cb9c9ea3d92c8616d0 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 9 Mar 2024 14:26:47 -0800 Subject: [PATCH 1/3] Bump version to 18.1.2 --- llvm/CMakeLists.txt | 2 +- 1

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83834 >From 9cec3b7b1ea0491df688555a51750efe6c9bd075 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720)

[llvm-branch-commits] [lld] 78859f1 - [lld][LoongArch] Support the R_LARCH_{ADD, SUB}_ULEB128 relocation types (#81133)

Author: Jinyang He Date: 2024-03-12T17:44:48-07:00 New Revision: 78859f118a6b4c7b06c543c7794c59befdc78924 URL: https://github.com/llvm/llvm-project/commit/78859f118a6b4c7b06c543c7794c59befdc78924 DIFF: https://github.com/llvm/llvm-project/commit/78859f118a6b4c7b06c543c7794c59befdc78924.diff

[llvm-branch-commits] release/18.x: [lld][LoongArch] Support the R_LARCH_{ADD, SUB}_ULEB128 relocation types (#81133) (PR #83983)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/83983 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] release/18.x: [lld][LoongArch] Support the R_LARCH_{ADD, SUB}_ULEB128 relocation types (#81133) (PR #83983)

https://github.com/llvmbot closed https://github.com/llvm/llvm-project/pull/83983 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83834 >From 6d03789303fe3d5c84406df29353ddf63199eb08 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720)

[llvm-branch-commits] [mlir] release/18.x: [mlir][NFC] Apply rule of five to *Pass classes (#80998) (PR #83971)

tstellar wrote: I don't think we have tracked MLIR library ABI for previous releases, but I think this will change the ABI. Do we have a policy on this for MLIR? https://github.com/llvm/llvm-project/pull/83971 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/83911 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

tstellar wrote: Merged: d8352e93c1c8042d9166eab3d76d6c07ef585b6d https://github.com/llvm/llvm-project/pull/83911 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [compiler-rt] [compiler-rt] Allow running tests without installing first (PR #83088)

@@ -168,10 +169,45 @@ def push_dynamic_library_lookup_path(config, new_path): r"/i386(?=-[^/]+$)", "/x86_64", config.compiler_rt_libdir ) + +# Check if the test compiler resource dir matches the local build directory +# (which happens with

[llvm-branch-commits] [compiler-rt] [compiler-rt] Allow running tests without installing first (PR #83088)

https://github.com/delcypher edited https://github.com/llvm/llvm-project/pull/83088 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] [compiler-rt] Allow running tests without installing first (PR #83088)

https://github.com/delcypher approved this pull request. Thanks for addressing my feedback. I have a minor nit that you can address if you feel its worth it. When landing please make sure you squash your commits into a single commit and rewrite the commit message to be something that conforms

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Add test for aliasing miscompile fixed by #83017. NFC (PR #83856)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/83856 >From 10dcf50068b88e7f74d12d8c65e2a1ecbad472f5 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 28 Feb 2024 09:43:05 + Subject: [PATCH 1/2] [SelectionDAG] Change computeAliasing signature from optional

[llvm-branch-commits] [clang] Backport d23ef9e to release/18.x (PR #83911)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/83911 >From 74fa05dead4d52eef3c33406d05dd1bbaf10d546 Mon Sep 17 00:00:00 2001 From: Sirraide Date: Tue, 27 Feb 2024 20:19:44 +0100 Subject: [PATCH] [Clang] [Sema] Handle placeholders in '.*' expressions (#83103)

[llvm-branch-commits] [clang] d8352e9 - [Clang] [Sema] Handle placeholders in '.*' expressions (#83103)

Author: Sirraide Date: 2024-03-12T17:38:40-07:00 New Revision: d8352e93c1c8042d9166eab3d76d6c07ef585b6d URL: https://github.com/llvm/llvm-project/commit/d8352e93c1c8042d9166eab3d76d6c07ef585b6d DIFF: https://github.com/llvm/llvm-project/commit/d8352e93c1c8042d9166eab3d76d6c07ef585b6d.diff

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Fix crash when unrolling loop containing vector instructions (#83384) (PR #83744)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/83744 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] eb9bc02 - [RISCV] Fix crash when unrolling loop containing vector instructions (#83384)

Author: Shih-Po Hung Date: 2024-03-12T17:28:17-07:00 New Revision: eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f URL: https://github.com/llvm/llvm-project/commit/eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f DIFF: https://github.com/llvm/llvm-project/commit/eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f.diff

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Fix crash when unrolling loop containing vector instructions (#83384) (PR #83744)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/83744 >From eb9bc02b06cb07ffdd4c5ee55d6b6b591d78656f Mon Sep 17 00:00:00 2001 From: Shih-Po Hung Date: Sat, 2 Mar 2024 12:33:55 +0800 Subject: [PATCH] [RISCV] Fix crash when unrolling loop containing vector

[llvm-branch-commits] [lld] release/18.x: [ELF] Internalize enum (PR #83613)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/83613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] c3721c1 - [ELF] Internalize enum

Author: Fangrui Song Date: 2024-03-12T17:19:50-07:00 New Revision: c3721c1dcff5c2fa5e3b6916e369f5a499383c5a URL: https://github.com/llvm/llvm-project/commit/c3721c1dcff5c2fa5e3b6916e369f5a499383c5a DIFF: https://github.com/llvm/llvm-project/commit/c3721c1dcff5c2fa5e3b6916e369f5a499383c5a.diff

[llvm-branch-commits] [lld] release/18.x: [ELF] Internalize enum (PR #83613)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/83613 >From c3721c1dcff5c2fa5e3b6916e369f5a499383c5a Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 1 Mar 2024 11:17:22 -0800 Subject: [PATCH] [ELF] Internalize enum g++ -flto has a diagnostic `-Wodr` about

[llvm-branch-commits] [llvm-objcopy] --[de]compress-debug-sections: don't compress SHF_ALLOC sections, only decompress .debug sections (PR #84885)

https://github.com/MaskRay updated https://github.com/llvm/llvm-project/pull/84885 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-objcopy] --[de]compress-debug-sections: don't compress SHF_ALLOC sections, only decompress .debug sections (PR #84885)

https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/84885 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-objcopy] --[de]compress-debug-sections: don't compress SHF_ALLOC sections, only decompress .debug sections (PR #84885)

https://github.com/MaskRay updated https://github.com/llvm/llvm-project/pull/84885 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] release/18.x: Unbreak *tf builtins for hexfloat (#82208) (PR #82904)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/82904 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] c148795 - Unbreak *tf builtins for hexfloat (#82208)

Author: Alexander Richardson Date: 2024-03-12T17:13:57-07:00 New Revision: c14879562f46c9a5b24af8e21e8df0eef3079d4a URL: https://github.com/llvm/llvm-project/commit/c14879562f46c9a5b24af8e21e8df0eef3079d4a DIFF:

[llvm-branch-commits] [compiler-rt] release/18.x: Unbreak *tf builtins for hexfloat (#82208) (PR #82904)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/82904 >From c14879562f46c9a5b24af8e21e8df0eef3079d4a Mon Sep 17 00:00:00 2001 From: Alexander Richardson Date: Wed, 21 Feb 2024 12:59:56 -0800 Subject: [PATCH] Unbreak *tf builtins for hexfloat (#82208) This re-lands

[llvm-branch-commits] [llvm] 89d5432 - [AArch64] Skip over shadow space for ARM64EC entry thunk variadic calls (#80994)

Author: Billy Laws Date: 2024-03-11T14:29:51-07:00 New Revision: 89d543227a324d9925c68caf5d75c8c1e46c02a4 URL: https://github.com/llvm/llvm-project/commit/89d543227a324d9925c68caf5d75c8c1e46c02a4 DIFF: https://github.com/llvm/llvm-project/commit/89d543227a324d9925c68caf5d75c8c1e46c02a4.diff

[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/81800 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 42c599a - [AArch64] Fix generated types for ARM64EC variadic entry thunk targets (#80595)

Author: Billy Laws Date: 2024-03-11T14:29:51-07:00 New Revision: 42c599ab365b6d413d7e35a40f6e4ab98f523b67 URL: https://github.com/llvm/llvm-project/commit/42c599ab365b6d413d7e35a40f6e4ab98f523b67 DIFF: https://github.com/llvm/llvm-project/commit/42c599ab365b6d413d7e35a40f6e4ab98f523b67.diff

[llvm-branch-commits] [llvm] d7a9810 - [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

Author: Billy Laws Date: 2024-03-11T14:29:51-07:00 New Revision: d7a9810f9c14e6598265ab41519be9b861228450 URL: https://github.com/llvm/llvm-project/commit/d7a9810f9c14e6598265ab41519be9b861228450 DIFF: https://github.com/llvm/llvm-project/commit/d7a9810f9c14e6598265ab41519be9b861228450.diff

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [compiler-rt] [compiler-rt] Allow running tests without installing first (PR #83088)

https://github.com/vitalybuka approved this pull request. Looks like there are a bunch of CMAKE related patches from you. If possible, please try to land them with delay in-between for easier reverts if needed. https://github.com/llvm/llvm-project/pull/83088

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] Remove llvm_gtest dependency from unit tests (PR #83649)

https://github.com/vitalybuka approved this pull request. https://github.com/llvm/llvm-project/pull/83649 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [compiler-rt] Fix build race with COMPILER_RT_TEST_STANDALONE_BUILD_LIBS (PR #83650)

https://github.com/vitalybuka approved this pull request. https://github.com/llvm/llvm-project/pull/83650 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] Don't check COMPILER_RT_STANDALONE_BUILD for test deps (PR #83651)

https://github.com/vitalybuka approved this pull request. LGTM, but I bet we will brake some bots :) https://github.com/llvm/llvm-project/pull/83651 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The

[llvm-branch-commits] [clang][ubsan] Switch UBSAN optimization to `llvm.experimental.hot` (PR #84858)

https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/84858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang] support fir.alloca operations inside of omp reduction ops (PR #84952)

@@ -410,8 +410,15 @@ class FIROpConversion : public mlir::ConvertOpToLLVMPattern { mlir::ConversionPatternRewriter ) const { auto thisPt = rewriter.saveInsertionPoint(); mlir::Operation *parentOp = rewriter.getInsertionBlock()->getParentOp(); -mlir::Block

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -236,5 +238,37 @@ void alignAndPadAlloca(memtag::AllocaInfo , llvm::Align Alignment) { Info.AI = NewAI; } +Value *readRegister(IRBuilder<> , StringRef Name) { + Module *M = IRB.GetInsertBlock()->getParent()->getParent(); + Function *ReadRegister =

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -1246,32 +1244,16 @@ Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> , Type *Ty) { return nullptr; } -Value *HWAddressSanitizer::getPC(IRBuilder<> ) { - if (TargetTriple.getArch() == Triple::aarch64) -return readRegister(IRB, "pc"); - return

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

dpaoliello wrote: has been merged into master and cherry-picked here, so this is ready to land. > One thing we could consider is to skip .def file parser part of it. I'd rather not modify commits since they've already been tested in master

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

https://github.com/dpaoliello updated https://github.com/llvm/llvm-project/pull/84590 >From e84cbe53501ae106c25ca7233e48ad3c5daf539a Mon Sep 17 00:00:00 2001 From: Jacek Caban Date: Tue, 6 Feb 2024 13:47:58 +0100 Subject: [PATCH 1/4] [llvm-readobj][Object][COFF] Print COFF import library

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -236,5 +238,37 @@ void alignAndPadAlloca(memtag::AllocaInfo , llvm::Align Alignment) { Info.AI = NewAI; } +Value *readRegister(IRBuilder<> , StringRef Name) { + Module *M = IRB.GetInsertBlock()->getParent()->getParent(); + Function *ReadRegister =

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -236,5 +238,37 @@ void alignAndPadAlloca(memtag::AllocaInfo , llvm::Align Alignment) { Info.AI = NewAI; } +Value *readRegister(IRBuilder<> , StringRef Name) { + Module *M = IRB.GetInsertBlock()->getParent()->getParent(); + Function *ReadRegister =

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

@@ -1246,32 +1244,16 @@ Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> , Type *Ty) { return nullptr; } -Value *HWAddressSanitizer::getPC(IRBuilder<> ) { - if (TargetTriple.getArch() == Triple::aarch64) -return readRegister(IRB, "pc"); - return

[llvm-branch-commits] [flang] [flang][OpenMP] Convert repeatable clauses (except Map) in ClauseProc… (PR #81623)

https://github.com/kparzysz edited https://github.com/llvm/llvm-project/pull/81623 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang][OpenMP] Convert repeatable clauses (except Map) in ClauseProc… (PR #81623)

@@ -181,45 +172,41 @@ genDependKindAttr(fir::FirOpBuilder , pbKind); } -static mlir::Value getIfClauseOperand( -Fortran::lower::AbstractConverter , -const Fortran::parser::OmpClause::If *ifClause, -

[llvm-branch-commits] [flang] [flang][OpenMP] Convert repeatable clauses (except Map) in ClauseProc… (PR #81623)

https://github.com/kparzysz edited https://github.com/llvm/llvm-project/pull/81623 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang][OpenMP] Convert repeatable clauses (except Map) in ClauseProc… (PR #81623)

@@ -181,45 +172,41 @@ genDependKindAttr(fir::FirOpBuilder , pbKind); } -static mlir::Value getIfClauseOperand( -Fortran::lower::AbstractConverter , -const Fortran::parser::OmpClause::If *ifClause, -

[llvm-branch-commits] [flang] [flang][OpenMP] Convert repeatable clauses (except Map) in ClauseProc… (PR #81623)

@@ -87,50 +87,44 @@ getSimdModifier(const omp::clause::Schedule ) { static void genAllocateClause(Fortran::lower::AbstractConverter , - const Fortran::parser::OmpAllocateClause , + const omp::clause::Allocate ,

[llvm-branch-commits] [clang] release/18x: [clang] Avoid -Wshadow warning when init-capture named same as class … (PR #84912)

sheredom wrote: Yeah indeed - its not a clang 17 regression. It's a _clang 16_ regression. At the minute we're holding our internal compiler toolchain on clang 16, and for our users we've got to special case disable the warning entirely for clang 17.

[llvm-branch-commits] [clang] release/18x: [clang] Avoid -Wshadow warning when init-capture named same as class … (PR #84912)

erichkeane wrote: As far as I can tell, this isn't fixing a regression in Clang17, and thus isn't really a candidate for inclusion into the 18.x branches. https://github.com/llvm/llvm-project/pull/84912 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

https://github.com/nikic closed https://github.com/llvm/llvm-project/pull/84491 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

https://github.com/nikic edited https://github.com/llvm/llvm-project/pull/83834 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

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