date:20120712

Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

2012-07-12 Thread Zhao, Halley

Hi Ian:
There is no other comments for these patches, could you help me commit it to 
git tree?

Thanks.


 -Original Message-
 From: Zhao, Halley
 Sent: Monday, July 09, 2012 1:55 PM
 To: mesa-dev@lists.freedesktop.org
 Cc: Zhao, Halley
 Subject: [PATCH 00/11] Add YUYV format support of dri image
 
 Intel SNB/IVB platform supports rendering YUYV buffer to overlay plane,
 however YUYV is missing support from mesa/dri-image yet.
 so I go ahead to add it; basing on it, libva can send YUYV buffer directly to
 wayland/weston, then weston output it to overlay plane.
 
 v2 update:
 - set internal_format to GL_YCBCR_MESA
 - improve gbm/intel-driver to support YUYV bo generation,
   add handle2 (intel buffer name) in gbm
   buffer data update (intel_image_write with tiling support)
 - update test case to depend on gbm instead of intel driver directly
 
 v3 update:
 - move wayland-drm-test to
 $mesa/src/egl/wayland/wayland-drm/drm-test-client
 - add YUYV support to
 eglCreateDRMImageMesa/eglExportDRMImageMesa
   and eglCreateImageKHR
 - add egl-create-drm-image test to piglit
 
 v4 update:
 - gbm: change gbm_bo_get_handle2() to gbm_bo_get_shared_handle(),
 - gbm: allocate region name only when it is asked
 - drm-test-client update according to above change:
 gbm_bo_get_shared_handle
 
 v5 update:
 - rebase to latest git tree for check in, 0002/0003 patches are updated.
 
 
 Zhao Halley (10):
   GL: add YUYV to dri image format
   intel: add YUYV format for dri images
   egl wayland: add YUYV support
   gallium egl wayland: add YUYV support
   gbm dri backend: add YUYV support
   wayland-drm: add YUYV support
   gbm: add shared_handle(drm buffer region name)
   intel driver: dri image write update
   test: test case drm-test-client in src/egl/wayland/wayland-drm
   EGL: add YUYV support to eglCreateImageKHR and
 eglCreateDRMImageMESA
 
  include/EGL/eglmesaext.h   |3 +
  include/GL/internal/dri_interface.h|1 +
  src/egl/drivers/dri2/egl_dri2.c|9 +-
  src/egl/drivers/dri2/platform_wayland.c|7 +-
  src/egl/wayland/wayland-drm/Makefile.am|   15 +-
  src/egl/wayland/wayland-drm/drm-test-client.c  |  456
 
  src/egl/wayland/wayland-drm/wayland-drm.c  |3 +
  .../state_trackers/egl/wayland/native_drm.c|3 +
  .../state_trackers/egl/wayland/native_wayland.h|3 +-
  src/gbm/backends/dri/gbm_dri.c |   22 +
  src/gbm/main/gbm.c |   18 +
  src/gbm/main/gbm.h |8 +-
  src/gbm/main/gbmint.h  |2 +
  src/mesa/drivers/dri/intel/intel_screen.c  |   20 +-
  src/mesa/drivers/dri/intel/intel_tex_image.c   |6 +
  15 files changed, 569 insertions(+), 7 deletions(-)  mode change 100644 =
 100755 include/EGL/eglext.h  mode change 100644 = 100755
 include/EGL/eglmesaext.h  mode change 100644 = 100755
 include/GL/internal/dri_interface.h
  mode change 100644 = 100755 src/egl/drivers/dri2/platform_wayland.c
  create mode 100755 src/egl/wayland/wayland-drm/drm-test-client.c
  mode change 100644 = 100755
 src/egl/wayland/wayland-drm/wayland-drm.c
  mode change 100644 = 100755
 src/gallium/state_trackers/egl/wayland/native_drm.c
  mode change 100644 = 100755
 src/gallium/state_trackers/egl/wayland/native_wayland.h
  mode change 100644 = 100755 src/gbm/backends/dri/gbm_dri.c  mode
 change 100644 = 100755 src/gbm/main/gbm.c  mode change 100644 =
 100755 src/gbm/main/gbm.h  mode change 100644 = 100755
 src/gbm/main/gbmint.h  mode change 100644 = 100755
 src/mesa/drivers/dri/intel/intel_screen.c
  mode change 100644 = 100755 src/mesa/drivers/dri/intel/intel_tex_image.c
 
 --
 1.7.4.1

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Re: [Mesa-dev] Mesa (master): docs: Update GL3.txt.

2012-07-12 Thread Bryan Cain

On 07/11/2012 12:24 AM, Eric Anholt wrote:
 Kenneth Graunke k...@kemper.freedesktop.org writes:
 inverse() has been done for a while.
 Does the inverse() builtin constant expression handling work for
 you?  It doesn't here.

 None of us know what highp change means;
 GLSL 1.40 spec: Make the default precision qualification for fragment
 shader be high. -- it was also on our task list.

Like the commit message said, precision qualifiers are entirely ignored
by the GLSL compiler - they don't even make it to the IR stage.  So
there's no such thing as a default here since it doesn't have a value
at all for any variable in the IR.


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[Mesa-dev] Mesa 8.0 regression - two bugs

2012-07-12 Thread Deve


Hi!

I'm writing about two bugs which I see on 8.0 - now 8.0.4 version of 
mesa. It was OK on mesa 7.11.2, after upgrade to 8.0 is problem.


First is starting movie in Sims 3 run by Wine. It runs VERY slow. The 
later part of game runs ok. Example:

http://imageshack.us/clip/my-videos/444/f5f.mp4/
Problem is with other games too, for example with transparency object.

Other problem is with Super Tux Kart game. It's only with enabled pixel 
shaders. Edge of screen looks badly. Example:

http://desmond.imageshack.us/Himg443/scaled.php?server=443filename=screen1eipng.jpgres=landing
http://desmond.imageshack.us/Himg515/scaled.php?server=515filename=screen2kipng.jpgres=landing

I don't have enough skills to do solid bug report so I'm writing to 
mailing list. If you want, you can write to mi what information you need 
and how it to do.



Lastest working version: 7.11.2
OS Debian Wheezy/Sid
Intel 965GM Chipset
Intel drivers 2.19.0
Kernel 3.2.21
libc6 2.13
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Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

2012-07-12 Thread Gwenole Beauchesne

Hi Halley,

2012/7/12 Zhao, Halley halley.z...@intel.com:

 There is no other comments for these patches, could you help me commit it to 
 git tree?

Please rebase against current git master tree. YUV support, including
YUYV was added. The remaining patchset should reduce to the GBM bits.

Thanks,
Gwenole.
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[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

2012-07-12 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=51972

Michel Dänzer mic...@daenzer.net changed:

   What|Removed |Added

  Attachment #64118|text/x-log  |text/plain
  mime type||

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[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

2012-07-12 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=51972

--- Comment #3 from Michel Dänzer mic...@daenzer.net 2012-07-12 08:04:47 PDT 
---
The below looks like your system environment for 32 bit compilation is broken.

configure:20439: checking expat.h usability
configure:20439: gcc -c -g -O2 -Wall -std=c99
-Werror=implicit-function-declaration -Werror=missing-prototypes
-fno-strict-aliasing -fno-builtin-memcmp -m32  conftest.c 5
In file included from /usr/include/stdio.h:28:0,
 from conftest.c:24:
/usr/include/features.h:323:26: fatal error: bits/predefs.h: No such file or
directory

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[Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

2012-07-12 Thread Marek Olšák

This was not implemented, because the spec was changed just recently.

Everything has been in place already.

Gallium has PIPE_FORMAT_B5G6R5_UNORM, while Mesa has MESA_FORMAT_RGB565.
---
 src/mesa/main/fbobject.c  |3 +++
 src/mesa/main/image.c |1 +
 src/mesa/main/texformat.c |   10 ++
 src/mesa/main/teximage.c  |9 +
 src/mesa/state_tracker/st_cb_drawpixels.c |2 ++
 src/mesa/state_tracker/st_format.c|4 
 6 files changed, 29 insertions(+)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index cfaea62..4370c72 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1296,6 +1296,9 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum 
internalFormat)
 
case GL_RGB10_A2UI:
   return ctx-Extensions.ARB_texture_rgb10_a2ui ? GL_RGBA : 0;
+
+   case GL_RGB565:
+  return ctx-Extensions.ARB_ES2_compatibility ? GL_RGB : 0;
default:
   return 0;
}
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
index b6c2645..678dfeb 100644
--- a/src/mesa/main/image.c
+++ b/src/mesa/main/image.c
@@ -770,6 +770,7 @@ _mesa_is_color_format(GLenum format)
   case GL_R3_G3_B2:
   case GL_RGB4:
   case GL_RGB5:
+  case GL_RGB565:
   case GL_RGB8:
   case GL_RGB10:
   case GL_RGB12:
diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c
index 5fdc2ab..26bcbc1 100644
--- a/src/mesa/main/texformat.c
+++ b/src/mesa/main/texformat.c
@@ -258,6 +258,16 @@ _mesa_choose_tex_format( struct gl_context *ctx, GLint 
internalFormat,
  ; /* fallthrough */
}
 
+   if (ctx-Extensions.ARB_ES2_compatibility) {
+  switch (internalFormat) {
+ case GL_RGB565:
+RETURN_IF_SUPPORTED(MESA_FORMAT_RGB565);
+break;
+ default:
+ ; /* fallthrough */
+  }
+   }
+
if (ctx-Extensions.MESA_ycbcr_texture) {
   if (internalFormat == GL_YCBCR_MESA) {
  if (type == GL_UNSIGNED_SHORT_8_8_MESA)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index b16baaf..126386e 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -138,6 +138,15 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint 
internalFormat )
   }
}
 
+   if (ctx-Extensions.ARB_ES2_compatibility) {
+  switch (internalFormat) {
+ case GL_RGB565:
+return GL_RGB;
+ default:
+; /* fallthrough */
+  }
+   }
+
if (ctx-Extensions.ARB_depth_texture) {
   switch (internalFormat) {
  case GL_DEPTH_COMPONENT:
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 10eaa84..c5f3631 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -403,6 +403,8 @@ internal_format(struct gl_context *ctx, GLenum format, 
GLenum type)
 
  case GL_UNSIGNED_SHORT_5_6_5:
  case GL_UNSIGNED_SHORT_5_6_5_REV:
+return GL_RGB565;
+
  case GL_UNSIGNED_SHORT_5_5_5_1:
  case GL_UNSIGNED_SHORT_1_5_5_5_REV:
 return GL_RGB5_A1;
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index 4265d14..57d3441 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -793,6 +793,10 @@ static const struct format_mapping format_map[] = {
   { PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
 DEFAULT_RGBA_FORMATS }
},
+   {
+  { GL_RGB565 },
+  { PIPE_FORMAT_B5G6R5_UNORM, DEFAULT_RGBA_FORMATS }
+   },
 
/* basic Alpha formats */
{
-- 
1.7.9.5

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Re: [Mesa-dev] [PATCH 5/5] i965/fs: Make register spill/unspill only do the regs for that instruction.

2012-07-12 Thread Kenneth Graunke


On 07/09/2012 03:40 PM, Eric Anholt wrote:

Previously, if we were spilling the result of a texture call, we would store
all 4 regs, then for each use of one of those regs as the source of an
instruction, we would unspill all 4 regs even though only one was needed.

In an app we're looking at, one shader goes from 2817 instructions to 2179,
and another one successfully compiles that didn't before.
---
  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |   56 ++---
  1 file changed, 28 insertions(+), 28 deletions(-)


When reading this, I was confused because I was expecting things to go 
from size down to 1.  But it doesn't, it goes to 
inst-regs_written()...since an instruction might write more than one 
register, but not the whole thing.


This looks OK to me.  Nice to not be overzealously spilling.

One comment below, but other than that:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org


diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 3f10ca6..ebf5eaa 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -281,24 +281,17 @@ fs_visitor::assign_regs()
  void
  fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst, uint32_t spill_offset)
  {
-   int size = virtual_grf_sizes[dst.reg];
-   dst.reg_offset = 0;
-
-   for (int chan = 0; chan  size; chan++) {
-  fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL,
-  dst);
-  dst.reg_offset++;
-  unspill_inst-offset = spill_offset + chan * REG_SIZE;
-  unspill_inst-ir = inst-ir;
-  unspill_inst-annotation = inst-annotation;
-
-  /* Choose a MRF that won't conflict with an MRF that's live across the
-   * spill.  Nothing else will make it up to MRF 14/15.
-   */
-  unspill_inst-base_mrf = 14;
-  unspill_inst-mlen = 1; /* header contains offset */
-  inst-insert_before(unspill_inst);
-   }
+   fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL, dst);
+   unspill_inst-offset = spill_offset;
+   unspill_inst-ir = inst-ir;
+   unspill_inst-annotation = inst-annotation;
+
+   /* Choose a MRF that won't conflict with an MRF that's live across the
+* spill.  Nothing else will make it up to MRF 14/15.
+*/
+   unspill_inst-base_mrf = 14;
+   unspill_inst-mlen = 1; /* header contains offset */
+   inst-insert_before(unspill_inst);
  }

  int
@@ -322,14 +315,12 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)

for (unsigned int i = 0; i  3; i++) {
 if (inst-src[i].file == GRF) {
-   int size = virtual_grf_sizes[inst-src[i].reg];
-   spill_costs[inst-src[i].reg] += size * loop_scale;
+   spill_costs[inst-src[i].reg] += loop_scale;
 }
}

if (inst-dst.file == GRF) {
-int size = virtual_grf_sizes[inst-dst.reg];
-spill_costs[inst-dst.reg] += size * loop_scale;
+spill_costs[inst-dst.reg] += inst-regs_written() * loop_scale;
}

switch (inst-opcode) {
@@ -384,21 +375,30 @@ fs_visitor::spill_reg(int spill_reg)
for (unsigned int i = 0; i  3; i++) {
 if (inst-src[i].file == GRF 
 inst-src[i].reg == spill_reg) {
-   inst-src[i].reg = virtual_grf_alloc(size);
-   emit_unspill(inst, inst-src[i], spill_offset);
+   inst-src[i].reg = virtual_grf_alloc(1);
+   emit_unspill(inst, inst-src[i],
+ spill_offset + REG_SIZE * inst-src[i].reg_offset);
 }
}

if (inst-dst.file == GRF 
  inst-dst.reg == spill_reg) {
-inst-dst.reg = virtual_grf_alloc(size);
+ int subset_spill_offset = (spill_offset +
+REG_SIZE * inst-dst.reg_offset);
+ inst-dst.reg = virtual_grf_alloc(inst-regs_written());
+ inst-dst.reg_offset = 0;

 /* Since we spill/unspill the whole thing even if we access
  * just a component, we may need to unspill before the
  * instruction we're spilling for.
  */


This comment isn't really true anymore.


 if (size != 1 || inst-predicated) {
-   emit_unspill(inst, inst-dst, spill_offset);
+fs_reg unspill_reg = inst-dst;
+for (int chan = 0; chan  inst-regs_written(); chan++) {
+   emit_unspill(inst, unspill_reg,
+subset_spill_offset + REG_SIZE * chan);
+   unspill_reg.reg_offset++;
+}
 }

 fs_reg spill_src = inst-dst;
@@ -407,11 +407,11 @@ fs_visitor::spill_reg(int spill_reg)
 spill_src.negate = false;
 spill_src.smear = -1;

-for (int chan = 0; chan  size; chan++) {
+for (int chan = 0; chan  inst-regs_written(); chan++) {
fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,

Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

2012-07-12 Thread Kenneth Graunke


On 07/12/2012 05:25 AM, Marek Olšák wrote:

This was not implemented, because the spec was changed just recently.

Everything has been in place already.

Gallium has PIPE_FORMAT_B5G6R5_UNORM, while Mesa has MESA_FORMAT_RGB565.


Oh wow, I didn't realize this was missing.  These changes look good to me.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

One question: should it be ctx-Extensions.ARB_ES2_compatibility || 
ctx-API == API_OPENGLES2?  I suspect most drivers that support ES2 will 
also support ARB_ES2_compatibility, so it shouldn't be a big deal in 
practice, but...



---
  src/mesa/main/fbobject.c  |3 +++
  src/mesa/main/image.c |1 +
  src/mesa/main/texformat.c |   10 ++
  src/mesa/main/teximage.c  |9 +
  src/mesa/state_tracker/st_cb_drawpixels.c |2 ++
  src/mesa/state_tracker/st_format.c|4 
  6 files changed, 29 insertions(+)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index cfaea62..4370c72 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1296,6 +1296,9 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum 
internalFormat)

 case GL_RGB10_A2UI:
return ctx-Extensions.ARB_texture_rgb10_a2ui ? GL_RGBA : 0;
+
+   case GL_RGB565:
+  return ctx-Extensions.ARB_ES2_compatibility ? GL_RGB : 0;
 default:
return 0;
 }
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
index b6c2645..678dfeb 100644
--- a/src/mesa/main/image.c
+++ b/src/mesa/main/image.c
@@ -770,6 +770,7 @@ _mesa_is_color_format(GLenum format)
case GL_R3_G3_B2:
case GL_RGB4:
case GL_RGB5:
+  case GL_RGB565:
case GL_RGB8:
case GL_RGB10:
case GL_RGB12:
diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c
index 5fdc2ab..26bcbc1 100644
--- a/src/mesa/main/texformat.c
+++ b/src/mesa/main/texformat.c
@@ -258,6 +258,16 @@ _mesa_choose_tex_format( struct gl_context *ctx, GLint 
internalFormat,
   ; /* fallthrough */
 }

+   if (ctx-Extensions.ARB_ES2_compatibility) {
+  switch (internalFormat) {
+ case GL_RGB565:
+RETURN_IF_SUPPORTED(MESA_FORMAT_RGB565);
+break;
+ default:
+ ; /* fallthrough */
+  }
+   }
+
 if (ctx-Extensions.MESA_ycbcr_texture) {
if (internalFormat == GL_YCBCR_MESA) {
   if (type == GL_UNSIGNED_SHORT_8_8_MESA)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index b16baaf..126386e 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -138,6 +138,15 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint 
internalFormat )
}
 }

+   if (ctx-Extensions.ARB_ES2_compatibility) {
+  switch (internalFormat) {
+ case GL_RGB565:
+return GL_RGB;
+ default:
+; /* fallthrough */
+  }
+   }
+
 if (ctx-Extensions.ARB_depth_texture) {
switch (internalFormat) {
   case GL_DEPTH_COMPONENT:
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 10eaa84..c5f3631 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -403,6 +403,8 @@ internal_format(struct gl_context *ctx, GLenum format, 
GLenum type)

   case GL_UNSIGNED_SHORT_5_6_5:
   case GL_UNSIGNED_SHORT_5_6_5_REV:
+return GL_RGB565;
+
   case GL_UNSIGNED_SHORT_5_5_5_1:
   case GL_UNSIGNED_SHORT_1_5_5_5_REV:
  return GL_RGB5_A1;
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index 4265d14..57d3441 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -793,6 +793,10 @@ static const struct format_mapping format_map[] = {
{ PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
  DEFAULT_RGBA_FORMATS }
 },
+   {
+  { GL_RGB565 },
+  { PIPE_FORMAT_B5G6R5_UNORM, DEFAULT_RGBA_FORMATS }
+   },

 /* basic Alpha formats */
 {




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Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

2012-07-12 Thread Ian Romanick


On 07/11/2012 10:47 PM, Zhao, Halley wrote:

Hi Ian:
There is no other comments for these patches, could you help me commit it to 
git tree?


I haven't seen any Reviewed-by or Acked-by messages.  This is a requirement.


Thanks.



-Original Message-
From: Zhao, Halley
Sent: Monday, July 09, 2012 1:55 PM
To: mesa-dev@lists.freedesktop.org
Cc: Zhao, Halley
Subject: [PATCH 00/11] Add YUYV format support of dri image

Intel SNB/IVB platform supports rendering YUYV buffer to overlay plane,
however YUYV is missing support from mesa/dri-image yet.
so I go ahead to add it; basing on it, libva can send YUYV buffer directly to
wayland/weston, then weston output it to overlay plane.

v2 update:
 - set internal_format to GL_YCBCR_MESA
 - improve gbm/intel-driver to support YUYV bo generation,
   add handle2 (intel buffer name) in gbm
   buffer data update (intel_image_write with tiling support)
 - update test case to depend on gbm instead of intel driver directly

v3 update:
 - move wayland-drm-test to
$mesa/src/egl/wayland/wayland-drm/drm-test-client
 - add YUYV support to
eglCreateDRMImageMesa/eglExportDRMImageMesa
   and eglCreateImageKHR
 - add egl-create-drm-image test to piglit

v4 update:
 - gbm: change gbm_bo_get_handle2() to gbm_bo_get_shared_handle(),
 - gbm: allocate region name only when it is asked
 - drm-test-client update according to above change:
gbm_bo_get_shared_handle

v5 update:
 - rebase to latest git tree for check in, 0002/0003 patches are updated.


Zhao Halley (10):
   GL: add YUYV to dri image format
   intel: add YUYV format for dri images
   egl wayland: add YUYV support
   gallium egl wayland: add YUYV support
   gbm dri backend: add YUYV support
   wayland-drm: add YUYV support
   gbm: add shared_handle(drm buffer region name)
   intel driver: dri image write update
   test: test case drm-test-client in src/egl/wayland/wayland-drm
   EGL: add YUYV support to eglCreateImageKHR and
eglCreateDRMImageMESA

  include/EGL/eglmesaext.h   |3 +
  include/GL/internal/dri_interface.h|1 +
  src/egl/drivers/dri2/egl_dri2.c|9 +-
  src/egl/drivers/dri2/platform_wayland.c|7 +-
  src/egl/wayland/wayland-drm/Makefile.am|   15 +-
  src/egl/wayland/wayland-drm/drm-test-client.c  |  456

  src/egl/wayland/wayland-drm/wayland-drm.c  |3 +
  .../state_trackers/egl/wayland/native_drm.c|3 +
  .../state_trackers/egl/wayland/native_wayland.h|3 +-
  src/gbm/backends/dri/gbm_dri.c |   22 +
  src/gbm/main/gbm.c |   18 +
  src/gbm/main/gbm.h |8 +-
  src/gbm/main/gbmint.h  |2 +
  src/mesa/drivers/dri/intel/intel_screen.c  |   20 +-
  src/mesa/drivers/dri/intel/intel_tex_image.c   |6 +
  15 files changed, 569 insertions(+), 7 deletions(-)  mode change 100644 =
100755 include/EGL/eglext.h  mode change 100644 = 100755
include/EGL/eglmesaext.h  mode change 100644 = 100755
include/GL/internal/dri_interface.h
  mode change 100644 = 100755 src/egl/drivers/dri2/platform_wayland.c
  create mode 100755 src/egl/wayland/wayland-drm/drm-test-client.c
  mode change 100644 = 100755
src/egl/wayland/wayland-drm/wayland-drm.c
  mode change 100644 = 100755
src/gallium/state_trackers/egl/wayland/native_drm.c
  mode change 100644 = 100755
src/gallium/state_trackers/egl/wayland/native_wayland.h
  mode change 100644 = 100755 src/gbm/backends/dri/gbm_dri.c  mode
change 100644 = 100755 src/gbm/main/gbm.c  mode change 100644 =
100755 src/gbm/main/gbm.h  mode change 100644 = 100755
src/gbm/main/gbmint.h  mode change 100644 = 100755
src/mesa/drivers/dri/intel/intel_screen.c
  mode change 100644 = 100755 src/mesa/drivers/dri/intel/intel_tex_image.c

--
1.7.4.1





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[Mesa-dev] [PATCH 0/7] i965/blorp: Improvements to the blorp engine for Gen7.

2012-07-12 Thread Paul Berry

This patch series makes three improvements to the blorp engine (which
does MSAA resolves and other blits) for Gen7:

Patches 1-3 fix downsampling of integer format framebuffers on Gen7,
by using the AVG instruction to average the samples, rather than
adding the samples and performing a division.  This is necessary to
avoid overflow with 32-bit integer buffers.  In the process, we
rearrange the order of adds/averages to reduce the accumulation of
numerical errors (patch 2).

Patch 4 adds an optimization to the MSAA resolve when using Gen7's CMS
MSAA layout: when the MCS buffer indicates that all samples
corresponding to a given pixel contain the same color value, we don't
have to load all the samples and average them; we just load the first
sample and use its value.

Patches 5-7 make blorp take advantage of the 3D pipeline's ability to
decode the IMS MSAA layout when reading from depth and stencil
textures.  Previously blorp would emit extra shader instructions to
account for the IMS MSAA layout.  This change should make blits from
multisampled depth and stencil buffers more efficient.

[PATCH 1/7] i965: Add support for AVG instruction.
[PATCH 2/7] i965/blorp: Modify manual_blend() to avoid unnecessary loss of 
precision.
[PATCH 3/7] i965/blorp: Fix integer downsampling on Gen7.
[PATCH 4/7] i965/blorp: Optimize manual_blend() for compressed multisampled 
surfaces.
[PATCH 5/7] i965/blorp: Configure SURFACE_STATE correctly for IMS surfaces.
[PATCH 6/7] i965/blorp: Loosen assertions in compute_msaa_layout_for_pipeline.
[PATCH 7/7] i965/blorp: Use IMS layout when texturing from depth/stencil 
surfaces.
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[Mesa-dev] [PATCH 1/7] i965: Add support for AVG instruction.

2012-07-12 Thread Paul Berry

From the Ivy Bridge PRM, Vol4 Part3 p152:

The avg instruction performs component-wise integer average of
src0 and src1 and stores the results in dst. An integer average
uses integer upward rounding. It is equivalent to increment one to
the addition of src0 and src1 and then apply an arithmetic right
shift to this intermediate value.
---
 src/mesa/drivers/dri/i965/brw_eu.h  |1 +
 src/mesa/drivers/dri/i965/brw_eu_emit.c |   22 ++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index f25b09d..233b94c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -861,6 +861,7 @@ ALU2(RSL)
 ALU2(ASR)
 ALU2(JMPI)
 ALU2(ADD)
+ALU2(AVG)
 ALU2(MUL)
 ALU1(FRC)
 ALU1(RNDD)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 8de872e..93e84ae 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -929,6 +929,28 @@ struct brw_instruction *brw_ADD(struct brw_compile *p,
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
 }
 
+struct brw_instruction *brw_AVG(struct brw_compile *p,
+struct brw_reg dest,
+struct brw_reg src0,
+struct brw_reg src1)
+{
+   assert(dest.type == src0.type);
+   assert(src0.type == src1.type);
+   switch (src0.type) {
+   case BRW_REGISTER_TYPE_B:
+   case BRW_REGISTER_TYPE_UB:
+   case BRW_REGISTER_TYPE_W:
+   case BRW_REGISTER_TYPE_UW:
+   case BRW_REGISTER_TYPE_D:
+   case BRW_REGISTER_TYPE_UD:
+  break;
+   default:
+  assert(!Bad type for brw_AVG);
+   }
+
+   return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
+}
+
 struct brw_instruction *brw_MUL(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg src0,
-- 
1.7.7.6

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[Mesa-dev] [PATCH 2/7] i965/blorp: Modify manual_blend() to avoid unnecessary loss of precision.

2012-07-12 Thread Paul Berry

When downsampling from an MSAA image to a single-sampled image, it is
inevitable that some loss of numerical precision will occur, since we
have to use 32-bit floating point registers to hold the intermediate
results while blending.  However, it seems reasonable to expect that
when all samples corresponding to a given pixel have the exact same
color value, there will be no loss of precision.

Previously, we averaged samples as follows:

blend = (((sample[0] + sample[1]) + sample[2]) + sample[3]) / 4

This had the potential to lose numerical precision when all samples
have the same color value, since ((sample[0] + sample[1]) + sample[2])
may not be precisely representable as a 32-bit float, even if the
individual samples are.

This patch changes the formula to:

blend = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4

This avoids any loss of precision in the event that all samples are
the same, by ensuring that each addition operation adds two equal
values.

As a side benefit, this puts the formula in the form we will need in
order to implement correct blending of integer formats.
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |  117 --
 1 files changed, 90 insertions(+), 27 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 6954733..74ae52d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -434,6 +434,11 @@ private:
const sampler_message_arg *args, int num_args);
void render_target_write();
 
+   /**
+* Base-2 logarithm of the maximum number of samples that can be blended.
+*/
+   static const unsigned LOG2_MAX_BLEND_SAMPLES = 2;
+
void *mem_ctx;
struct brw_context *brw;
const brw_blorp_blit_prog_key *key;
@@ -455,13 +460,8 @@ private:
   struct brw_reg offset;
} x_transform, y_transform;
 
-   /* Data to be written to render target (4 vec16's) */
-   struct brw_reg result;
-
-   /* Auxiliary storage for data returned by a sampling operation when
-* blending (4 vec16's)
-*/
-   struct brw_reg texture_data;
+   /* Data read from texture (4 vec16's per array element) */
+   struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1];
 
/* Auxiliary storage for the contents of the MCS surface.
 *
@@ -622,7 +622,7 @@ brw_blorp_blit_program::compile(struct brw_context *brw,
   if (brw-intel.gen == 6) {
  /* Gen6 hardware an automatically blend using the SAMPLE message */
  single_to_blend();
- sample(result);
+ sample(texture_data[0]);
   } else {
  /* Gen7+ hardware doesn't automaticaly blend. */
  manual_blend();
@@ -656,7 +656,7 @@ brw_blorp_blit_program::compile(struct brw_context *brw,
*/
   if (key-tex_layout == INTEL_MSAA_LAYOUT_CMS)
  mcs_fetch();
-  texel_fetch(result);
+  texel_fetch(texture_data[0]);
}
 
/* Finally, write the fetched (or blended) value to the render target and
@@ -695,8 +695,9 @@ brw_blorp_blit_program::alloc_regs()
prog_data.first_curbe_grf = reg;
alloc_push_const_regs(reg);
reg += BRW_BLORP_NUM_PUSH_CONST_REGS;
-   this-result = vec16(brw_vec8_grf(reg, 0)); reg += 8;
-   this-texture_data = vec16(brw_vec8_grf(reg, 0)); reg += 8;
+   for (unsigned i = 0; i  ARRAY_SIZE(texture_data); ++i) {
+  this-texture_data[i] = vec16(brw_vec8_grf(reg, 0)); reg += 8;
+   }
this-mcs_data =
   retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8;
for (int i = 0; i  2; ++i) {
@@ -711,6 +712,9 @@ brw_blorp_blit_program::alloc_regs()
this-t1 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
this-t2 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
 
+   /* Make sure we didn't run out of registers */
+   assert(reg = GEN7_MRF_HACK_START);
+
int mrf = 2;
this-base_mrf = mrf;
 }
@@ -1061,6 +1065,24 @@ brw_blorp_blit_program::single_to_blend()
SWAP_XY_AND_XPYP();
 }
 
+
+/**
+ * Count the number of trailing 1 bits in the given value.  For example:
+ *
+ * count_trailing_one_bits(0) == 0
+ * count_trailing_one_bits(7) == 3
+ * count_trailing_one_bits(11) == 2
+ */
+inline int count_trailing_one_bits(unsigned value)
+{
+#if defined(__GNUC__)  ((__GNUC__ * 100 + __GNUC_MINOR__) = 304) /* gcc 3.4 
or later */
+   return __builtin_ctz(~value);
+#else
+   return _mesa_bitcount(value  ~(value + 1));
+#endif
+}
+
+
 void
 brw_blorp_blit_program::manual_blend()
 {
@@ -1070,27 +1092,68 @@ brw_blorp_blit_program::manual_blend()
if (key-tex_layout == INTEL_MSAA_LAYOUT_CMS)
   mcs_fetch();
 
-   /* Gather sample 0 data first */
-   s_is_zero = true;
-   texel_fetch(result);
-
-   /* Gather data for remaining samples and accumulate it into result. */
-   s_is_zero = false;
-   for (int i = 1; i  num_samples; ++i) {
-  brw_MOV(func, S, brw_imm_uw(i));
-  texel_fetch(texture_data);
-
-

[Mesa-dev] [PATCH 3/7] i965/blorp: Fix integer downsampling on Gen7.

2012-07-12 Thread Paul Berry

When downsampling an integer-format buffer on Gen7, we need to use the
avg instruction rather than the add instruction, to ensure that we
don't overflow the range of 32-bit integers.  Also, we need to use the
proper register type (BRW_REGISTER_TYPE_D or BRW_REGISTER_TYPE_UD) for
intermediate color data and for writing to the render target.

Note: this patch causes blorp to use the proper register type for all
operations (downsampling, upsampling, and ordinary blits).  Strictly
speaking, this is only necessary for downsampling, because the other
operations exclusively use MOV instructions on the color data.  But
it's simpler to use the proper register type in all cases.
---
 src/mesa/drivers/dri/i965/brw_blorp.h|5 ++
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |   61 +-
 2 files changed, 55 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 053eef7..9af492d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -223,6 +223,11 @@ struct brw_blorp_blit_prog_key
/* Actual MSAA layout used by the destination image. */
intel_msaa_layout dst_layout;
 
+   /* Type of the data to be read from the texture (one of
+* BRW_REGISTER_TYPE_{UD,D,F}).
+*/
+   unsigned texture_data_type;
+
/* True if the source image is W tiled.  If true, the surface state for the
 * source image must be configured as Y tiled, and tex_samples must be 0.
 */
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 74ae52d..32fd48e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -696,7 +696,9 @@ brw_blorp_blit_program::alloc_regs()
alloc_push_const_regs(reg);
reg += BRW_BLORP_NUM_PUSH_CONST_REGS;
for (unsigned i = 0; i  ARRAY_SIZE(texture_data); ++i) {
-  this-texture_data[i] = vec16(brw_vec8_grf(reg, 0)); reg += 8;
+  this-texture_data[i] =
+ retype(vec16(brw_vec8_grf(reg, 0)), key-texture_data_type);
+  reg += 8;
}
this-mcs_data =
   retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8;
@@ -1117,7 +1119,16 @@ brw_blorp_blit_program::manual_blend()
 * operations we do is equal to the number of trailing 1 bits in i.  This
 * works provided the total number of samples is a power of two, which it
 * always is for i965.
+*
+* For integer formats, we replace the add operations with average
+* operations and skip the final division.
 */
+   typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *,
+  struct brw_reg,
+  struct brw_reg,
+  struct brw_reg);
+   brw_op2_ptr combine_op =
+  key-texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG;
unsigned stack_depth = 0;
for (int i = 0; i  num_samples; ++i) {
   assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */
@@ -1139,9 +1150,9 @@ brw_blorp_blit_program::manual_blend()
 
  /* TODO: should use a smaller loop bound for non_RGBA formats */
  for (int k = 0; k  4; ++k) {
-brw_ADD(func, offset(texture_data[stack_depth - 1], 2*k),
-offset(vec8(texture_data[stack_depth - 1]), 2*k),
-offset(vec8(texture_data[stack_depth]), 2*k));
+combine_op(func, offset(texture_data[stack_depth - 1], 2*k),
+   offset(vec8(texture_data[stack_depth - 1]), 2*k),
+   offset(vec8(texture_data[stack_depth]), 2*k));
  }
   }
}
@@ -1149,12 +1160,14 @@ brw_blorp_blit_program::manual_blend()
/* We should have just 1 sample on the stack now. */
assert(stack_depth == 1);
 
-   /* Scale the result down by a factor of num_samples */
-   /* TODO: should use a smaller loop bound for non-RGBA formats */
-   for (int j = 0; j  4; ++j) {
-  brw_MUL(func, offset(texture_data[0], 2*j),
-  offset(vec8(texture_data[0]), 2*j),
-  brw_imm_f(1.0/num_samples));
+   if (key-texture_data_type == BRW_REGISTER_TYPE_F) {
+  /* Scale the result down by a factor of num_samples */
+  /* TODO: should use a smaller loop bound for non-RGBA formats */
+  for (int j = 0; j  4; ++j) {
+ brw_MUL(func, offset(texture_data[0], 2*j),
+ offset(vec8(texture_data[0]), 2*j),
+ brw_imm_f(1.0/num_samples));
+  }
}
 }
 
@@ -1319,7 +1332,8 @@ brw_blorp_blit_program::texture_lookup(struct brw_reg dst,
 void
 brw_blorp_blit_program::render_target_write()
 {
-   struct brw_reg mrf_rt_write = vec16(brw_message_reg(base_mrf));
+   struct brw_reg mrf_rt_write =
+  retype(vec16(brw_message_reg(base_mrf)), key-texture_data_type);
int mrf_offset = 0;
 
/* If we may have

[Mesa-dev] [PATCH 4/7] i965/blorp: Optimize manual_blend() for compressed multisampled surfaces.

2012-07-12 Thread Paul Berry

When downsampling a compressed multisampled surface, we can take a
shortcut to downsample any pixels that were completely covered by a
single primitive.  In this case, the first color value we fetch is the
correct final color for the downsampled pixel, so we can skip the rest
of the blending operation.
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |   23 +++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 32fd48e..c8db662 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1143,6 +1143,26 @@ brw_blorp_blit_program::manual_blend()
   }
   texel_fetch(texture_data[stack_depth++]);
 
+  if (i == 0  key-tex_layout == INTEL_MSAA_LAYOUT_CMS) {
+ /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
+  * suggests an optimization:
+  *
+  * A simple optimization with probable large return in
+  * performance is to compare the MCS value to zero (indicating
+  * all samples are on sample slice 0), and sample only from
+  * sample slice 0 using ld2dss if MCS is zero.
+  *
+  * Note that in the case where the MCS value is zero, sampling from
+  * sample slice 0 using ld2dss and sampling from sample 0 using
+  * ld2dms are equivalent (since all samples are on sample slice 0).
+  * Since we have already sampled from sample 0, all we need to do is
+  * skip the remaining fetches and averaging if MCS is zero.
+  */
+ brw_CMP(func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ,
+ mcs_data, brw_imm_ud(0));
+ brw_IF(func, BRW_EXECUTE_16);
+  }
+
   /* Do count_trailing_one_bits(i) times */
   for (int j = count_trailing_one_bits(i); j--  0; ) {
  assert(stack_depth = 2);
@@ -1169,6 +1189,9 @@ brw_blorp_blit_program::manual_blend()
  brw_imm_f(1.0/num_samples));
   }
}
+
+   if (key-tex_layout == INTEL_MSAA_LAYOUT_CMS)
+  brw_ENDIF(func);
 }
 
 /**
-- 
1.7.7.6

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[Mesa-dev] [PATCH 5/7] i965/blorp: Configure SURFACE_STATE correctly for IMS surfaces.

2012-07-12 Thread Paul Berry

This patch modifies gen7_set_surface_num_multisamples() to set up the
SURFACE_STATE appropriately for texturing from IMS format MSAA
surfaces (which are only used on Gen7 for depth and stencil buffers).
Since the function now sets more than just the number of multisamples,
it's been renamed to gen7_set_surface_msaa().

This will make it possible to remove some kludginess from the blorp
engine.
---
 src/mesa/drivers/dri/i965/brw_state.h |7 +--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |2 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |   11 ---
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 1c70db2..68e92a8 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -39,6 +39,8 @@
 extern C {
 #endif
 
+enum intel_msaa_layout;
+
 extern const struct brw_tracked_state brw_blend_constant_color;
 extern const struct brw_tracked_state brw_cc_vp;
 extern const struct brw_tracked_state brw_cc_unit;
@@ -199,8 +201,9 @@ GLuint translate_tex_format(gl_format mesa_format,
 
 /* gen7_wm_surface_state.c */
 void gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling);
-void gen7_set_surface_num_multisamples(struct gen7_surface_state *surf,
-   unsigned num_samples);
+void gen7_set_surface_msaa(struct gen7_surface_state *surf,
+   unsigned num_samples,
+   enum intel_msaa_layout layout);
 void gen7_set_surface_mcs_info(struct brw_context *brw,
struct gen7_surface_state *surf,
uint32_t surf_offset,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f087dbd..cc28d8c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -180,7 +180,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
   pitch_bytes *= 2;
surf-ss3.pitch = pitch_bytes - 1;
 
-   gen7_set_surface_num_multisamples(surf, surface-num_samples);
+   gen7_set_surface_msaa(surf, surface-num_samples, surface-msaa_layout);
if (surface-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
   gen7_set_surface_mcs_info(brw, surf, wm_surf_offset,
 surface-mt-mcs_mt, is_render_target);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index f037026..869f943 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -56,8 +56,8 @@ gen7_set_surface_tiling(struct gen7_surface_state *surf, 
uint32_t tiling)
 
 
 void
-gen7_set_surface_num_multisamples(struct gen7_surface_state *surf,
-  unsigned num_samples)
+gen7_set_surface_msaa(struct gen7_surface_state *surf, unsigned num_samples,
+  enum intel_msaa_layout layout)
 {
if (num_samples  4)
   surf-ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_8;
@@ -65,6 +65,11 @@ gen7_set_surface_num_multisamples(struct gen7_surface_state 
*surf,
   surf-ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_4;
else
   surf-ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_1;
+
+   surf-ss4.multisampled_surface_storage_format =
+  layout == INTEL_MSAA_LAYOUT_IMS ?
+  GEN7_SURFACE_MSFMT_DEPTH_STENCIL :
+  GEN7_SURFACE_MSFMT_MSS;
 }
 
 
@@ -490,7 +495,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
gen7_set_surface_tiling(surf, region-tiling);
surf-ss3.pitch = (region-pitch * region-cpp) - 1;
 
-   gen7_set_surface_num_multisamples(surf, irb-mt-num_samples);
+   gen7_set_surface_msaa(surf, irb-mt-num_samples, irb-mt-msaa_layout);
 
if (irb-mt-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
   gen7_set_surface_mcs_info(brw, surf, brw-wm.surf_offset[unit],
-- 
1.7.7.6

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[Mesa-dev] [PATCH 7/7] i965/blorp: Use IMS layout when texturing from depth/stencil surfaces.

2012-07-12 Thread Paul Berry

Previously, on Gen7, when texturing from a depth or stencil surface,
the blorp engine would configure the 3D pipeline as though the input
surface was non-multisampled, and perform the necessary coordinate
transformations in the fragment shader to account for the IMS layout.
This meant outputting a lot of extra fragment shader code, and it
raised some uncertainty about how to deal with very large surfaces.

This patch modifies blorp to configure the 3D pipeline properly for
IMS layout when reading from depth and stencil surfaces.
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |   66 +-
 1 files changed, 43 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c5e0ef9..f72145f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1246,18 +1246,31 @@ brw_blorp_blit_program::texel_fetch(struct brw_reg dst)
  s_is_zero ? 2 : 5);
   break;
case 7:
-  if (key-tex_samples  0) {
- if (key-tex_layout == INTEL_MSAA_LAYOUT_CMS) {
-texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS,
-   gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args));
- } else {
-texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS,
-   gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args));
- }
-  } else {
+  switch (key-tex_layout) {
+  case INTEL_MSAA_LAYOUT_IMS:
+ /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface 
Storage
+  * Format):
+  *
+  * If this field is MSFMT_DEPTH_STENCIL
+  * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
+  * messages allowed are ld2dms, resinfo, and sampleinfo.
+  *
+  * So fall through to emit the same message as we use for
+  * INTEL_MSAA_LAYOUT_CMS.
+  */
+  case INTEL_MSAA_LAYOUT_CMS:
+ texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS,
+gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args));
+ break;
+  case INTEL_MSAA_LAYOUT_UMS:
+ texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS,
+gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args));
+ break;
+  case INTEL_MSAA_LAYOUT_NONE:
  assert(s_is_zero);
  texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args,
 ARRAY_SIZE(gen7_ld_args));
+ break;
   }
   break;
default:
@@ -1321,7 +1334,22 @@ brw_blorp_blit_program::texture_lookup(struct brw_reg 
dst,
 expand_to_32_bits(S, mrf);
  break;
   case SAMPLER_MESSAGE_ARG_MCS_INT:
- brw_MOV(func, mrf, mcs_data);
+ switch (key-tex_layout) {
+ case INTEL_MSAA_LAYOUT_CMS:
+brw_MOV(func, mrf, mcs_data);
+break;
+ case INTEL_MSAA_LAYOUT_IMS:
+/* When sampling from an IMS surface, MCS data is not relevant,
+ * and the hardware ignores it.  So don't bother populating it.
+ */
+break;
+ default:
+/* We shouldn't be trying to send MCS data with any other
+ * layouts.
+ */
+assert (!Unsupported layout for MCS data);
+break;
+ }
  break;
   case SAMPLER_MESSAGE_ARG_ZERO_INT:
  brw_MOV(func, mrf, brw_imm_ud(0));
@@ -1485,19 +1513,11 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct 
brw_context *brw,
}
 
if (brw-intel.gen  6) {
-  /* Gen7's texturing hardware only supports the IMS layout with the
-   * ld2dms instruction (which blorp doesn't use).  So if the source is
-   * IMS, we'll have to map it as a single-sampled texture and
-   * de-interleave the samples ourselves.
-   */
-  if (src_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS)
- src.num_samples = 0;
-
-  /* Similarly, Gen7's rendering hardware only supports the IMS layout for
-   * depth and stencil render targets.  Blorp always maps its destination
-   * surface as a color render target (even if it's actually a depth or
-   * stencil buffer).  So if the destination is IMS, we'll have to map it
-   * as a single-sampled texture and interleave the samples ourselves.
+  /* Gen7's rendering hardware only supports the IMS layout for depth and
+   * stencil render targets.  Blorp always maps its destination surface as
+   * a color render target (even if it's actually a depth or stencil
+   * buffer).  So if the destination is IMS, we'll have to map it as a
+   * single-sampled texture and interleave the samples ourselves.
*/
   if (dst_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS)
  dst.num_samples = 0;
-- 
1.7.7.6

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Re: [Mesa-dev] [PATCH 1/7] i965: Add support for AVG instruction.

2012-07-12 Thread Kenneth Graunke

On 07/12/2012 10:43 AM, Paul Berry wrote:
 From the Ivy Bridge PRM, Vol4 Part3 p152:
 
 The avg instruction performs component-wise integer average of
 src0 and src1 and stores the results in dst. An integer average
 uses integer upward rounding. It is equivalent to increment one to
 the addition of src0 and src1 and then apply an arithmetic right
 shift to this intermediate value.
 ---
  src/mesa/drivers/dri/i965/brw_eu.h  |1 +
  src/mesa/drivers/dri/i965/brw_eu_emit.c |   22 ++
  2 files changed, 23 insertions(+), 0 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
 b/src/mesa/drivers/dri/i965/brw_eu.h
 index f25b09d..233b94c 100644
 --- a/src/mesa/drivers/dri/i965/brw_eu.h
 +++ b/src/mesa/drivers/dri/i965/brw_eu.h
 @@ -861,6 +861,7 @@ ALU2(RSL)
  ALU2(ASR)
  ALU2(JMPI)
  ALU2(ADD)
 +ALU2(AVG)
  ALU2(MUL)
  ALU1(FRC)
  ALU1(RNDD)
 diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
 b/src/mesa/drivers/dri/i965/brw_eu_emit.c
 index 8de872e..93e84ae 100644
 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
 +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
 @@ -929,6 +929,28 @@ struct brw_instruction *brw_ADD(struct brw_compile *p,
 return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
  }
  
 +struct brw_instruction *brw_AVG(struct brw_compile *p,
 +struct brw_reg dest,
 +struct brw_reg src0,
 +struct brw_reg src1)
 +{
 +   assert(dest.type == src0.type);
 +   assert(src0.type == src1.type);
 +   switch (src0.type) {
 +   case BRW_REGISTER_TYPE_B:
 +   case BRW_REGISTER_TYPE_UB:
 +   case BRW_REGISTER_TYPE_W:
 +   case BRW_REGISTER_TYPE_UW:
 +   case BRW_REGISTER_TYPE_D:
 +   case BRW_REGISTER_TYPE_UD:
 +  break;
 +   default:
 +  assert(!Bad type for brw_AVG);
 +   }
 +
 +   return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
 +}
 +
  struct brw_instruction *brw_MUL(struct brw_compile *p,
   struct brw_reg dest,
   struct brw_reg src0,

Always nice to see the new instructions in use.

Patch 1 is:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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Re: [Mesa-dev] Mesa 8.0 regression - two bugs

2012-07-12 Thread Sven Arvidsson

On Wed, 2012-07-11 at 21:25 +0200, Deve wrote:
 Hi!
 
 I'm writing about two bugs which I see on 8.0 - now 8.0.4 version of 
 mesa. It was OK on mesa 7.11.2, after upgrade to 8.0 is problem.
 
 First is starting movie in Sims 3 run by Wine. It runs VERY slow. The 
 later part of game runs ok. Example:
 http://imageshack.us/clip/my-videos/444/f5f.mp4/
 Problem is with other games too, for example with transparency object.
 
 Other problem is with Super Tux Kart game. It's only with enabled pixel 
 shaders. Edge of screen looks badly. Example:
 http://desmond.imageshack.us/Himg443/scaled.php?server=443filename=screen1eipng.jpgres=landing
 http://desmond.imageshack.us/Himg515/scaled.php?server=515filename=screen2kipng.jpgres=landing
 
 I don't have enough skills to do solid bug report so I'm writing to 
 mailing list. If you want, you can write to mi what information you need 
 and how it to do.

Hi,

You don't really need any special skills to file a bug report. You have
basically provided everything necessary in your mail, just follow the
instructions here: http://intellinuxgraphics.org/how_to_report_bug.html

Even going further and bisecting to find what caused these bugs isn't
too hard.

-- 
Cheers,
Sven Arvidsson
http://www.whiz.se
PGP Key ID 760BDD22



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Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

2012-07-12 Thread Marek Olšák

On Thu, Jul 12, 2012 at 6:42 PM, Kenneth Graunke kenn...@whitecape.org wrote:
 On 07/12/2012 05:25 AM, Marek Olšák wrote:

 This was not implemented, because the spec was changed just recently.

 Everything has been in place already.

 Gallium has PIPE_FORMAT_B5G6R5_UNORM, while Mesa has MESA_FORMAT_RGB565.


 Oh wow, I didn't realize this was missing.  These changes look good to me.

 Reviewed-by: Kenneth Graunke kenn...@whitecape.org

 One question: should it be ctx-Extensions.ARB_ES2_compatibility || ctx-API
 == API_OPENGLES2?  I suspect most drivers that support ES2 will also support
 ARB_ES2_compatibility, so it shouldn't be a big deal in practice, but...

Frankly, I'm not sure. I usually try to stay of out ES2 matters. I'll
update the conditional as you say then.

Marek
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[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

2012-07-12 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=51972

--- Comment #5 from virgile.bes...@free.fr 2012-07-12 18:25:31 PDT ---
(In reply to comment #3)
 The below looks like your system environment for 32 bit compilation is broken.
 
 configure:20439: checking expat.h usability
 configure:20439: gcc -c -g -O2 -Wall -std=c99
 -Werror=implicit-function-declaration -Werror=missing-prototypes
 -fno-strict-aliasing -fno-builtin-memcmp -m32  conftest.c 5
 In file included from /usr/include/stdio.h:28:0,
  from conftest.c:24:
 /usr/include/features.h:323:26: fatal error: bits/predefs.h: No such file or
 directory


Ok, I've installed libc6-dev-i386 but it still not works although it seems to
be better.

% ./autogen.sh --with-gallium-drivers=r600 --with-dri-drivers= --enable-32-bit 
autoreconf: Entering directory `.'
autoreconf: configure.ac: not using Gettext
autoreconf: running: aclocal 
autoreconf: configure.ac: tracing
autoreconf: running: libtoolize --copy
libtoolize: putting auxiliary files in AC_CONFIG_AUX_DIR, `bin'.
libtoolize: copying file `bin/ltmain.sh'
libtoolize: Consider adding `AC_CONFIG_MACRO_DIR([m4])' to configure.ac and
libtoolize: rerunning libtoolize, to keep the correct libtool macros in-tree.
libtoolize: Consider adding `-I m4' to ACLOCAL_AMFLAGS in Makefile.am.
autoreconf: running: /usr/bin/autoconf
autoreconf: configure.ac: not using Autoheader
autoreconf: running: automake --add-missing --copy --no-force
configure.ac:24: installing `bin/ar-lib'
configure.ac:48: installing `bin/compile'
configure.ac:12: installing `bin/config.guess'
configure.ac:12: installing `bin/config.sub'
configure.ac:13: installing `bin/install-sh'
configure.ac:13: installing `bin/missing'
src/egl/drivers/dri2/Makefile.am: installing `bin/depcomp'
autoreconf: Leaving directory `.'
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for a thread-safe mkdir -p... /bin/mkdir -p
checking for gawk... gawk
checking whether make sets $(MAKE)... yes
checking whether make supports nested variables... yes
checking for style of include used by make... GNU
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables... 
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking dependency style of gcc... gcc3
checking for ar... ar
checking the archiver (ar) interface... ar
checking how to print strings... printf
checking for a sed that does not truncate output... /bin/sed
checking for grep that handles long lines and -e... /bin/grep
checking for egrep... /bin/grep -E
checking for fgrep... /bin/grep -F
checking for ld used by gcc... /usr/bin/ld
checking if the linker (/usr/bin/ld) is GNU ld... yes
checking for BSD- or MS-compatible name lister (nm)... /usr/bin/nm -B
checking the name lister (/usr/bin/nm -B) interface... BSD nm
checking whether ln -s works... yes
checking the maximum length of command line arguments... 1572864
checking whether the shell understands some XSI constructs... yes
checking whether the shell understands +=... yes
checking how to convert x86_64-unknown-linux-gnu file names to
x86_64-unknown-linux-gnu format... func_convert_file_noop
checking how to convert x86_64-unknown-linux-gnu file names to toolchain
format... func_convert_file_noop
checking for /usr/bin/ld option to reload object files... -r
checking for objdump... objdump
checking how to recognize dependent libraries... pass_all
checking for dlltool... no
checking how to associate runtime and link libraries... printf %s\n
checking for archiver @FILE support... @
checking for strip... strip
checking for ranlib... ranlib
checking command to parse /usr/bin/nm -B output from gcc object... ok
checking for sysroot... no
checking for mt... mt
checking if mt is a manifest tool... no
checking how to run the C preprocessor... gcc -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking for dlfcn.h... yes
checking for objdir... .libs
checking if gcc supports -fno-rtti -fno-exceptions... no
checking for gcc option to produce PIC... -fPIC -DPIC
checking if gcc PIC flag -fPIC -DPIC works... yes
checking if gcc static flag -static works... yes
checking if gcc supports -c -o file.o... yes
checking if gcc supports -c -o file.o... (cached) yes
checking whether the gcc linker (/usr/bin/ld -m elf_x86_64) supports shared
libraries... yes

Re: [Mesa-dev] [PATCH 2/9] automake: convert libglsl

2012-07-12 Thread Matt Turner

On Wed, Jul 11, 2012 at 11:58 AM, Jon TURNEY
jon.tur...@dronecode.org.uk wrote:
 v2: Use AM_V_GEN to silence generated code rules. Add BUILT_SOURCES to 
 CLEANFILES
 v3:
 - Fix an accidental // in a path
 - Use automake make rules for lex/yacc rather than writing our own
 - Update .gitignore appropriately
 - Build a libglcpp convenience library rather than awkwardly including
 the files in libglsl and delegating the generation
 - Remove libglsl.a compatibility link on clean

 Signed-off-by: Jon TURNEY jon.tur...@dronecode.org.uk

I'm now getting:

make: *** No rule to make target `../../glsl/glsl_lexer.cpp', needed
by `glsl_lexer.lo'.  Stop.

which is that obnoxious problem where we renamed .lpp - .ll and .ypp
- .yy since... scons.

automake creates .cc files from .ll and .yy, and .cpp from .lpp and
.ypp, so we're generating .cc files.

Solutions:
 - We can apply a patch like what I've attached
 - We can make links from .ll - .lpp and .yy - .ypp and make
automake use the .?pp files
 - Fix scons and rename the files back to .?pp

Also in the patch I've attached is a fix where libdricore$VERSION.a
needs to be libdricore$(VERSION).a, or else dri drivers try to link
with libdricoreERSION.a.

Please squash those in (or let's find another solution to the .ll
problem) and slap a Tested-by: Matt Turner matts...@gmail.com on the
series.
diff --git a/Makefile.am b/Makefile.am
index 8210fcc..b2c810a 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -58,9 +58,9 @@ PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
 EXTRA_FILES = \
aclocal.m4  \
configure   \
-   src/glsl/glsl_parser.cpp\
+   src/glsl/glsl_parser.cc \
src/glsl/glsl_parser.h  \
-   src/glsl/glsl_lexer.cpp \
+   src/glsl/glsl_lexer.cc  \
src/glsl/glcpp/glcpp-lex.c  \
src/glsl/glcpp/glcpp-parse.c\
src/glsl/glcpp/glcpp-parse.h\
@@ -80,7 +80,7 @@ IGNORE_FILES = \
 
 parsers: configure
-@touch $(top_builddir)/configs/current
-   $(MAKE) -C src/glsl glsl_parser.cpp glsl_parser.h glsl_lexer.cpp
+   $(MAKE) -C src/glsl glsl_parser.cc glsl_parser.h glsl_lexer.cc
$(MAKE) -C src/glsl/glcpp glcpp-lex.c glcpp-parse.c glcpp-parse.h
$(MAKE) -C src/mesa program/lex.yy.c program/program_parse.tab.c 
program/program_parse.tab.h
 
diff --git a/configure.ac b/configure.ac
index 7e55907..e62ff2f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1085,8 +1085,8 @@ GALLIUM_DRI_LIB_DEPS='$(TOP)/src/mesa/libmesa.a'
 
 dnl ... or dricore?
 if test x$enable_dri = xyes  test x$driglx_direct = xyes ; then
-DRI_LIB_DEPS='$(TOP)/src/mesa/libdricore/libdricore$VERSION.la'
-GALLIUM_DRI_LIB_DEPS='$(TOP)/src/mesa/libdricore/libdricore$VERSION.a'
+DRI_LIB_DEPS='$(TOP)/src/mesa/libdricore/libdricore$(VERSION).la'
+GALLIUM_DRI_LIB_DEPS='$(TOP)/src/mesa/libdricore/libdricore$(VERSION).a'
 HAVE_DRICORE=yes
 fi
 AM_CONDITIONAL(HAVE_DRICORE, test x$HAVE_DRICORE = xyes)
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index 0425fa3..f2743f7 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -101,8 +101,8 @@ BUILTIN_COMPILER_CXX_FILES = \
$(GLSL_SRCDIR)/builtin_stubs.cpp
 
 BUILTIN_COMPILER_GENERATED_CXX_FILES = \
-   $(GLSL_SRCDIR)/glsl_lexer.cpp \
-   $(GLSL_SRCDIR)/glsl_parser.cpp
+   $(GLSL_SRCDIR)/glsl_lexer.cc \
+   $(GLSL_SRCDIR)/glsl_parser.cc
 
 # libglsl generated sources
 LIBGLSL_GENERATED_CXX_FILES = \
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[Mesa-dev] [PATCH 1/2] r600g: Unify 3D and compute vertex buffer emission

2012-07-12 Thread Tom Stellard

---
 src/gallium/drivers/r600/evergreen_compute.c   |   47 +---
 .../drivers/r600/evergreen_compute_internal.c  |   81 
 .../drivers/r600/evergreen_compute_internal.h  |1 -
 src/gallium/drivers/r600/evergreen_state.c |   30 +--
 src/gallium/drivers/r600/r600_pipe.h   |5 +
 5 files changed, 64 insertions(+), 100 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index a88cad1..b61ea8f 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -83,6 +83,22 @@ writable images will consume TEX slots, VTX slots too 
because of linear indexing
 
 */
 
+static void evergreen_cs_set_vertex_buffer(
+   struct r600_context * rctx,
+   unsigned vb_index,
+   unsigned offset,
+   struct pipe_resource * buffer)
+{
+   struct pipe_vertex_buffer *vb = rctx-cs_vertex_buffer[vb_index];
+   vb-stride = 1;
+   vb-buffer_offset = offset;
+   vb-buffer = buffer;
+   vb-user_buffer = NULL;
+
+   r600_inval_vertex_cache(rctx);
+   r600_atom_dirty(rctx, rctx-cs_vertex_buffer_state);
+}
+
 const struct u_resource_vtbl r600_global_buffer_vtbl =
 {
u_default_resource_get_handle, /* get_handle */
@@ -263,8 +279,8 @@ void evergreen_compute_upload_input(
ctx-ws-buffer_unmap(ctx-cs_shader-kernel_param-cs_buf);
 
///ID=0 is reserved for the parameters
-   evergreen_set_vtx_resource(ctx-cs_shader,
-   ctx-cs_shader-kernel_param, 0, 0, 0);
+   evergreen_cs_set_vertex_buffer(ctx, 0, 0,
+   (struct pipe_resource*)ctx-cs_shader-kernel_param);
///ID=0 is reserved for parameters
evergreen_set_const_cache(ctx-cs_shader, 0,
ctx-cs_shader-kernel_param, ctx-cs_shader-input_size, 0);
@@ -350,6 +366,10 @@ static void compute_emit_cs(struct r600_context *ctx)
 cb_state = ctx-states[R600_PIPE_STATE_FRAMEBUFFER];
r600_context_pipe_state_emit(ctx, cb_state, 
RADEON_CP_PACKET3_COMPUTE_MODE);
 
+   /* Emit vertex buffer state */
+   ctx-cs_vertex_buffer_state.num_dw = 12 * ctx-nr_cs_vertex_buffers;
+   r600_emit_atom(ctx, ctx-cs_vertex_buffer_state);
+
for (i = 0; i  get_compute_resource_num(); i++) {
if (ctx-cs_shader-resources[i].enabled) {
int j;
@@ -452,14 +472,15 @@ static void evergreen_set_compute_resources(struct 
pipe_context * ctx_,
start, count);
 
for (int i = 0; i  count; i++) {
+   /* The First two vertex buffers are reserved for parameters and
+* global buffers. */
+   unsigned vtx_id = 2 + i;
if (resources[i]) {
struct r600_resource_global *buffer =
-   (struct 
r600_resource_global*)resources[i]-base.texture;
+   (struct r600_resource_global*)
+   resources[i]-base.texture;
if (resources[i]-base.writable) {
assert(i+1  12);
-   struct r600_resource_global *buffer =
-   (struct r600_resource_global*)
-   resources[i]-base.texture;
 
evergreen_set_rat(ctx-cs_shader, i+1,
(struct r600_resource 
*)resources[i]-base.texture,
@@ -467,9 +488,10 @@ static void evergreen_set_compute_resources(struct 
pipe_context * ctx_,
resources[i]-base.texture-width0);
}
 
-   evergreen_set_vtx_resource(ctx-cs_shader,
-   (struct r600_resource 
*)resources[i]-base.texture, i+2,
-buffer-chunk-start_in_dw*4, 
resources[i]-base.writable);
+   evergreen_cs_set_vertex_buffer(ctx, vtx_id,
+   buffer-chunk-start_in_dw * 4,
+   resources[i]-base.texture);
+   ctx-nr_cs_vertex_buffers = vtx_id + 1;
}
}
 
@@ -539,7 +561,8 @@ static void evergreen_set_global_binding(
}
 
evergreen_set_rat(ctx-cs_shader, 0, pool-bo, 0, pool-size_in_dw * 4);
-   evergreen_set_vtx_resource(ctx-cs_shader, pool-bo, 1, 0, 1);
+   evergreen_cs_set_vertex_buffer(ctx, 1, 0,
+   (struct pipe_resource*)pool-bo);
 }
 
 /**
@@ -712,6 +735,10 @@ void evergreen_init_compute_state_functions(struct 
r600_context *ctx)
ctx-context.bind_compute_sampler_states = 
evergreen_bind_compute_sampler_states;
ctx-context.set_global_binding = evergreen_set_global_binding;
ctx-context.launch_grid = evergreen_launch_grid;
+
+   /* We always use at least two vertex

[Mesa-dev] [PATCH 2/2] r600g: Emit vertex buffers using the same method as constant buffers

2012-07-12 Thread Tom Stellard

---
 src/gallium/drivers/r600/evergreen_compute.c |8 +++--
 src/gallium/drivers/r600/evergreen_state.c   |   45 -
 src/gallium/drivers/r600/r600_buffer.c   |5 ++-
 src/gallium/drivers/r600/r600_hw_context.c   |2 +-
 src/gallium/drivers/r600/r600_pipe.h |   10 -
 src/gallium/drivers/r600/r600_state.c|2 +-
 src/gallium/drivers/r600/r600_state_common.c |9 -
 7 files changed, 55 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index b61ea8f..947a328 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -90,13 +90,15 @@ static void evergreen_cs_set_vertex_buffer(
struct pipe_resource * buffer)
 {
struct pipe_vertex_buffer *vb = rctx-cs_vertex_buffer[vb_index];
+   struct r600_vertexbuf_state * state = rctx-cs_vertex_buffer_state;
vb-stride = 1;
vb-buffer_offset = offset;
vb-buffer = buffer;
vb-user_buffer = NULL;
 
r600_inval_vertex_cache(rctx);
-   r600_atom_dirty(rctx, rctx-cs_vertex_buffer_state);
+   state-dirty_mask |= 1  vb_index;
+   r600_atom_dirty(rctx, state-atom);
 }
 
 const struct u_resource_vtbl r600_global_buffer_vtbl =
@@ -367,8 +369,8 @@ static void compute_emit_cs(struct r600_context *ctx)
r600_context_pipe_state_emit(ctx, cb_state, 
RADEON_CP_PACKET3_COMPUTE_MODE);
 
/* Emit vertex buffer state */
-   ctx-cs_vertex_buffer_state.num_dw = 12 * ctx-nr_cs_vertex_buffers;
-   r600_emit_atom(ctx, ctx-cs_vertex_buffer_state);
+   ctx-cs_vertex_buffer_state.atom.num_dw = 12 * 
ctx-nr_cs_vertex_buffers;
+   r600_emit_atom(ctx, ctx-cs_vertex_buffer_state.atom);
 
for (i = 0; i  get_compute_resource_num(); i++) {
if (ctx-cs_shader-resources[i].enabled) {
diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index ab78f58..592acfb 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1765,32 +1765,39 @@ static void evergreen_emit_db_misc_state(struct 
r600_context *rctx, struct r600_
r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, 
db_render_override);
 }
 
-static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct 
r600_atom *atom,
-   struct pipe_vertex_buffer *vb, unsigned vb_count, unsigned 
resource_offset,
-   unsigned pkt_flags)
+static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
+ struct r600_vertexbuf_state *state,
+ struct pipe_vertex_buffer 
*vertex_buffers,
+ unsigned vb_count,
+ unsigned resource_offset,
+ unsigned pkt_flags)
 {
struct radeon_winsys_cs *cs = rctx-cs;
-   unsigned i;
-   uint64_t va;
+   uint32_t dirty_mask = state-dirty_mask;
 
-   for (i = 0; i  vb_count; i++) {
-   struct r600_resource *rbuffer = (struct 
r600_resource*)vb[i].buffer;
+   while (dirty_mask) {
+   struct pipe_vertex_buffer *vb;
+   struct r600_resource *rbuffer;
+   uint64_t va;
+   unsigned buffer_index = ffs(dirty_mask) - 1;
 
+   vb = vertex_buffers[buffer_index];
+   rbuffer = (struct r600_resource*)vb-buffer;
if (!rbuffer) {
-   continue;
+   goto next;
}
 
va = r600_resource_va(rctx-screen-screen, rbuffer-b.b);
-   va += vb[i].buffer_offset;
+   va += vb-buffer_offset;
 
/* fetch resources start at index 992 */
r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
-   r600_write_value(cs, (resource_offset + i) * 8);
+   r600_write_value(cs, (resource_offset + buffer_index) * 8);
r600_write_value(cs, va); /* RESOURCEi_WORD0 */
-   r600_write_value(cs, rbuffer-buf-size - vb[i].buffer_offset - 
1); /* RESOURCEi_WORD1 */
+   r600_write_value(cs, rbuffer-buf-size - vb-buffer_offset - 
1); /* RESOURCEi_WORD1 */
r600_write_value(cs, /* RESOURCEi_WORD2 */
 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
-S_030008_STRIDE(vb[i].stride) |
+S_030008_STRIDE(vb-stride) |
 S_030008_BASE_ADDRESS_HI(va  32UL));
r600_write_value(cs, /* RESOURCEi_WORD3 */
 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
@@ -1804,18 +1811,24 @@ static void evergreen_emit_vertex_buffers(struct 
r600_context *rctx, struct r600

[Mesa-dev] [PATCH 1/2] draw,gallivm: Fix draw_get_shader_param.

2012-07-12 Thread jfonseca

From: José Fonseca jfons...@vmware.com

- Use LLVM limits when LLVM is being used, instead of TGSI limits
- Provide draw_get_shader_param_no_llvm for when llvm is never used (softpipe)
- Eliminate several of the hacks around draw shader caps in several drivers

Unfortunately the hack for PIPE_MAX_VERTEX_SAMPLERS is still necessary.
---
 src/gallium/auxiliary/draw/draw_context.c |   41 +
 src/gallium/auxiliary/draw/draw_context.h |   16 +++
 src/gallium/auxiliary/gallivm/lp_bld_limits.h |   58 -
 src/gallium/drivers/i915/i915_screen.c|2 -
 src/gallium/drivers/llvmpipe/lp_screen.c  |6 +--
 src/gallium/drivers/softpipe/sp_screen.c  |   18 +++-
 6 files changed, 110 insertions(+), 31 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_context.c 
b/src/gallium/auxiliary/draw/draw_context.c
index 2eae204..9713db8 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -42,6 +42,7 @@
 
 #if HAVE_LLVM
 #include gallivm/lp_bld_init.h
+#include gallivm/lp_bld_limits.h
 #include draw_llvm.h
 
 static boolean
@@ -830,3 +831,43 @@ draw_set_mapped_texture(struct draw_context *draw,
 row_stride, img_stride, data);
 #endif
 }
+
+/**
+ * XXX: Results for PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS because there are two
+ * different ways of setting textures, and drivers typically only support one.
+ */
+int
+draw_get_shader_param_no_llvm(unsigned shader, enum pipe_shader_cap param)
+{
+   switch(shader) {
+   case PIPE_SHADER_VERTEX:
+   case PIPE_SHADER_GEOMETRY:
+  return tgsi_exec_get_shader_param(param);
+   default:
+  return 0;
+   }
+}
+
+/**
+ * XXX: Results for PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS because there are two
+ * different ways of setting textures, and drivers typically only support one.
+ */
+int
+draw_get_shader_param(unsigned shader, enum pipe_shader_cap param)
+{
+
+#ifdef HAVE_LLVM
+   if (draw_get_option_use_llvm()) {
+   switch(shader) {
+   case PIPE_SHADER_VERTEX:
+   case PIPE_SHADER_GEOMETRY:
+  return gallivm_get_shader_param(param);
+   default:
+  return 0;
+   }
+   }
+#endif
+
+   return draw_get_shader_param_no_llvm(shader, param);
+}
+
diff --git a/src/gallium/auxiliary/draw/draw_context.h 
b/src/gallium/auxiliary/draw/draw_context.h
index 4cd0caf..852cbc3 100644
--- a/src/gallium/auxiliary/draw/draw_context.h
+++ b/src/gallium/auxiliary/draw/draw_context.h
@@ -277,16 +277,10 @@ boolean draw_need_pipeline(const struct draw_context 
*draw,
const struct pipe_rasterizer_state *rasterizer,
unsigned prim );
 
-static INLINE int
-draw_get_shader_param(unsigned shader, enum pipe_shader_cap param)
-{
-   switch(shader) {
-   case PIPE_SHADER_VERTEX:
-   case PIPE_SHADER_GEOMETRY:
-  return tgsi_exec_get_shader_param(param);
-   default:
-  return 0;
-   }
-}
+int
+draw_get_shader_param(unsigned shader, enum pipe_shader_cap param);
+
+int
+draw_get_shader_param_no_llvm(unsigned shader, enum pipe_shader_cap param);
 
 #endif /* DRAW_CONTEXT_H */
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h 
b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index 2dbb7ce..905070e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -1,6 +1,6 @@
 /**
  *
- * Copyright 2010 VMware, Inc.
+ * Copyright 2010-2012 VMware, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -29,6 +29,13 @@
 #ifndef LP_BLD_LIMITS_H_
 #define LP_BLD_LIMITS_H_
 
+
+#include limits.h
+
+#include pipe/p_state.h
+#include pipe/p_defines.h
+
+
 /*
  * TGSI translation limits.
  *
@@ -57,4 +64,53 @@
  */
 #define LP_MAX_TGSI_LOOP_ITERATIONS 65535
 
+
+/**
+ * Some of these limits are actually infinite (i.e., only limited by available
+ * memory), however advertising INT_MAX would cause some test problems to
+ * actually try to allocate the maximum and run out of memory and crash.  So
+ * stick with something reasonable here.
+ */
+static INLINE int
+gallivm_get_shader_param(enum pipe_shader_cap param)
+{
+   switch(param) {
+   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+  return 1 * 1024 * 1024;
+   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+  return LP_MAX_TGSI_NESTING;
+   case PIPE_SHADER_CAP_MAX_INPUTS:
+  return PIPE_MAX_SHADER_INPUTS;
+   case PIPE_SHADER_CAP_MAX_CONSTS:
+  return 16 * 2024;
+   case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+  return PIPE_MAX_CONSTANT_BUFFERS;
+   case PIPE_SHADER_CAP_MAX_TEMPS:
+  return LP_MAX_TGSI_TEMPS;
+   case PIPE_SHADER_CAP_MAX_ADDRS:
+  return LP_MAX_TGSI_ADDRS;
+   case PIPE_SHADER_CAP_MAX_PREDS:

[Mesa-dev] [PATCH 2/2] mesa/st: Generates TGSI that always recognizes INSTANCEID/VERTEXID as integers.

2012-07-12 Thread jfonseca

From: José Fonseca jfons...@vmware.com

Tested by running piglit draw-instanced, and by forcing llvmpipe advertise no 
native
integer support, which now produces:

VERT
DCL IN[0]
DCL SV[0], INSTANCEID
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..19]
DCL TEMP[0], LOCAL
DCL TEMP[1], LOCAL
DCL TEMP[2], LOCAL
DCL ADDR[0]
  0: U2F TEMP[0].x, SV[0]
  1: ARL ADDR[0].x, TEMP[0].
  2: MOV TEMP[1].xy, CONST[ADDR[0].x+8].xyxx
  3: ADD TEMP[2].x, IN[0]., TEMP[1].
  4: ADD TEMP[1].x, IN[0]., TEMP[1].
  5: MUL TEMP[2], CONST[16], TEMP[2].
  6: MAD TEMP[2], CONST[17], TEMP[1]., TEMP[2]
  7: MAD TEMP[2], CONST[18], IN[0]., TEMP[2]
  8: MAD TEMP[2], CONST[19], IN[0]., TEMP[2]
  9: ARL ADDR[0].x, TEMP[0].
 10: MOV TEMP[1], CONST[ADDR[0].x]
 11: MOV OUT[0], TEMP[2]
 12: MOV OUT[1], TEMP[1]
 13: END
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |   19 +++
 src/mesa/state_tracker/st_mesa_to_tgsi.c   |   19 +++
 2 files changed, 38 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b6abe84..320706c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4615,6 +4615,25 @@ st_translate_program(
  if (sysInputs  (1  i)) {
 unsigned semName = mesa_sysval_to_semantic[i];
 t-systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 
0);
+if (semName == TGSI_SEMANTIC_INSTANCEID ||
+semName == TGSI_SEMANTIC_VERTEXID) {
+   /* From Gallium perspective, these system values are always
+* integer, and require native integer support.  However, if
+* native integer is supported on the vertex stage but not the
+* pixel stage (e.g, i915g + draw), Mesa will generate IR that
+* assumes these system values are floats. To resolve the
+* inconsistency, we insert a U2F.
+*/
+   struct st_context *st = st_context(ctx);
+   struct pipe_screen *pscreen = st-pipe-screen;
+   assert(procType == TGSI_PROCESSOR_VERTEX);
+   assert(pscreen-get_shader_param(pscreen, procType, 
PIPE_SHADER_CAP_INTEGERS));
+  if (!ctx-Const.NativeIntegers) {
+  struct ureg_dst temp = ureg_DECL_local_temporary(t-ureg);
+  ureg_U2F( t-ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), 
t-systemValues[i]);
+  t-systemValues[i] = ureg_scalar(ureg_src(temp), 0);
+   }
+}
 numSys++;
 sysInputs = ~(1  i);
  }
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index e414ed8..396f0f3 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -1159,6 +1159,25 @@ st_translate_mesa_program(
  if (sysInputs  (1  i)) {
 unsigned semName = mesa_sysval_to_semantic[i];
 t-systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 
0);
+if (semName == TGSI_SEMANTIC_INSTANCEID ||
+semName == TGSI_SEMANTIC_VERTEXID) {
+   /* From Gallium perspective, these system values are always
+* integer, and require native integer support.  However, if
+* native integer is supported on the vertex stage but not the
+* pixel stage (e.g, i915g + draw), Mesa will generate IR that
+* assumes these system values are floats. To resolve the
+* inconsistency, we insert a U2F.
+*/
+   struct st_context *st = st_context(ctx);
+   struct pipe_screen *pscreen = st-pipe-screen;
+   assert(procType == TGSI_PROCESSOR_VERTEX);
+   assert(pscreen-get_shader_param(pscreen, procType, 
PIPE_SHADER_CAP_INTEGERS));
+  if (!ctx-Const.NativeIntegers) {
+  struct ureg_dst temp = ureg_DECL_local_temporary(t-ureg);
+  ureg_U2F( t-ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), 
t-systemValues[i]);
+  t-systemValues[i] = ureg_scalar(ureg_src(temp), 0);
+   }
+}
 numSys++;
 sysInputs = ~(1  i);
  }
-- 
1.7.9.5

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Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

2012-07-12 Thread Kenneth Graunke


On 07/12/2012 11:12 AM, Marek Olšák wrote:

On Thu, Jul 12, 2012 at 6:42 PM, Kenneth Graunke kenn...@whitecape.org wrote:

On 07/12/2012 05:25 AM, Marek Olšák wrote:


This was not implemented, because the spec was changed just recently.

Everything has been in place already.

Gallium has PIPE_FORMAT_B5G6R5_UNORM, while Mesa has MESA_FORMAT_RGB565.



Oh wow, I didn't realize this was missing.  These changes look good to me.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

One question: should it be ctx-Extensions.ARB_ES2_compatibility || ctx-API
== API_OPENGLES2?  I suspect most drivers that support ES2 will also support
ARB_ES2_compatibility, so it shouldn't be a big deal in practice, but...


Frankly, I'm not sure. I usually try to stay of out ES2 matters. I'll
update the conditional as you say then.

Marek


I just talked to Ian about this, and he seems to think 565 should be 
enabled if:


- ARB_ES2_compatibility is advertised
- API is ES 2
- API is ES 1 and the framebuffer object extension is enabled

That's a fairly complicated check that I hate to spam everywhere, so I 
might just leave it as you had it originally.  It won't be a problem for 
us since we always set the ARB_ES2_compatibility bit in the Intel drivers.


Either way.
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Re: [Mesa-dev] [PATCH 1/2] r600g: Unify 3D and compute vertex buffer emission

2012-07-12 Thread Marek Olšák

For the series:

Reviewed-by: Marek Olšák mar...@gmail.com

Marek

On Thu, Jul 12, 2012 at 9:50 PM, Tom Stellard tstel...@gmail.com wrote:
 ---
  src/gallium/drivers/r600/evergreen_compute.c   |   47 +---
  .../drivers/r600/evergreen_compute_internal.c  |   81 
 
  .../drivers/r600/evergreen_compute_internal.h  |1 -
  src/gallium/drivers/r600/evergreen_state.c |   30 +--
  src/gallium/drivers/r600/r600_pipe.h   |5 +
  5 files changed, 64 insertions(+), 100 deletions(-)

 diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
 b/src/gallium/drivers/r600/evergreen_compute.c
 index a88cad1..b61ea8f 100644
 --- a/src/gallium/drivers/r600/evergreen_compute.c
 +++ b/src/gallium/drivers/r600/evergreen_compute.c
 @@ -83,6 +83,22 @@ writable images will consume TEX slots, VTX slots too 
 because of linear indexing

  */

 +static void evergreen_cs_set_vertex_buffer(
 +   struct r600_context * rctx,
 +   unsigned vb_index,
 +   unsigned offset,
 +   struct pipe_resource * buffer)
 +{
 +   struct pipe_vertex_buffer *vb = rctx-cs_vertex_buffer[vb_index];
 +   vb-stride = 1;
 +   vb-buffer_offset = offset;
 +   vb-buffer = buffer;
 +   vb-user_buffer = NULL;
 +
 +   r600_inval_vertex_cache(rctx);
 +   r600_atom_dirty(rctx, rctx-cs_vertex_buffer_state);
 +}
 +
  const struct u_resource_vtbl r600_global_buffer_vtbl =
  {
 u_default_resource_get_handle, /* get_handle */
 @@ -263,8 +279,8 @@ void evergreen_compute_upload_input(
 ctx-ws-buffer_unmap(ctx-cs_shader-kernel_param-cs_buf);

 ///ID=0 is reserved for the parameters
 -   evergreen_set_vtx_resource(ctx-cs_shader,
 -   ctx-cs_shader-kernel_param, 0, 0, 0);
 +   evergreen_cs_set_vertex_buffer(ctx, 0, 0,
 +   (struct pipe_resource*)ctx-cs_shader-kernel_param);
 ///ID=0 is reserved for parameters
 evergreen_set_const_cache(ctx-cs_shader, 0,
 ctx-cs_shader-kernel_param, ctx-cs_shader-input_size, 0);
 @@ -350,6 +366,10 @@ static void compute_emit_cs(struct r600_context *ctx)
  cb_state = ctx-states[R600_PIPE_STATE_FRAMEBUFFER];
 r600_context_pipe_state_emit(ctx, cb_state, 
 RADEON_CP_PACKET3_COMPUTE_MODE);

 +   /* Emit vertex buffer state */
 +   ctx-cs_vertex_buffer_state.num_dw = 12 * ctx-nr_cs_vertex_buffers;
 +   r600_emit_atom(ctx, ctx-cs_vertex_buffer_state);
 +
 for (i = 0; i  get_compute_resource_num(); i++) {
 if (ctx-cs_shader-resources[i].enabled) {
 int j;
 @@ -452,14 +472,15 @@ static void evergreen_set_compute_resources(struct 
 pipe_context * ctx_,
 start, count);

 for (int i = 0; i  count; i++) {
 +   /* The First two vertex buffers are reserved for parameters 
 and
 +* global buffers. */
 +   unsigned vtx_id = 2 + i;
 if (resources[i]) {
 struct r600_resource_global *buffer =
 -   (struct 
 r600_resource_global*)resources[i]-base.texture;
 +   (struct r600_resource_global*)
 +   resources[i]-base.texture;
 if (resources[i]-base.writable) {
 assert(i+1  12);
 -   struct r600_resource_global *buffer =
 -   (struct r600_resource_global*)
 -   resources[i]-base.texture;

 evergreen_set_rat(ctx-cs_shader, i+1,
 (struct r600_resource 
 *)resources[i]-base.texture,
 @@ -467,9 +488,10 @@ static void evergreen_set_compute_resources(struct 
 pipe_context * ctx_,
 resources[i]-base.texture-width0);
 }

 -   evergreen_set_vtx_resource(ctx-cs_shader,
 -   (struct r600_resource 
 *)resources[i]-base.texture, i+2,
 -buffer-chunk-start_in_dw*4, 
 resources[i]-base.writable);
 +   evergreen_cs_set_vertex_buffer(ctx, vtx_id,
 +   buffer-chunk-start_in_dw * 4,
 +   resources[i]-base.texture);
 +   ctx-nr_cs_vertex_buffers = vtx_id + 1;
 }
 }

 @@ -539,7 +561,8 @@ static void evergreen_set_global_binding(
 }

 evergreen_set_rat(ctx-cs_shader, 0, pool-bo, 0, pool-size_in_dw * 
 4);
 -   evergreen_set_vtx_resource(ctx-cs_shader, pool-bo, 1, 0, 1);
 +   evergreen_cs_set_vertex_buffer(ctx, 1, 0,
 +   (struct pipe_resource*)pool-bo);
  }

  /**
 @@ -712,6 +735,10 @@ void evergreen_init_compute_state_functions(struct 
 r600_context *ctx)

Re: [Mesa-dev] [PATCH 1/2] draw, gallivm: Fix draw_get_shader_param.

2012-07-12 Thread Marek Olšák

On Thu, Jul 12, 2012 at 9:50 PM,  jfons...@vmware.com wrote:
 From: José Fonseca jfons...@vmware.com

 - Use LLVM limits when LLVM is being used, instead of TGSI limits
 - Provide draw_get_shader_param_no_llvm for when llvm is never used (softpipe)
 - Eliminate several of the hacks around draw shader caps in several drivers

 Unfortunately the hack for PIPE_MAX_VERTEX_SAMPLERS is still necessary.
 ---
  src/gallium/auxiliary/draw/draw_context.c |   41 +
  src/gallium/auxiliary/draw/draw_context.h |   16 +++
  src/gallium/auxiliary/gallivm/lp_bld_limits.h |   58 
 -
  src/gallium/drivers/i915/i915_screen.c|2 -
  src/gallium/drivers/llvmpipe/lp_screen.c  |6 +--
  src/gallium/drivers/softpipe/sp_screen.c  |   18 +++-
  6 files changed, 110 insertions(+), 31 deletions(-)

 diff --git a/src/gallium/auxiliary/draw/draw_context.c 
 b/src/gallium/auxiliary/draw/draw_context.c
 index 2eae204..9713db8 100644
 --- a/src/gallium/auxiliary/draw/draw_context.c
 +++ b/src/gallium/auxiliary/draw/draw_context.c
 @@ -42,6 +42,7 @@

  #if HAVE_LLVM
  #include gallivm/lp_bld_init.h
 +#include gallivm/lp_bld_limits.h
  #include draw_llvm.h

  static boolean
 @@ -830,3 +831,43 @@ draw_set_mapped_texture(struct draw_context *draw,
  row_stride, img_stride, data);
  #endif
  }
 +
 +/**
 + * XXX: Results for PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS because there are 
 two
 + * different ways of setting textures, and drivers typically only support 
 one.
 + */
 +int
 +draw_get_shader_param_no_llvm(unsigned shader, enum pipe_shader_cap param)
 +{
 +   switch(shader) {
 +   case PIPE_SHADER_VERTEX:
 +   case PIPE_SHADER_GEOMETRY:
 +  return tgsi_exec_get_shader_param(param);
 +   default:
 +  return 0;
 +   }
 +}
 +
 +/**
 + * XXX: Results for PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS because there are 
 two
 + * different ways of setting textures, and drivers typically only support 
 one.
 + */
 +int
 +draw_get_shader_param(unsigned shader, enum pipe_shader_cap param)
 +{
 +
 +#ifdef HAVE_LLVM
 +   if (draw_get_option_use_llvm()) {
 +   switch(shader) {
 +   case PIPE_SHADER_VERTEX:
 +   case PIPE_SHADER_GEOMETRY:
 +  return gallivm_get_shader_param(param);
 +   default:
 +  return 0;
 +   }
 +   }
 +#endif

The indentation here is wrong. Apart from that, the series looks good.

Reviewed-by: Marek Olšák mar...@gmail.com

Marek

 +
 +   return draw_get_shader_param_no_llvm(shader, param);
 +}
 +
 diff --git a/src/gallium/auxiliary/draw/draw_context.h 
 b/src/gallium/auxiliary/draw/draw_context.h
 index 4cd0caf..852cbc3 100644
 --- a/src/gallium/auxiliary/draw/draw_context.h
 +++ b/src/gallium/auxiliary/draw/draw_context.h
 @@ -277,16 +277,10 @@ boolean draw_need_pipeline(const struct draw_context 
 *draw,
 const struct pipe_rasterizer_state *rasterizer,
 unsigned prim );

 -static INLINE int
 -draw_get_shader_param(unsigned shader, enum pipe_shader_cap param)
 -{
 -   switch(shader) {
 -   case PIPE_SHADER_VERTEX:
 -   case PIPE_SHADER_GEOMETRY:
 -  return tgsi_exec_get_shader_param(param);
 -   default:
 -  return 0;
 -   }
 -}
 +int
 +draw_get_shader_param(unsigned shader, enum pipe_shader_cap param);
 +
 +int
 +draw_get_shader_param_no_llvm(unsigned shader, enum pipe_shader_cap param);

  #endif /* DRAW_CONTEXT_H */
 diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h 
 b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
 index 2dbb7ce..905070e 100644
 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
 +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
 @@ -1,6 +1,6 @@
  /**
   *
 - * Copyright 2010 VMware, Inc.
 + * Copyright 2010-2012 VMware, Inc.
   * All Rights Reserved.
   *
   * Permission is hereby granted, free of charge, to any person obtaining a
 @@ -29,6 +29,13 @@
  #ifndef LP_BLD_LIMITS_H_
  #define LP_BLD_LIMITS_H_

 +
 +#include limits.h
 +
 +#include pipe/p_state.h
 +#include pipe/p_defines.h
 +
 +
  /*
   * TGSI translation limits.
   *
 @@ -57,4 +64,53 @@
   */
  #define LP_MAX_TGSI_LOOP_ITERATIONS 65535

 +
 +/**
 + * Some of these limits are actually infinite (i.e., only limited by 
 available
 + * memory), however advertising INT_MAX would cause some test problems to
 + * actually try to allocate the maximum and run out of memory and crash.  So
 + * stick with something reasonable here.
 + */
 +static INLINE int
 +gallivm_get_shader_param(enum pipe_shader_cap param)
 +{
 +   switch(param) {
 +   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 +   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 +   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 +   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 +  return 1 * 1024 * 1024;
 +   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 +  return LP_MAX_TGSI_NESTING;
 +   case PIPE_SHADER_CAP_MAX_INPUTS:
 +  return

[Mesa-dev] [Bug 52034] New: [llvmpipe] piglit depthstencil-default_fb-blit regression

2012-07-12 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=52034

 Bug #: 52034
   Summary: [llvmpipe] piglit depthstencil-default_fb-blit
regression
Classification: Unclassified
   Product: Mesa
   Version: git
  Platform: x86-64 (AMD64)
OS/Version: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
AssignedTo: mesa-dev@lists.freedesktop.org
ReportedBy: v...@freedesktop.org


mesa: 1a06e8454ec714e950bc2cd985534a18bf1f

Run piglit depthstencil-default_fb-blit on llvmpipe.

$ ./bin/fbo-depthstencil blit default_fb -auto
Testing default_fb.
Testing glBlitFramebuffer(depthstencil).
Mesa 8.1-devel implementation error: st_BlitFramebuffer(STENCIL) software
fallback not implemented
Please report at bugs.freedesktop.org
Stencil at 0,0   Expected: 0x33   Observed: 0xfe
Stencil at 1,0   Expected: 0x33   Observed: 0xfe
Stencil at 2,0   Expected: 0x33   Observed: 0xfe
Stencil at 3,0   Expected: 0x33   Observed: 0xfe
Stencil at 4,0   Expected: 0x33   Observed: 0xfe
Stencil at 5,0   Expected: 0x33   Observed: 0xfe
Stencil at 6,0   Expected: 0x33   Observed: 0xfe
Stencil at 7,0   Expected: 0x33   Observed: 0xfe
Stencil at 8,0   Expected: 0x33   Observed: 0xfe
Stencil at 9,0   Expected: 0x33   Observed: 0xfe
Stencil at 10,0   Expected: 0x33   Observed: 0xfe
Stencil at 11,0   Expected: 0x33   Observed: 0xfe
Stencil at 12,0   Expected: 0x33   Observed: 0xfe
Stencil at 13,0   Expected: 0x33   Observed: 0xfe
Stencil at 14,0   Expected: 0x33   Observed: 0xfe
Stencil at 15,0   Expected: 0x33   Observed: 0xfe
Stencil at 16,0   Expected: 0x33   Observed: 0xfe
Stencil at 17,0   Expected: 0x33   Observed: 0xfe
Stencil at 18,0   Expected: 0x33   Observed: 0xfe
...
Total failures: 3721
PIGLIT: {'result': 'fail' }


There are only 'skip'ped commits left to test.
The first bad commit could be any of:
6842d5fced16b275a06d39fe1d38b8326a11c84e
5a17d8318ec2c20bf86275044dc8f715105a88e7
fe1fd675565231b49d3ac53d0b4bec39d8bc6781
dee58f94af833906863b0ff2955b20f3ab407e63
e773a48a3bf9ab839f10794506c0a492b7eab883
6d13d91f4e49b186f7715e907c784bce471c2441
df79eb59566f20a7fa8e11d87b63b81ec35eaf25
43e3f19c766863a655bb9f7c04f7820cbda0c8f5
9576d555e06df52a64906de94db4c1c7434630f9
21cb5ed20d1d7984b7695395327ed0ba0b0d16e2
4fe74412cfdba9af6ce878aebbb0c367f19cbb4b
375e73d85948b43aa509e25f0a210ebd10238b6f
a1a1ff5ec09acda0c4849c9e41a37ae82a80f000
0ea76916e63f8fc556f5e8f5a46c196d317cd5ad
553e13dbc2d5eff16f2c9a384ee5c5cf70b90901
5ba15d8d38d98cb7b625fa55e7d818ef9c6629ce
ce16ca4635152db4c1af45888cb9c225e8d94f5a
7e0cb473b063072fee121d536e7e37679528e991
a7f3697eb849376dda23556df479127909cb7fd4
5a74e17ab0f5ec864c18bc74f951e18d3ecc136f
db7404defd47aa22082b52a6a31a08fb39fab626
24e0a2633512afa3208969520b9e29a8b974275d
d24ece97e5ac755b9fd11d1d00d2eafc8524ca04
3f13b5da1510bff8ceaf6718e4b21936d3180376
63d8c8baa99560c7a051b88afae645e60f07bc8f
0f3659bb564c6b8cfcf7c1ab276fbdfdc018e439
2dca61bcb357d70be2bb4f2d28321dfc5fc10c69
d9a8cd76e5a156eb8af686eba614b9fada7258fe
We cannot bisect more!
bisect run cannot continue any more

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[Mesa-dev] [Bug 52034] [llvmpipe] piglit depthstencil-default_fb-blit regression

2012-07-12 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=52034

--- Comment #1 from Marek Olšák mar...@gmail.com 2012-07-13 04:11:50 PDT ---
This is not a regression. The stencil blit has never been implemented for
llvmpipe. The test used to pass incorrectly.

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Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

Re: [Mesa-dev] Mesa (master): docs: Update GL3.txt.

[Mesa-dev] Mesa 8.0 regression - two bugs

Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

[Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

Re: [Mesa-dev] [PATCH 5/5] i965/fs: Make register spill/unspill only do the regs for that instruction.

Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

Re: [Mesa-dev] [PATCH 00/11] Add YUYV format support of dri image

[Mesa-dev] [PATCH 0/7] i965/blorp: Improvements to the blorp engine for Gen7.

[Mesa-dev] [PATCH 1/7] i965: Add support for AVG instruction.

[Mesa-dev] [PATCH 2/7] i965/blorp: Modify manual_blend() to avoid unnecessary loss of precision.

[Mesa-dev] [PATCH 3/7] i965/blorp: Fix integer downsampling on Gen7.

[Mesa-dev] [PATCH 4/7] i965/blorp: Optimize manual_blend() for compressed multisampled surfaces.

[Mesa-dev] [PATCH 5/7] i965/blorp: Configure SURFACE_STATE correctly for IMS surfaces.

[Mesa-dev] [PATCH 7/7] i965/blorp: Use IMS layout when texturing from depth/stencil surfaces.

Re: [Mesa-dev] [PATCH 1/7] i965: Add support for AVG instruction.

Re: [Mesa-dev] Mesa 8.0 regression - two bugs

Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

[Mesa-dev] [Bug 51972] Compilation error on x86-64 with --enable-32-bit option

Re: [Mesa-dev] [PATCH 2/9] automake: convert libglsl

[Mesa-dev] [PATCH 1/2] r600g: Unify 3D and compute vertex buffer emission

[Mesa-dev] [PATCH 2/2] r600g: Emit vertex buffers using the same method as constant buffers

[Mesa-dev] [PATCH 1/2] draw,gallivm: Fix draw_get_shader_param.

[Mesa-dev] [PATCH 2/2] mesa/st: Generates TGSI that always recognizes INSTANCEID/VERTEXID as integers.

Re: [Mesa-dev] [PATCH] mesa, st/mesa: implement GL_RGB565 from ARB_ES2_compatibility

Re: [Mesa-dev] [PATCH 1/2] r600g: Unify 3D and compute vertex buffer emission

Re: [Mesa-dev] [PATCH 1/2] draw, gallivm: Fix draw_get_shader_param.

[Mesa-dev] [Bug 52034] New: [llvmpipe] piglit depthstencil-default_fb-blit regression

[Mesa-dev] [Bug 52034] [llvmpipe] piglit depthstencil-default_fb-blit regression

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