[Mesa-dev] [PATCH] i965: Fix src0 vs src1 typo

[Matt Turner]

A typo caused us to copy src0's reg file to src1 rather than reading
src1's as intended. This caused us to fail to compact instructions like

   mov(8)   g4<1>D0D  { align1 1Q };

because src1 was set to immediate rather than architecture file. Fixing
this reenables compaction (after the precompact() pass changes the data
types):

   mov(8)   g4<1>UD   0xUD{ align1 1Q compacted };

Fixes: 1cb0a7941b27 ("i965: Switch to using the logical register types")
---
 src/intel/compiler/brw_eu_compact.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index 7674aa8b85..7b32270957 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -998,7 +998,7 @@ precompact(const struct gen_device_info *devinfo, brw_inst 
inst)
  (brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_DF ||
   brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_UQ ||
   brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_Q))) {
-  enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, );
+  enum brw_reg_file file = brw_inst_src1_reg_file(devinfo, );
   brw_inst_set_src1_file_type(devinfo, , file, BRW_REGISTER_TYPE_UD);
}
 
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] intel: Always set Cube Face Enables for all surfaces.

[Matt Turner]

Looks good to me.

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH v2] i965 : optimized bucket index calculation

[Muthukumar, Aravindan]

Hi Reviewers,
Please review and provide the comments on the second version of the 
patch.

Thanks,
Aravindan

> -Original Message-
> From: Marathe, Yogesh
> Sent: Friday, September 22, 2017 8:41 AM
> To: Ekstrand, Jason ; Palli, Tapani
> ; Ian Romanick ; Emil Velikov
> 
> Cc: Muthukumar, Aravindan ; J Karanje,
> Kedar ; mesa-dev@lists.freedesktop.org
> Subject: RE: [Mesa-dev] [PATCH v2] i965 : optimized bucket index calculation
> 
> + all v1 reviewers. Does this look ok?
> 
> -Yogesh.
> 
> >-Original Message-
> >From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> >Behalf Of aravindan.muthuku...@intel.com
> >Sent: Thursday, September 14, 2017 12:13 PM
> >To: mesa-dev@lists.freedesktop.org
> >Cc: Muthukumar, Aravindan ; J Karanje,
> >Kedar 
> >Subject: [Mesa-dev] [PATCH v2] i965 : optimized bucket index
> >calculation
> >
> >From: Aravindan Muthukumar 
> >
> >Avoiding the loop which was running with O(n) complexity.
> >Now the complexity has been reduced to O(1)
> >
> >Algorithm calculates the index using matrix method.
> >Matrix arrangement is as below:
> >Assuming PAGE_SIZE is 4096.
> >
> > 1*4096   2*40963*40964*4096
> > 5*4096   6*40967*40968*4096
> >  ...  ...   ...   ...
> >  ...  ...   ...   ...
> >  ...  ...   ...   max_cache_size
> >
> >From this matrix its cleary seen that every row follows the below way:
> > ...   ...   ...n
> >   n+(1/4)n  n+(1/2)n  n+(3/4)n2n
> >
> >Row is calulated as log2(size/PAGE_SIZE) Column is calculated as
> >converting the difference between the elements to fit into power size of two
> and indexing it.
> >
> >Final Index is (row*4)+(col-1)
> >
> >Tested with Intel Mesa CI.
> >
> >Improves performance of 3d Mark on Broxton.
> >Analyzed using Compare Perf Analyser:
> >Average : 201.2 +/- 65.4836 (n=20)
> >Percentage : 0.705966% +/- 0.229767% (n=20)
> >
> >v2: Review comments regarding cosmetics and asserts implemented
> >
> >Signed-off-by: Aravindan Muthukumar 
> >Signed-off-by: Kedar Karanje 
> >Reviewed-by: Yogesh Marathe 
> >---
> > src/mesa/drivers/dri/i965/brw_bufmgr.c | 46
> >--
> > 1 file changed, 39 insertions(+), 7 deletions(-)
> >
> >diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >index 8017219..8013ccb 100644
> >--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >@@ -87,6 +87,8 @@
> >
> > #define memclear(s) memset(, 0, sizeof(s))
> >
> >+#define PAGE_SIZE 4096
> >+
> > #define FILE_DEBUG_FLAG DEBUG_BUFMGR
> >
> > static inline int
> >@@ -181,19 +183,45 @@ bo_tile_pitch(struct brw_bufmgr *bufmgr, uint32_t
> >pitch, uint32_t tiling)
> >return ALIGN(pitch, tile_width);
> > }
> >
> >+static inline int
> >+ilog2_round_up(int value)
> >+{
> >+   assert(value != 0);
> >+   return 32 - __builtin_clz(value - 1); }
> >+
> >+/*
> >+ * This function finds the correct bucket fit for the input size.
> >+ * The function works with O(1) complexity when the requested size
> >+ * was queried instead of iterating the size through all the buckets.
> >+ */
> > static struct bo_cache_bucket *
> > bucket_for_size(struct brw_bufmgr *bufmgr, uint64_t size)  {
> >-   int i;
> >+   int index = -1;
> >+   int row, col = 0;
> >+   int pages, pages_log2;
> >
> >-   for (i = 0; i < bufmgr->num_buckets; i++) {
> >-  struct bo_cache_bucket *bucket = >cache_bucket[i];
> >-  if (bucket->size >= size) {
> >- return bucket;
> >-  }
> >+   /* condition for size less  than 4*4096 (16KB) page size */
> >+   if(size <= 4 * PAGE_SIZE) {
> >+  index = DIV_ROUND_UP(size, PAGE_SIZE) - 1;;
> >+   } else {
> >+  /* Number of pages of page size */
> >+  pages = DIV_ROUND_UP(size, PAGE_SIZE);
> >+  pages_log2 = ilog2_round_up(pages) - 1;
> >+
> >+  /* Finding the row and column of the matrix */
> >+  row = pages_log2 - 1;
> >+  col = DIV_ROUND_UP((pages - (1 << pages_log2)),
> >+(1 << (pages_log2 - 2)));
> >+
> >+  /* Using the calculated row and column to index into the matrix */
> >+  index = (row << 2) + (col - 1);
> >}
> >
> >-   return NULL;
> >+   /* Checking the error condition */
> >+   return (index >= 0 && index < bufmgr->num_buckets) ?
> >+  (>cache_bucket[index]) : NULL;
> > }
> >
> > int
> >@@ -1239,6 +1267,10 @@ add_bucket(struct brw_bufmgr *bufmgr, int size)
> >list_inithead(>cache_bucket[i].head);
> >bufmgr->cache_bucket[i].size = size;
> >bufmgr->num_buckets++;
> >+
> >+   

Re: [Mesa-dev] Using --enable-opencl-icd by default and deprecating the toggle

[Jan Vesely]

On Fri, 2017-09-29 at 16:14 +0100, Emil Velikov wrote:
> Hi all,
> 
> Currently nearly all the distributions I've seen* enable and use the ICD.
> Only Gentoo does not use it, but manages the OpenCL.so conflicts via eselect.

to be fair, you can install and eselect ocl-icd. eselect switches
libOpenCL.so providers, and mesa is one of them.

> 
> They have the ocl-icd library as a separate option, which makes me
> wonder how that's supposed to work. After all, for it to work the
> vendor package should:
> a) provided a binary not called libOpenCL.so (it could be called like
> that, but must be outside of ld's search path)
> b) provide a $foo.icd file, listing the ICD file/path name
> 
> Most likely I'm having a dull moment somewhere and things work just fine.
> 
> Considering that the --enable-opencl-icd is almost always set, I think
> we should change the default.

Dieter recently reported that building with --enable-opencl-icd
produces broken libOpenCL.so library (in addition to client
libMesaOpenCL.so) [0]. It'd be nice if mesa libOpenCL.so could act as
ICD loader when built with --enable-opencl-icd.

Jan

[0] https://lists.freedesktop.org/archives/mesa-dev/2017-September/1709
11.html

> Deprecating and removing it (at a later stage) also a nice option,
> since it will allow us to do some tidy-ups.
> 
> What do you guys think? I'd love to hear people's thoughts about this.
> 
> Thanks
> Emil
> 
> *Fedora, Suse, Arch, Debian, Ubuntu, FreeBSD
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-- 
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Re: [Mesa-dev] [PATCH 4/4] i965/gen10: Implement Wa3DStateMode

[Jason Ekstrand]

On Mon, Oct 2, 2017 at 4:08 PM, Anuj Phogat  wrote:

> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index a1bf54dc72..c224355a2b 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -88,8 +88,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> if (devinfo->gen == 10) {
>BEGIN_BATCH(2);
>OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
> -  OUT_BATCH(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE << 16 |
> -GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
> +  /* From gen10 workaround table in h/w specs:
> +   * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
> +   *  a value of 0x"
> +   */
> +  OUT_BATCH(0x << 16 | GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
>

Bits 31:16 are the mask bits.  By programming them to 0x, you're making
it write the entire register and not just the float blend optimization
enable bit.  If we're going to do that, we need to figure out what values
we want in the other fields and always set them along with the float blend
optimization enable bit.

--Jason


>ADVANCE_BATCH();
> }
>
> --
> 2.13.5
>
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Re: [Mesa-dev] [PATCH 1/4] i965/gen10: Implement WaSampleOffsetIZ workaround

[Jason Ekstrand]

On Mon, Oct 2, 2017 at 4:07 PM, Anuj Phogat  wrote:

> WaFlushHangWhenNonPipelineStateAndMarkerStalled goes along
> with WaSampleOffsetIZ. Both recommends the same.
>
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_context.h|  2 +
>  src/mesa/drivers/dri/i965/brw_defines.h|  1 +
>  src/mesa/drivers/dri/i965/brw_pipe_control.c   | 54
> ++
>  src/mesa/drivers/dri/i965/gen8_multisample_state.c |  8 
>  4 files changed, 65 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 92fc16de13..f0e8d562e9 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1647,6 +1647,8 @@ void brw_emit_post_sync_nonzero_flush(struct
> brw_context *brw);
>  void brw_emit_depth_stall_flushes(struct brw_context *brw);
>  void gen7_emit_vs_workaround_flush(struct brw_context *brw);
>  void gen7_emit_cs_stall_flush(struct brw_context *brw);
> +void gen10_emit_wa_cs_stall_flush(struct brw_context *brw);
> +void gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw);
>
>  /* brw_queryformat.c */
>  void brw_query_internal_format(struct gl_context *ctx, GLenum target,
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 4abb790612..270cdf29db 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1609,6 +1609,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>  #define GEN7_GPGPU_DISPATCHDIMY 0x2504
>  #define GEN7_GPGPU_DISPATCHDIMZ 0x2508
>
> +#define GEN7_CACHE_MODE_0   0x7000
>  #define GEN7_CACHE_MODE_1   0x7004
>  # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
>  # define GEN8_HIZ_NP_PMA_FIX_ENABLE(1 << 11)
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 460b8f73b6..6326957a7a 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -278,6 +278,60 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
> brw->workaround_bo, 0, 0);
>  }
>
> +static void
> +brw_flush_write_caches(struct brw_context *brw) {
> +   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS);
> +}
> +
> +static void
> +brw_flush_read_caches(struct brw_context *brw) {
> +   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_INVALIDATE_BITS);
> +}
> +
> +/**
> + * From Gen10 Workarounds page in h/w specs:
> + * WaSampleOffsetIZ:
> + * Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
> + * markers in the pipeline by programming a PIPE_CONTROL with stall.
> + */
> +void
> +gen10_emit_wa_cs_stall_flush(struct brw_context *brw)
> +{
> +   const struct gen_device_info *devinfo = >screen->devinfo;
> +   assert(devinfo->gen == 10);
> +   brw_emit_pipe_control_flush(brw,
> +   PIPE_CONTROL_CS_STALL |
> +   PIPE_CONTROL_STALL_AT_SCOREBOARD);
> +}
> +
> +/**
> + * From Gen10 Workarounds page in h/w specs:
> + * WaSampleOffsetIZ:
> + * When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
> + * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and
> 0x7FFF(SVL)
> + * after the command to ensure the state has been delivered prior to any
> + * command causing a marker in the pipeline.
> + */
> +void
> +gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw)
> +{
> +   const struct gen_device_info *devinfo = >screen->devinfo;
> +   assert(devinfo->gen == 10);
> +
> +   /* Before changing the value of CACHE_MODE_0 register, GFX pipeline
> must
> +* be idle; i.e., full flush is required.
> +*/
> +   brw_flush_write_caches(brw);
> +   brw_flush_read_caches(brw);
>

If you do

brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS |
 PIPE_CONTROL_CACHE_INVALIDATE_BITS)

It will automatically do both and insert a stall between them.  What you
have above, I don't think will actually every CS stall which appears to be
required when changing CACHE_MODE_0


> +
> +   /* Write to CACHE_MODE_0 (0x7000) */
> +   BEGIN_BATCH(3);
> +   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> +   OUT_BATCH(GEN7_CACHE_MODE_0);
> +   OUT_BATCH(0);
>

I believe this won't actually change the register which is good.  But is
that sufficient for the workaround?

+   ADVANCE_BATCH();
> +}
> +
>  /**
>   * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
>   * implementing two workarounds on gen6.  From section 1.4.7.1
> diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> index 7a31a5df4a..14043025b6 100644
> --- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> 

[Mesa-dev] [PATCH 6/6] tgsi/scan: scan address operands (v2)

[Marek Olšák]

From: Marek Olšák 

v2: set swizzled usage mask
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 43 +-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 1f8904c..989c57e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -451,20 +451,43 @@ scan_instruction(struct tgsi_shader_info *info,
fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
   info->uses_doubles = TRUE;
 
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
   scan_src_operand(info, fullinst, >Src[i], i,
tgsi_util_get_inst_usage_mask(fullinst, i),
is_interp_instruction, _mem_inst);
+
+  if (fullinst->Src[i].Register.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = fullinst->Src[i].Indirect.File;
+ src.Register.Index = fullinst->Src[i].Indirect.Index;
+
+ scan_src_operand(info, fullinst, , -1,
+  1 << fullinst->Src[i].Indirect.Swizzle,
+  false, NULL);
+  }
+
+  if (fullinst->Src[i].Register.Dimension &&
+  fullinst->Src[i].Dimension.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = fullinst->Src[i].DimIndirect.File;
+ src.Register.Index = fullinst->Src[i].DimIndirect.Index;
+
+ scan_src_operand(info, fullinst, , -1,
+  1 << fullinst->Src[i].DimIndirect.Swizzle,
+  false, NULL);
+  }
}
 
if (fullinst->Instruction.Texture) {
   for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
  struct tgsi_full_src_register src = {{0}};
 
  src.Register.File = fullinst->TexOffsets[i].File;
  src.Register.Index = fullinst->TexOffsets[i].Index;
 
  /* The usage mask is suboptimal but should be safe. */
@@ -472,27 +495,45 @@ scan_instruction(struct tgsi_shader_info *info,
   (1 << fullinst->TexOffsets[i].SwizzleX) |
   (1 << fullinst->TexOffsets[i].SwizzleY) |
   (1 << fullinst->TexOffsets[i].SwizzleZ),
   false, _mem_inst);
   }
}
 
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
   const struct tgsi_full_dst_register *dst = >Dst[i];
+
   if (dst->Register.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = dst->Indirect.File;
+ src.Register.Index = dst->Indirect.Index;
+
+ scan_src_operand(info, fullinst, , -1,
+  1 << dst->Indirect.Swizzle, false, NULL);
+
  info->indirect_files |= (1 << dst->Register.File);
  info->indirect_files_written |= (1 << dst->Register.File);
   }
 
-  if (dst->Register.Dimension && dst->Dimension.Indirect)
+  if (dst->Register.Dimension && dst->Dimension.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = dst->DimIndirect.File;
+ src.Register.Index = dst->DimIndirect.Index;
+
+ scan_src_operand(info, fullinst, , -1,
+  1 << dst->DimIndirect.Swizzle, false, NULL);
+
  info->dim_indirect_files |= 1u << dst->Register.File;
+  }
 
   if (is_memory_file(dst->Register.File)) {
  assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
 
  is_mem_inst = true;
  info->writes_memory = TRUE;
 
  if (dst->Register.File == TGSI_FILE_IMAGE) {
 if (dst->Register.Indirect)
info->images_store = info->images_declared;
-- 
2.7.4

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[Mesa-dev] [PATCH 4/6] tgsi/scan: take advantage of already swizzled usage mask in scan_src_operand

[Marek Olšák]

From: Marek Olšák 

It has always been a usage mask *after* swizzling.
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 47 --
 1 file changed, 17 insertions(+), 30 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 6f87f8d..ee9a261 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -100,98 +100,85 @@ computes_derivative(unsigned opcode)
   opcode == TGSI_OPCODE_SAMPLE_B ||
   opcode == TGSI_OPCODE_SAMPLE_C;
 }
 
 
 static void
 scan_src_operand(struct tgsi_shader_info *info,
  const struct tgsi_full_instruction *fullinst,
  const struct tgsi_full_src_register *src,
  unsigned src_index,
- unsigned usage_mask,
+ unsigned usage_mask_after_swizzle,
  bool is_interp_instruction,
  bool *is_mem_inst)
 {
int ind = src->Register.Index;
 
if (info->processor == PIPE_SHADER_COMPUTE &&
src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
-  unsigned swizzle[4], i, name;
+  unsigned name, mask;
 
   name = info->system_value_semantic_name[src->Register.Index];
-  swizzle[0] = src->Register.SwizzleX;
-  swizzle[1] = src->Register.SwizzleY;
-  swizzle[2] = src->Register.SwizzleZ;
-  swizzle[3] = src->Register.SwizzleW;
 
   switch (name) {
   case TGSI_SEMANTIC_THREAD_ID:
   case TGSI_SEMANTIC_BLOCK_ID:
- for (i = 0; i < 4; i++) {
-if (swizzle[i] <= TGSI_SWIZZLE_Z) {
-   if (name == TGSI_SEMANTIC_THREAD_ID)
-  info->uses_thread_id[swizzle[i]] = true;
-   else
-  info->uses_block_id[swizzle[i]] = true;
-}
+ mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
+ while (mask) {
+unsigned i = u_bit_scan();
+
+if (name == TGSI_SEMANTIC_THREAD_ID)
+   info->uses_thread_id[i] = true;
+else
+   info->uses_block_id[i] = true;
  }
  break;
   case TGSI_SEMANTIC_BLOCK_SIZE:
  /* The block size is translated to IMM with a fixed block size. */
  if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 info->uses_block_size = true;
  break;
   case TGSI_SEMANTIC_GRID_SIZE:
  info->uses_grid_size = true;
  break;
   }
}
 
/* Mark which inputs are effectively used */
if (src->Register.File == TGSI_FILE_INPUT) {
   if (src->Register.Indirect) {
  for (ind = 0; ind < info->num_inputs; ++ind) {
-info->input_usage_mask[ind] |= usage_mask;
+info->input_usage_mask[ind] |= usage_mask_after_swizzle;
  }
   } else {
  assert(ind >= 0);
  assert(ind < PIPE_MAX_SHADER_INPUTS);
- info->input_usage_mask[ind] |= usage_mask;
+ info->input_usage_mask[ind] |= usage_mask_after_swizzle;
   }
 
   if (info->processor == PIPE_SHADER_FRAGMENT) {
  unsigned name, index, input;
 
  if (src->Register.Indirect && src->Indirect.ArrayID)
 input = info->input_array_first[src->Indirect.ArrayID];
  else
 input = src->Register.Index;
 
  name = info->input_semantic_name[input];
  index = info->input_semantic_index[input];
 
  if (name == TGSI_SEMANTIC_POSITION &&
- (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
-  src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
-  src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
-  src->Register.SwizzleW == TGSI_SWIZZLE_Z))
-info->reads_z = TRUE;
-
- if (name == TGSI_SEMANTIC_COLOR) {
-unsigned mask =
-   (1 << src->Register.SwizzleX) |
-   (1 << src->Register.SwizzleY) |
-   (1 << src->Register.SwizzleZ) |
-   (1 << src->Register.SwizzleW);
-
-info->colors_read |= mask << (index * 4);
- }
+ usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
+info->reads_z = true;
+
+ if (name == TGSI_SEMANTIC_COLOR)
+info->colors_read |= usage_mask_after_swizzle << (index * 4);
 
  /* Process only interpolated varyings. Don't include POSITION.
   * Don't include integer varyings, because they are not
   * interpolated. Don't process inputs interpolated by INTERP
   * opcodes. Those are tracked separately.
   */
  if ((!is_interp_instruction || src_index != 0) &&
  (name == TGSI_SEMANTIC_GENERIC ||
   name == TGSI_SEMANTIC_TEXCOORD ||
   name == TGSI_SEMANTIC_COLOR ||
-- 
2.7.4

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[Mesa-dev] [PATCH 2/6] tgsi: implement tgsi_util_get_inst_usage_mask properly

[Marek Olšák]

From: Marek Olšák 

All opcodes are handled.
---
 src/gallium/auxiliary/tgsi/tgsi_util.c| 307 ++
 src/gallium/auxiliary/tgsi/tgsi_util.h|  12 +
 src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c |  11 -
 3 files changed, 206 insertions(+), 124 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c 
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index 327e42f..be8bcdf 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -20,23 +20,25 @@
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  * 
  **/
 
 #include "util/u_debug.h"
 #include "pipe/p_shader_tokens.h"
+#include "tgsi_info.h"
 #include "tgsi_parse.h"
 #include "tgsi_util.h"
 #include "tgsi_exec.h"
+#include "util/bitscan.h"
 
 union pointer_hack
 {
void *pointer;
uint64_t uint64;
 };
 
 void *
 tgsi_align_128bit(
void *unaligned )
@@ -173,162 +175,241 @@ unsigned
 tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst,
   unsigned src_idx)
 {
const struct tgsi_full_src_register *src = >Src[src_idx];
unsigned write_mask = inst->Dst[0].Register.WriteMask;
unsigned read_mask;
unsigned usage_mask;
unsigned chan;
 
switch (inst->Instruction.Opcode) {
-   case TGSI_OPCODE_MOV:
-   case TGSI_OPCODE_ARL:
-   case TGSI_OPCODE_ARR:
+   case TGSI_OPCODE_IF:
+   case TGSI_OPCODE_UIF:
+   case TGSI_OPCODE_EMIT:
+   case TGSI_OPCODE_ENDPRIM:
case TGSI_OPCODE_RCP:
-   case TGSI_OPCODE_MUL:
-   case TGSI_OPCODE_DIV:
-   case TGSI_OPCODE_ADD:
-   case TGSI_OPCODE_MIN:
-   case TGSI_OPCODE_MAX:
-   case TGSI_OPCODE_SLT:
-   case TGSI_OPCODE_SGE:
-   case TGSI_OPCODE_MAD:
-   case TGSI_OPCODE_LRP:
-   case TGSI_OPCODE_FMA:
-   case TGSI_OPCODE_FRC:
-   case TGSI_OPCODE_CEIL:
-   case TGSI_OPCODE_FLR:
-   case TGSI_OPCODE_ROUND:
-   case TGSI_OPCODE_POW:
-   case TGSI_OPCODE_COS:
-   case TGSI_OPCODE_SIN:
-   case TGSI_OPCODE_DDX:
-   case TGSI_OPCODE_DDY:
-   case TGSI_OPCODE_SEQ:
-   case TGSI_OPCODE_SGT:
-   case TGSI_OPCODE_SLE:
-   case TGSI_OPCODE_SNE:
-   case TGSI_OPCODE_SSG:
-   case TGSI_OPCODE_CMP:
-   case TGSI_OPCODE_TRUNC:
-   case TGSI_OPCODE_NOT:
-   case TGSI_OPCODE_AND:
-   case TGSI_OPCODE_OR:
-   case TGSI_OPCODE_XOR:
-   case TGSI_OPCODE_FSEQ:
-   case TGSI_OPCODE_FSGE:
-   case TGSI_OPCODE_FSLT:
-   case TGSI_OPCODE_FSNE:
-   case TGSI_OPCODE_F2I:
-   case TGSI_OPCODE_IDIV:
-   case TGSI_OPCODE_IMAX:
-   case TGSI_OPCODE_IMIN:
-   case TGSI_OPCODE_INEG:
-   case TGSI_OPCODE_ISGE:
-   case TGSI_OPCODE_ISHR:
-   case TGSI_OPCODE_ISLT:
-   case TGSI_OPCODE_F2U:
-   case TGSI_OPCODE_U2F:
-   case TGSI_OPCODE_UADD:
-   case TGSI_OPCODE_UDIV:
-   case TGSI_OPCODE_UMAD:
-   case TGSI_OPCODE_UMAX:
-   case TGSI_OPCODE_UMIN:
-   case TGSI_OPCODE_UMOD:
-   case TGSI_OPCODE_UMUL:
-   case TGSI_OPCODE_USEQ:
-   case TGSI_OPCODE_USGE:
-   case TGSI_OPCODE_USHR:
-   case TGSI_OPCODE_USLT:
-   case TGSI_OPCODE_USNE:
-   case TGSI_OPCODE_IMUL_HI:
-   case TGSI_OPCODE_UMUL_HI:
-   case TGSI_OPCODE_DDX_FINE:
-   case TGSI_OPCODE_DDY_FINE:
-  /* Channel-wise operations */
-  read_mask = write_mask;
-  break;
-
+   case TGSI_OPCODE_RSQ:
+   case TGSI_OPCODE_SQRT:
case TGSI_OPCODE_EX2:
case TGSI_OPCODE_LG2:
+   case TGSI_OPCODE_SIN:
+   case TGSI_OPCODE_COS:
+   case TGSI_OPCODE_POW: /* reads src0.x and src1.x */
+   case TGSI_OPCODE_UP2H:
+   case TGSI_OPCODE_UP2US:
+   case TGSI_OPCODE_UP4B:
+   case TGSI_OPCODE_UP4UB:
+   case TGSI_OPCODE_MEMBAR:
+   case TGSI_OPCODE_BALLOT:
   read_mask = TGSI_WRITEMASK_X;
   break;
 
-   case TGSI_OPCODE_EXP:
-   case TGSI_OPCODE_LOG:
-  read_mask = write_mask & TGSI_WRITEMASK_XYZ ? TGSI_WRITEMASK_X : 0;
-  break;
-
case TGSI_OPCODE_DP2:
+   case TGSI_OPCODE_PK2H:
+   case TGSI_OPCODE_PK2US:
+   case TGSI_OPCODE_DFRACEXP:
+   case TGSI_OPCODE_F2D:
+   case TGSI_OPCODE_I2D:
+   case TGSI_OPCODE_U2D:
+   case TGSI_OPCODE_F2U64:
+   case TGSI_OPCODE_F2I64:
+   case TGSI_OPCODE_U2I64:
+   case TGSI_OPCODE_I2I64:
+   case TGSI_OPCODE_TXQS: /* bindless handle possible */
+   case TGSI_OPCODE_RESQ: /* bindless handle possible */
   read_mask = TGSI_WRITEMASK_XY;
   break;
 
+   case TGSI_OPCODE_TXQ:
+  if (src_idx == 0)
+ read_mask = TGSI_WRITEMASK_X;
+  else
+ read_mask = TGSI_WRITEMASK_XY;  /* bindless handle possible */
+  break;
+
case TGSI_OPCODE_DP3:
   read_mask = TGSI_WRITEMASK_XYZ;
   break;
 
case TGSI_OPCODE_DP4:
+   case TGSI_OPCODE_PK4B:
+   case TGSI_OPCODE_PK4UB:
+   case 

[Mesa-dev] [PATCH 5/6] tgsi/scan: set correct usage mask for tex offsets in scan_src_operand

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index ee9a261..1f8904c 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -459,26 +459,26 @@ scan_instruction(struct tgsi_shader_info *info,
tgsi_util_get_inst_usage_mask(fullinst, i),
is_interp_instruction, _mem_inst);
}
 
if (fullinst->Instruction.Texture) {
   for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
  struct tgsi_full_src_register src = {{0}};
 
  src.Register.File = fullinst->TexOffsets[i].File;
  src.Register.Index = fullinst->TexOffsets[i].Index;
- src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
- src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
- src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
 
  /* The usage mask is suboptimal but should be safe. */
- scan_src_operand(info, fullinst, , -1, TGSI_WRITEMASK_XYZ,
+ scan_src_operand(info, fullinst, , -1,
+  (1 << fullinst->TexOffsets[i].SwizzleX) |
+  (1 << fullinst->TexOffsets[i].SwizzleY) |
+  (1 << fullinst->TexOffsets[i].SwizzleZ),
   false, _mem_inst);
   }
}
 
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
   const struct tgsi_full_dst_register *dst = >Dst[i];
   if (dst->Register.Indirect) {
  info->indirect_files |= (1 << dst->Register.File);
  info->indirect_files_written |= (1 << dst->Register.File);
-- 
2.7.4

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[Mesa-dev] [PATCH 3/6] tgsi/scan: set non-valid src_index for tex offsets in scan_src_operand

[Marek Olšák]

From: Marek Olšák 

tex offsets are not "Src" operands.
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 212d1bb..6f87f8d 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -477,21 +477,21 @@ scan_instruction(struct tgsi_shader_info *info,
   for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
  struct tgsi_full_src_register src = {{0}};
 
  src.Register.File = fullinst->TexOffsets[i].File;
  src.Register.Index = fullinst->TexOffsets[i].Index;
  src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
  src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
  src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
 
  /* The usage mask is suboptimal but should be safe. */
- scan_src_operand(info, fullinst, , 0, TGSI_WRITEMASK_XYZ,
+ scan_src_operand(info, fullinst, , -1, TGSI_WRITEMASK_XYZ,
   false, _mem_inst);
   }
}
 
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
   const struct tgsi_full_dst_register *dst = >Dst[i];
   if (dst->Register.Indirect) {
  info->indirect_files |= (1 << dst->Register.File);
  info->indirect_files_written |= (1 << dst->Register.File);
-- 
2.7.4

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[Mesa-dev] [PATCH 1/6] tgsi: add docs for some existing pack opcodes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/docs/source/tgsi.rst | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 551e9dd..1a51fe9 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -410,31 +410,49 @@ while DDY is allowed to be the same for the entire 2x2 
quad.
 
 This instruction replicates its result.
 
 .. math::
 
   dst = f32\_to\_f16(src.x) | f32\_to\_f16(src.y) << 16
 
 
 .. opcode:: PK2US - Pack Two Unsigned 16-bit Scalars
 
-  TBD
+This instruction replicates its result.
+
+.. math::
+
+  dst = f32\_to\_unorm16(src.x) | f32\_to\_unorm16(src.y) << 16
 
 
 .. opcode:: PK4B - Pack Four Signed 8-bit Scalars
 
-  TBD
+This instruction replicates its result.
+
+.. math::
+
+  dst = f32\_to\_snorm8(src.x) |
+(f32\_to\_snorm8(src.y) << 8) |
+(f32\_to\_snorm8(src.z) << 16) |
+(f32\_to\_snorm8(src.w) << 24)
 
 
 .. opcode:: PK4UB - Pack Four Unsigned 8-bit Scalars
 
-  TBD
+This instruction replicates its result.
+
+.. math::
+
+  dst = f32\_to\_unorm8(src.x) |
+(f32\_to\_unorm8(src.y) << 8) |
+(f32\_to\_unorm8(src.z) << 16) |
+(f32\_to\_unorm8(src.w) << 24)
 
 
 .. opcode:: SEQ - Set On Equal
 
 .. math::
 
   dst.x = (src0.x == src1.x) ? 1.0F : 0.0F
 
   dst.y = (src0.y == src1.y) ? 1.0F : 0.0F
 
-- 
2.7.4

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[Mesa-dev] [PATCH] wayland-egl: redistribute wayland.egl.h include

[Tobias Klausmann]

Starting with commit ab0589c6ed ("wayland-egl: remove no longer needed
wayland-client dependency") the wayland-egl.h include was missing leading to a
build failure:

  CC   wayland-egl.lo
wayland-egl.c:33:10: fatal error: wayland-egl.h: Datei oder Verzeichnis nicht
gefunden
 #include "wayland-egl.h"
  ^~~

Signed-off-by: Tobias Klausmann 
Fixes: ab0589c6ed ("swayland-egl: remove no longer needed wayland-client
dependency")
---
 src/egl/wayland/wayland-egl/Makefile.am | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
b/src/egl/wayland/wayland-egl/Makefile.am
index 08a6768049..730fd03ddb 100644
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ b/src/egl/wayland/wayland-egl/Makefile.am
@@ -2,7 +2,8 @@ pkgconfigdir = $(libdir)/pkgconfig
 pkgconfig_DATA = wayland-egl.pc
 
 AM_CFLAGS = $(DEFINES) \
-   $(VISIBILITY_CFLAGS)
+   $(VISIBILITY_CFLAGS) \
+   $(WAYLAND_SERVER_CFLAGS)
 
 lib_LTLIBRARIES = libwayland-egl.la
 noinst_HEADERS = wayland-egl-backend.h
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 1/2] anv: Fix vkCmdFillBuffer()

[Lionel Landwerlin]

Thanks, I modified the CTS slightly to reproduce the problem (will try 
to send it upstream).


Reviewed-by: Lionel Landwerlin 

On 02/10/17 20:41, Józef Kucia wrote:

On Mon, Oct 2, 2017 at 9:19 PM, Lionel Landwerlin
 wrote:

I guess it makes things clearer.
Does this fix something?

Yes, it fixes buffer fills. After the change buffers are filled with
uint32_t values instead of uint8_t or uint16_t values.

Before the change, when the fill value is 0xabcdef buffers are filled
with 0xcdefcdef or 0xefefefef.



On 02/10/17 18:58, Józef Kucia wrote:

The vkCmdFillBuffer() command fills a buffer with an uint32_t value.
---
   src/intel/vulkan/anv_blorp.c | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8d0c275248..a8ebdb384c 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -533,8 +533,8 @@ isl_format_for_size(unsigned size_B)
  switch (size_B) {
  case 1:  return ISL_FORMAT_R8_UINT;
  case 2:  return ISL_FORMAT_R8G8_UINT;
-   case 4:  return ISL_FORMAT_R8G8B8A8_UINT;
-   case 8:  return ISL_FORMAT_R16G16B16A16_UINT;
+   case 4:  return ISL_FORMAT_R32_UINT;
+   case 8:  return ISL_FORMAT_R32G32_UINT;
  case 16: return ISL_FORMAT_R32G32B32A32_UINT;
  default:
 unreachable("Not a power-of-two format size");





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Re: [Mesa-dev] [PATCH 0/4] i965: ARB_indirect_parameters

[Kenneth Graunke]

On Monday, October 2, 2017 1:58:23 PM PDT Plamena Manolova wrote:
> A series of patches introducing ARB_indirect_parameters
> for i965. We can implement ARB_indirect_parameters for i965
> by taking advantage of the conditional rendering mechanism.
> This works by issuing maxdrawcount draw calls and using
> conditional rendering to predicate each of them with
> "drawcount > gl_DrawID". The first three patches are part
> of a necessary refactor of brw_try_draw_prims while the last
> one actually introduces the functionality.
> 
> Plamena Manolova (4):
>   i965: Introduce brw_prepare_drawing.
>   i965: Indroduce brw_finish_drawing.
>   i965: Refactor brw_try_draw_prims.
>   i965: Implement ARB_indirect_parameters.
> 
>  src/mesa/drivers/dri/i965/brw_context.h  |   8 +
>  src/mesa/drivers/dri/i965/brw_draw.c | 384 
> ++-
>  src/mesa/drivers/dri/i965/brw_draw.h |  10 +
>  src/mesa/drivers/dri/i965/intel_extensions.c |   4 +-
>  4 files changed, 273 insertions(+), 133 deletions(-)

Looks great, Pam!  Thank you!

Series is:
Reviewed-by: Kenneth Graunke 

and pushed:

To ssh://git.freedesktop.org/git/mesa/mesa
   765e1fa3724..598d613dc31  master -> master



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[Mesa-dev] [Bug 103018] Add account for Rhys Kidd

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103018

Kenneth Graunke  changed:

   What|Removed |Added

  Component|Other   |New Accounts
Product|Mesa|freedesktop.org
 QA Contact|mesa-dev@lists.freedesktop. |
   |org |
Version|git |unspecified
 Status|NEW |ASSIGNED
   Assignee|mesa-dev@lists.freedesktop. |sitewranglers@lists.freedes
   |org |ktop.org

--- Comment #3 from Kenneth Graunke  ---
Approved.  Rhys has been around a long time and contributed useful patches.

Please add him to the 'mesa' and 'piglit' groups.  (shader-db is just part of
the mesa group, nothing special to do there.)

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[Mesa-dev] [PATCH 2/4] i965/gen10: Implement WaForceRCPFEHangWorkaround

[Anuj Phogat]

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 6326957a7a..3192d31758 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -89,6 +89,22 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context 
*brw, uint32_t flags)
return 0;
 }
 
+/* #1130 from gen10 workarounds page in h/w specs:
+ * "If a PIPE_CONTROL performs Render Target Cache Flush, function sets stall
+ * at Pixel Scoreboard. Otherwise, the function assumes that PIPE_CONTROL
+ * performs Post Sync Operation and WA sets Depth Stall Enable.
+ *
+ * Applicable to CNL B0 and C0 steppings only.
+ */
+static void
+gen10_add_rcpfe_workaround_bits(uint32_t *flags)
+{
+   if ((*flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) != 0)
+  *flags = *flags | PIPE_CONTROL_STALL_AT_SCOREBOARD;
+   else
+  *flags = *flags | PIPE_CONTROL_DEPTH_STALL;
+}
+
 static void
 brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
   struct brw_bo *bo, uint32_t offset, uint64_t imm)
@@ -109,6 +125,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
flags,
  brw_emit_pipe_control_flush(brw, 0);
   }
 
+  if (devinfo->gen == 10)
+ gen10_add_rcpfe_workaround_bits();
+
   BEGIN_BATCH(6);
   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
   OUT_BATCH(flags);
-- 
2.13.5

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[Mesa-dev] [PATCH 4/4] i965/gen10: Implement Wa3DStateMode

[Anuj Phogat]

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index a1bf54dc72..c224355a2b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -88,8 +88,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
if (devinfo->gen == 10) {
   BEGIN_BATCH(2);
   OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
-  OUT_BATCH(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE << 16 |
-GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+  /* From gen10 workaround table in h/w specs:
+   * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
+   *  a value of 0x"
+   */
+  OUT_BATCH(0x << 16 | GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
   ADVANCE_BATCH();
}
 
-- 
2.13.5

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[Mesa-dev] [PATCH 3/4] i965/gen10: Enable float blend optimization

[Anuj Phogat]

This optimization is enabled for previous generations too.
See Mesa commit c17e214a6b
On CNL this bit is moved to 3DSTATE_3D_MODE.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  | 3 +++
 src/mesa/drivers/dri/i965/brw_state_upload.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 270cdf29db..743b9d0a0d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1333,6 +1333,9 @@ enum brw_pixel_shader_coverage_mask_mode {
 /* DW2: start address */
 /* DW3: end address. */
 
+#define _3DSTATE_3D_MODE 0x791E
+# define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 9)
+
 #define CMD_MI_FLUSH  0x0200
 
 # define BLT_X_SHIFT   0
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7b31aad170..a1bf54dc72 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -85,6 +85,14 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   }
}
 
+   if (devinfo->gen == 10) {
+  BEGIN_BATCH(2);
+  OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
+  OUT_BATCH(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE << 16 |
+GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+  ADVANCE_BATCH();
+   }
+
if (devinfo->gen >= 8) {
   gen8_emit_3dstate_sample_pattern(brw);
 
-- 
2.13.5

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[Mesa-dev] [PATCH 1/4] i965/gen10: Implement WaSampleOffsetIZ workaround

[Anuj Phogat]

WaFlushHangWhenNonPipelineStateAndMarkerStalled goes along
with WaSampleOffsetIZ. Both recommends the same.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_context.h|  2 +
 src/mesa/drivers/dri/i965/brw_defines.h|  1 +
 src/mesa/drivers/dri/i965/brw_pipe_control.c   | 54 ++
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  8 
 4 files changed, 65 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 92fc16de13..f0e8d562e9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1647,6 +1647,8 @@ void brw_emit_post_sync_nonzero_flush(struct brw_context 
*brw);
 void brw_emit_depth_stall_flushes(struct brw_context *brw);
 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
 void gen7_emit_cs_stall_flush(struct brw_context *brw);
+void gen10_emit_wa_cs_stall_flush(struct brw_context *brw);
+void gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw);
 
 /* brw_queryformat.c */
 void brw_query_internal_format(struct gl_context *ctx, GLenum target,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 4abb790612..270cdf29db 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1609,6 +1609,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 #define GEN7_GPGPU_DISPATCHDIMY 0x2504
 #define GEN7_GPGPU_DISPATCHDIMZ 0x2508
 
+#define GEN7_CACHE_MODE_0   0x7000
 #define GEN7_CACHE_MODE_1   0x7004
 # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
 # define GEN8_HIZ_NP_PMA_FIX_ENABLE(1 << 11)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 460b8f73b6..6326957a7a 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -278,6 +278,60 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw->workaround_bo, 0, 0);
 }
 
+static void
+brw_flush_write_caches(struct brw_context *brw) {
+   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS);
+}
+
+static void
+brw_flush_read_caches(struct brw_context *brw) {
+   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_INVALIDATE_BITS);
+}
+
+/**
+ * From Gen10 Workarounds page in h/w specs:
+ * WaSampleOffsetIZ:
+ * Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
+ * markers in the pipeline by programming a PIPE_CONTROL with stall.
+ */
+void
+gen10_emit_wa_cs_stall_flush(struct brw_context *brw)
+{
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   assert(devinfo->gen == 10);
+   brw_emit_pipe_control_flush(brw,
+   PIPE_CONTROL_CS_STALL |
+   PIPE_CONTROL_STALL_AT_SCOREBOARD);
+}
+
+/**
+ * From Gen10 Workarounds page in h/w specs:
+ * WaSampleOffsetIZ:
+ * When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
+ * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
+ * after the command to ensure the state has been delivered prior to any
+ * command causing a marker in the pipeline.
+ */
+void
+gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw)
+{
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   assert(devinfo->gen == 10);
+
+   /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
+* be idle; i.e., full flush is required.
+*/
+   brw_flush_write_caches(brw);
+   brw_flush_read_caches(brw);
+
+   /* Write to CACHE_MODE_0 (0x7000) */
+   BEGIN_BATCH(3);
+   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+   OUT_BATCH(GEN7_CACHE_MODE_0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
+
 /**
  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
  * implementing two workarounds on gen6.  From section 1.4.7.1
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index 7a31a5df4a..14043025b6 100644
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -49,6 +49,11 @@ gen8_emit_3dstate_multisample(struct brw_context *brw, 
unsigned num_samples)
 void
 gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
+
+   if (devinfo->gen == 10)
+  gen10_emit_wa_cs_stall_flush(brw);
+
BEGIN_BATCH(9);
OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
 
@@ -68,4 +73,7 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
/* 1x and 2x MSAA */
OUT_BATCH(brw_multisample_positions_1x_2x);
ADVANCE_BATCH();
+
+   if (devinfo->gen == 10)
+  gen10_emit_wa_lri_to_cache_mode_zero(brw);
 }
-- 
2.13.5

[Mesa-dev] [PATCH] intel: Always set Cube Face Enables for all surfaces.

[Kenneth Graunke]

These shouldn't matter for non-cubes, and we always enable them all
for cubes, so we may as well set them all the time.  While we're at it,
let's make the genxml fields consistent.  We pick the boolean-per-face
approach because it's clear which bits correspond to which cube faces.

v2: Don't use "mbo" (requested by Matt and Jason).
---
 src/intel/genxml/gen4.xml |  7 ++-
 src/intel/genxml/gen45.xml|  7 ++-
 src/intel/genxml/gen5.xml |  7 ++-
 src/intel/genxml/gen6.xml |  7 ++-
 src/intel/genxml/gen7.xml |  7 ++-
 src/intel/genxml/gen75.xml|  7 ++-
 src/intel/isl/isl_surface_state.c | 18 ++
 7 files changed, 42 insertions(+), 18 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 6499346c999..fc24329535d 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -526,7 +526,12 @@
 
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 0f905754071..c91085831ea 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -531,7 +531,12 @@
   
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 70f50076abf..93e687a32bd 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -636,7 +636,12 @@
 
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 8aa03355055..96f4be784e3 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -574,7 +574,12 @@
   
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 993d10264fa..cc17018b582 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -638,7 +638,12 @@
   
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 105effa8cef..cb408a2bb8d 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -657,7 +657,12 @@
   
   
 
-
+
+
+
+
+
+
 
 
 
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index c6a55ce9707..bfb27fa4a44 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -452,18 +452,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
s.RenderCacheReadWriteMode = 0;
 #endif
 
-   if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
-#if GEN_GEN >= 8
-  s.CubeFaceEnablePositiveZ = 1;
-  s.CubeFaceEnableNegativeZ = 1;
-  s.CubeFaceEnablePositiveY = 1;
-  s.CubeFaceEnableNegativeY = 1;
-  s.CubeFaceEnablePositiveX = 1;
-  s.CubeFaceEnableNegativeX = 1;
-#else
-  s.CubeFaceEnables = 0x3f;
-#endif
-   }
+   s.CubeFaceEnablePositiveZ = 1;
+   s.CubeFaceEnableNegativeZ = 1;
+   s.CubeFaceEnablePositiveY = 1;
+   s.CubeFaceEnableNegativeY = 1;
+   s.CubeFaceEnablePositiveX = 1;
+   s.CubeFaceEnableNegativeX = 1;
 
 #if GEN_GEN >= 6
s.NumberofMultisamples = ffs(info->surf->samples) - 1;
-- 
2.14.2

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[Mesa-dev] [PATCH] util: include stdlib.h in u_string.h to silence MinGW warning

[Brian Paul]

Otherwise we don't get a prototype for malloc().
---
 src/util/u_string.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/util/u_string.h b/src/util/u_string.h
index 48f1125..5a2a3e9 100644
--- a/src/util/u_string.h
+++ b/src/util/u_string.h
@@ -38,6 +38,7 @@
 #if !defined(XF86_LIBC_H)
 #include 
 #endif
+#include 
 #include 
 #include 
 
-- 
1.9.1

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[Mesa-dev] [Bug 102597] [Regression] mpv, high rendering times (two to three times higher)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102597

--- Comment #9 from Niklas Haas  ---
> Thousands of mpv users rely on mesa's now incorrect behaviour to diagnose 
> performance issues.

Well, to be fair, that's going to end up being misleading one way or the other
- the timers are unreliable on so many platforms and configurations that using
them as the basis of a performance evaluation needs to be taken with a heavy
grain of salt. I also think these timers are only really relevant to developers
anyway; for users the only thing that really matters is whether or not it drops
frames (which mpv already displays separately).

> Are you going to revert that commit in accordance with the spec or are you 
> going to be stubborn and continue to violate it?

I don't think pestering the developers is going to help this issue progress; if
anything, it will accomplish the opposite.

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[Mesa-dev] [PATCH 2/2] egl/surfaceless: Use KMS swrast fallback

[gurchetansi...@chromium.org]

From: Gurchetan Singh 

The kms_swrast extension is an actively developed software fallback,
and platform_surfaceless can use it if there are no available
hardware drivers.

v2: Split into 2 patches, use booleans, check LIBGL_ALWAYS_SOFTWARE,
and modify the eglLog level (Emil, Eric, Tomasz).
---
 src/egl/drivers/dri2/platform_surfaceless.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index f6aa217d39..b0a43ac9de 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -36,6 +36,7 @@
 #include "egl_dri2.h"
 #include "egl_dri2_fallbacks.h"
 #include "loader.h"
+#include "util/debug.h"
 
 static __DRIimage*
 surfaceless_alloc_image(struct dri2_egl_display *dri2_dpy,
@@ -268,7 +269,7 @@ static const __DRIextension *image_loader_extensions[] = {
 };
 
 static bool
-surfaceless_probe_device(_EGLDisplay *dpy)
+surfaceless_probe_device(_EGLDisplay *dpy, bool swrast)
 {
struct dri2_egl_display *dri2_dpy = dpy->DriverData;
const int limit = 64;
@@ -286,7 +287,10 @@ surfaceless_probe_device(_EGLDisplay *dpy)
   if (fd < 0)
  continue;
 
-  dri2_dpy->driver_name = loader_get_driver_for_fd(fd);
+  if (swrast)
+ dri2_dpy->driver_name = strdup("kms_swrast");
+  else
+ dri2_dpy->driver_name = loader_get_driver_for_fd(fd);
   if (!dri2_dpy->driver_name) {
  close(fd);
  continue;
@@ -310,7 +314,7 @@ dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay 
*disp)
 {
struct dri2_egl_display *dri2_dpy;
const char* err;
-   int driver_loaded = 0;
+   bool driver_loaded = false;
 
loader_set_logger(_eglLog);
 
@@ -320,7 +324,14 @@ dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay 
*disp)
 
dri2_dpy->fd = -1;
disp->DriverData = (void *) dri2_dpy;
-   if (!surfaceless_probe_device(disp)) {
+   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
+  driver_loaded = surfaceless_probe_device(disp, false);
+  if (!driver_loaded)
+ _eglLog(_EGL_WARNING, "No hardware driver found, falling back to "
+"software rendering");
+   }
+
+   if (!driver_loaded && !surfaceless_probe_device(disp, true)) {
   err = "DRI2: failed to load driver";
   goto cleanup;
}
-- 
2.13.5

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[Mesa-dev] [PATCH 1/2] egl/surfaceless: add probe device helper function

[gurchetansi...@chromium.org]

From: Gurchetan Singh 

This will help us initialize a software driver, if it's needed
or requested.
---
 src/egl/drivers/dri2/platform_surfaceless.c | 67 +
 1 file changed, 39 insertions(+), 28 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index 3c00ff44ab..f6aa217d39 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -267,6 +267,44 @@ static const __DRIextension *image_loader_extensions[] = {
NULL,
 };
 
+static bool
+surfaceless_probe_device(_EGLDisplay *dpy)
+{
+   struct dri2_egl_display *dri2_dpy = dpy->DriverData;
+   const int limit = 64;
+   const int base = 128;
+   int fd;
+   int i;
+
+   for (i = 0; i < limit; ++i) {
+  char *card_path;
+  if (asprintf(_path, DRM_RENDER_DEV_NAME, DRM_DIR_NAME, base + i) < 
0)
+ continue;
+
+  fd = loader_open_device(card_path);
+  free(card_path);
+  if (fd < 0)
+ continue;
+
+  dri2_dpy->driver_name = loader_get_driver_for_fd(fd);
+  if (!dri2_dpy->driver_name) {
+ close(fd);
+ continue;
+  }
+
+  dri2_dpy->fd = fd;
+  if (dri2_load_driver_dri3(dpy))
+ return true;
+
+  close(fd);
+  dri2_dpy->fd = -1;
+  free(dri2_dpy->driver_name);
+  dri2_dpy->driver_name = NULL;
+   }
+
+   return false;
+}
+
 EGLBoolean
 dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay *disp)
 {
@@ -282,34 +320,7 @@ dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay 
*disp)
 
dri2_dpy->fd = -1;
disp->DriverData = (void *) dri2_dpy;
-
-   const int limit = 64;
-   const int base = 128;
-   for (int i = 0; i < limit; ++i) {
-  char *card_path;
-  if (asprintf(_path, DRM_RENDER_DEV_NAME, DRM_DIR_NAME, base + i) < 
0)
- continue;
-
-  dri2_dpy->fd = loader_open_device(card_path);
-
-  free(card_path);
-  if (dri2_dpy->fd < 0)
- continue;
-
-  dri2_dpy->driver_name = loader_get_driver_for_fd(dri2_dpy->fd);
-  if (dri2_dpy->driver_name) {
- if (dri2_load_driver_dri3(disp)) {
-driver_loaded = 1;
-break;
- }
- free(dri2_dpy->driver_name);
- dri2_dpy->driver_name = NULL;
-  }
-  close(dri2_dpy->fd);
-  dri2_dpy->fd = -1;
-   }
-
-   if (!driver_loaded) {
+   if (!surfaceless_probe_device(disp)) {
   err = "DRI2: failed to load driver";
   goto cleanup;
}
-- 
2.13.5

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Re: [Mesa-dev] [PATCH v2 2/2] etnaviv: Set up unknown GC3000 states

[Christian Gmeiner]

2017-10-01 16:23 GMT+02:00 Wladimir J. van der Laan :
> Set up new states that the blob started setting for GC3000 consistently.
>
> This makes sure that when another test or driver leaves the GPU in
> unpredictable state, these states are set up correctly for our
> rendering.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_context.c | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
> b/src/gallium/drivers/etnaviv/etnaviv_context.c
> index 45fc465..67aab6a 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
> @@ -317,8 +317,19 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream 
> *stream, void *priv)
> etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x0001);
> etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x0031);
> etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x3401);
> +   etna_set_state(stream, VIVS_PA_FLAGS, 0x); /* blob sets 
> ZCONVERT_BYPASS on GC3000, this messes up z for us */
> +   etna_set_state(stream, VIVS_RA_UNK00E0C, 0x);
> etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404);
> etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0));
> +   etna_set_state(stream, VIVS_PA_ZFARCLIPPING, 0x);
> +   etna_set_state(stream, VIVS_PE_ALPHA_COLOR_EXT0, 0x);
> +   etna_set_state(stream, VIVS_PE_ALPHA_COLOR_EXT1, 0x);
> +   etna_set_state(stream, VIVS_RA_HDEPTH_CONTROL, 0x7000);
> +   etna_set_state(stream, VIVS_PE_STENCIL_CONFIG_EXT2, 0x);
> +   etna_set_state(stream, VIVS_GL_UNK03834, 0x);
> +   etna_set_state(stream, VIVS_GL_UNK03838, 0x);
> +   etna_set_state(stream, VIVS_GL_UNK03854, 0x);
> +   etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x);
>
> /* Enable SINGLE_BUFFER for resolve, if supported */
> etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, 
> COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE));
> --
> 2.7.4
>

greets
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Re: [Mesa-dev] [PATCH v2 1/2] etnaviv: Fix point sprite rendering on GC3000

[Christian Gmeiner]

2017-10-01 16:23 GMT+02:00 Wladimir J. van der Laan :
> Setting PA_VIEWPORT_UNK state correctly is necessary to make point sprite
> rendering on GC3000 work.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_context.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
> b/src/gallium/drivers/etnaviv/etnaviv_context.c
> index 2ca09ce..45fc465 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
> @@ -317,6 +317,8 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream 
> *stream, void *priv)
> etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x0001);
> etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x0031);
> etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x3401);
> +   etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404);
> +   etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0));
>
> /* Enable SINGLE_BUFFER for resolve, if supported */
> etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, 
> COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE));
> --
> 2.7.4
>

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--
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Re: [Mesa-dev] [PATCH 1/2] anv: Fix vkCmdFillBuffer()

[Józef Kucia]

On Mon, Oct 2, 2017 at 9:19 PM, Lionel Landwerlin
 wrote:
> I guess it makes things clearer.
> Does this fix something?

Yes, it fixes buffer fills. After the change buffers are filled with
uint32_t values instead of uint8_t or uint16_t values.

Before the change, when the fill value is 0xabcdef buffers are filled
with 0xcdefcdef or 0xefefefef.

>
>
> On 02/10/17 18:58, Józef Kucia wrote:
>>
>> The vkCmdFillBuffer() command fills a buffer with an uint32_t value.
>> ---
>>   src/intel/vulkan/anv_blorp.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
>> index 8d0c275248..a8ebdb384c 100644
>> --- a/src/intel/vulkan/anv_blorp.c
>> +++ b/src/intel/vulkan/anv_blorp.c
>> @@ -533,8 +533,8 @@ isl_format_for_size(unsigned size_B)
>>  switch (size_B) {
>>  case 1:  return ISL_FORMAT_R8_UINT;
>>  case 2:  return ISL_FORMAT_R8G8_UINT;
>> -   case 4:  return ISL_FORMAT_R8G8B8A8_UINT;
>> -   case 8:  return ISL_FORMAT_R16G16B16A16_UINT;
>> +   case 4:  return ISL_FORMAT_R32_UINT;
>> +   case 8:  return ISL_FORMAT_R32G32_UINT;
>>  case 16: return ISL_FORMAT_R32G32B32A32_UINT;
>>  default:
>> unreachable("Not a power-of-two format size");
>
>
>
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Re: [Mesa-dev] [PATCH 3/3] nv50, nvc0/ir: Display shared memory usage in pipe_debug_message

[Ilia Mirkin]

Looks like this will upset my parser which is the only consumer of this info:

https://cgit.freedesktop.org/mesa/shader-db/tree/nv-report.py

Should be doable to rewrite it to not care about order. Or stick your
new thing at the end. Either way.

On Mon, Oct 2, 2017 at 2:57 PM, Pierre Moreau  wrote:
> Signed-off-by: Pierre Moreau 
> ---
>  src/gallium/drivers/nouveau/nv50/nv50_program.c | 7 ---
>  src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 7 ---
>  2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
> b/src/gallium/drivers/nouveau/nv50/nv50_program.c
> index 6b472d7fdd..6e943a3d94 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
> @@ -431,9 +431,10 @@ nv50_program_translate(struct nv50_program *prog, 
> uint16_t chipset,
> 
> >pipe.stream_output);
>
> pipe_debug_message(debug, SHADER_INFO,
> -  "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
> -  prog->type, info->bin.tlsSpace, prog->max_gpr,
> -  info->bin.instructions, info->bin.codeSize);
> +  "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, 
> bytes: %d",
> +  prog->type, info->bin.tlsSpace, info->bin.smemSize,
> +  prog->max_gpr, info->bin.instructions,
> +  info->bin.codeSize);
>
>  out:
> FREE(info);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> index a6112f401e..c95a96c717 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> @@ -684,9 +684,10 @@ nvc0_program_translate(struct nvc0_program *prog, 
> uint16_t chipset,
>  >pipe.stream_output);
>
> pipe_debug_message(debug, SHADER_INFO,
> -  "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
> -  prog->type, info->bin.tlsSpace, prog->num_gprs,
> -  info->bin.instructions, info->bin.codeSize);
> +  "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, 
> bytes: %d",
> +  prog->type, info->bin.tlsSpace, info->bin.smemSize,
> +  prog->num_gprs, info->bin.instructions,
> +  info->bin.codeSize);
>
>  #ifdef DEBUG
> if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
> --
> 2.14.2
>
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Re: [Mesa-dev] [PATCH 1/2] anv: Fix vkCmdFillBuffer()

[Lionel Landwerlin]

I guess it makes things clearer.
Does this fix something?

On 02/10/17 18:58, Józef Kucia wrote:

The vkCmdFillBuffer() command fills a buffer with an uint32_t value.
---
  src/intel/vulkan/anv_blorp.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8d0c275248..a8ebdb384c 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -533,8 +533,8 @@ isl_format_for_size(unsigned size_B)
 switch (size_B) {
 case 1:  return ISL_FORMAT_R8_UINT;
 case 2:  return ISL_FORMAT_R8G8_UINT;
-   case 4:  return ISL_FORMAT_R8G8B8A8_UINT;
-   case 8:  return ISL_FORMAT_R16G16B16A16_UINT;
+   case 4:  return ISL_FORMAT_R32_UINT;
+   case 8:  return ISL_FORMAT_R32G32_UINT;
 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
 default:
unreachable("Not a power-of-two format size");



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Re: [Mesa-dev] [PATCH 2/2] anv: Remove unreachable cases from isl_format_for_size()

[Lionel Landwerlin]

Make sense, if you could just update the comment in the unreachable(), 
should be multiple of 4.

With that changed :

Reviewed-by: Lionel Landwerlin 

[Mesa-dev] [PATCH 3/3] nv50, nvc0/ir: Display shared memory usage in pipe_debug_message

[Pierre Moreau]

Signed-off-by: Pierre Moreau 
---
 src/gallium/drivers/nouveau/nv50/nv50_program.c | 7 ---
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 7 ---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 6b472d7fdd..6e943a3d94 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -431,9 +431,10 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
>pipe.stream_output);
 
pipe_debug_message(debug, SHADER_INFO,
-  "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
-  prog->type, info->bin.tlsSpace, prog->max_gpr,
-  info->bin.instructions, info->bin.codeSize);
+  "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, 
bytes: %d",
+  prog->type, info->bin.tlsSpace, info->bin.smemSize,
+  prog->max_gpr, info->bin.instructions,
+  info->bin.codeSize);
 
 out:
FREE(info);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index a6112f401e..c95a96c717 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -684,9 +684,10 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t 
chipset,
 >pipe.stream_output);
 
pipe_debug_message(debug, SHADER_INFO,
-  "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
-  prog->type, info->bin.tlsSpace, prog->num_gprs,
-  info->bin.instructions, info->bin.codeSize);
+  "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, 
bytes: %d",
+  prog->type, info->bin.tlsSpace, info->bin.smemSize,
+  prog->num_gprs, info->bin.instructions,
+  info->bin.codeSize);
 
 #ifdef DEBUG
if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
-- 
2.14.2

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[Mesa-dev] [PATCH 1/3] nv50/ir: Store shared memory per block in nv50_ir_prog_info

[Pierre Moreau]

Signed-off-by: Pierre Moreau 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 76f08b1c3d..ffd53c9cd3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -87,6 +87,7 @@ struct nv50_ir_prog_info
   int16_t maxGPR; /* may be -1 if none used */
   int16_t maxOutput;
   uint32_t tlsSpace;  /* required local memory per thread */
+  uint32_t smemSize;  /* required shared memory per block */
   uint32_t *code;
   uint32_t codeSize;
   uint32_t instructions;
-- 
2.14.2

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[Mesa-dev] [PATCH 2/3] nv50, nvc0/ir: Copy shared memory per block to the program info structure and back

[Pierre Moreau]

In OpenCL/CUDA kernels, shared memory usage can be defined within the
kernel code. Those usage will only be picked up while parsing the
SPIR-V, during the translation phase of the program.

Signed-off-by: Pierre Moreau 
---
 src/gallium/drivers/nouveau/nv50/nv50_program.c | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 92e73f8c12..6b472d7fdd 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -336,6 +336,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
info->bin.source = (void *)prog->pipe.tokens;
 
+   info->bin.smemSize = prog->cp.smem_size;
info->io.auxCBSlot = 15;
info->io.ucpBase = NV50_CB_AUX_UCP_OFFSET;
info->io.genUserClip = prog->vp.clpd_nr;
@@ -382,6 +383,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
prog->interps = info->bin.fixupData;
prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
prog->tls_space = info->bin.tlsSpace;
+   prog->cp.smem_size = info->bin.smemSize;
prog->mul_zero_wins = info->io.mul_zero_wins;
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index e43a8de9f5..a6112f401e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -579,6 +579,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t 
chipset,
info->optLevel = 3;
 #endif
 
+   info->bin.smemSize = prog->cp.smem_size;
info->io.genUserClip = prog->vp.num_ucps;
info->io.auxCBSlot = 15;
info->io.msInfoCBSlot = 15;
@@ -618,6 +619,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t 
chipset,
prog->relocs = info->bin.relocData;
prog->fixups = info->bin.fixupData;
prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
+   prog->cp.smem_size = info->bin.smemSize;
prog->num_barriers = info->numBarriers;
 
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

[Roland Scheidegger]

Am 02.10.2017 um 19:36 schrieb Emil Velikov:
> On 2 October 2017 at 18:15, Matt Turner  wrote:
>> On Mon, Oct 2, 2017 at 6:17 AM, Emil Velikov  
>> wrote:
>>> On 2 October 2017 at 07:59, Matt Turner  wrote:
>>>
 +#include "../../../mesa/main/texcompress_s3tc_tmp.h"

>>> This feels a bit dirty. If people are not too keen on the idea,
>>> another approach is to have the code in src/util/
>>
>> This is how the ETC code is handled as well:
>>
>> src/gallium/auxiliary/util/u_format_etc.c:#include
>> "../../../mesa/main/texcompress_etc_tmp.h"
> 
> Hmm did not see that one - never mind me then.
>

I can't comment on the patch, but including things like that is indeed
dirty. But since there's precedence...

Roland

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Re: [Mesa-dev] [PATCH v2 1/2] egl/wayland: Check queryImage return for wl_buffer

[Daniel Stone]

On 2 October 2017 at 18:34, Daniel Stone  wrote:
> Marek, Michel, any ideas? Looks like the winsys buffers we create lose
> all their tiling information between client and KMS. You can test it
> just by running 'weston-simple-egl -f', with whatever version of
> Weston, and the two patches in this thread.

Perhaps unsurprisingly, adding __DRI_IMAGE_USE_SCANOUT to
src/egl/drivers/dri2/platform_wayland.c in the createImage() fallback
path (i.e. not createImageWithModifiers) fixes things. That being
said, Weston does do the GBM BO import with the scanout flag, which
will call the DRIImage's validateUsage() hook with the SCANOUT bit
set; for now, it should be enough to just detect that the image is not
scanout-compatible in radeonsi's validateUsage() hook, rejecting the
import which will make Weston fall back to GLES composition.

That being said, st/dri's dri2_validate_usage() doesn't really fill me
with too much confidence.

Cheers,
Daniel
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[Mesa-dev] [PATCH 2/2] anv: Remove unreachable cases from isl_format_for_size()

[Józef Kucia]

The dstOffset and fillSize parameters must be multiple of 4.
---
 src/intel/vulkan/anv_blorp.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index a8ebdb384c..8dead1d87a 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -531,8 +531,6 @@ static enum isl_format
 isl_format_for_size(unsigned size_B)
 {
switch (size_B) {
-   case 1:  return ISL_FORMAT_R8_UINT;
-   case 2:  return ISL_FORMAT_R8G8_UINT;
case 4:  return ISL_FORMAT_R32_UINT;
case 8:  return ISL_FORMAT_R32G32_UINT;
case 16: return ISL_FORMAT_R32G32B32A32_UINT;
-- 
2.13.6

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[Mesa-dev] [PATCH 1/2] anv: Fix vkCmdFillBuffer()

[Józef Kucia]

The vkCmdFillBuffer() command fills a buffer with an uint32_t value.
---
 src/intel/vulkan/anv_blorp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8d0c275248..a8ebdb384c 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -533,8 +533,8 @@ isl_format_for_size(unsigned size_B)
switch (size_B) {
case 1:  return ISL_FORMAT_R8_UINT;
case 2:  return ISL_FORMAT_R8G8_UINT;
-   case 4:  return ISL_FORMAT_R8G8B8A8_UINT;
-   case 8:  return ISL_FORMAT_R16G16B16A16_UINT;
+   case 4:  return ISL_FORMAT_R32_UINT;
+   case 8:  return ISL_FORMAT_R32G32_UINT;
case 16: return ISL_FORMAT_R32G32B32A32_UINT;
default:
   unreachable("Not a power-of-two format size");
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 10/12] intel/blorp: Handle clearing compressed surfaces

[Jason Ekstrand]

On Mon, Oct 2, 2017 at 10:49 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 29/09/17 04:23, Matt Turner wrote:
>
>> On Fri, Sep 15, 2017 at 9:01 AM, Jason Ekstrand 
>> wrote:
>>
>>> ---
>>>   src/intel/blorp/blorp_clear.c | 24 +---
>>>   1 file changed, 17 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/src/intel/blorp/blorp_clear.c
>>> b/src/intel/blorp/blorp_clear.c
>>> index 0feebef..e8b1e32 100644
>>> --- a/src/intel/blorp/blorp_clear.c
>>> +++ b/src/intel/blorp/blorp_clear.c
>>> @@ -442,14 +442,24 @@ blorp_clear(struct blorp_batch *batch,
>>> if (batch->blorp->isl_dev->info->gen == 4 &&
>>> (params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) {
>>>blorp_surf_convert_to_single_slice(batch->blorp->isl_dev,
>>> );
>>> +  }
>>> +
>>> +  if (isl_format_is_compressed(params.dst.surf.format)) {
>>> + blorp_surf_convert_to_uncompressed(batch->blorp->isl_dev,
>>> ,
>>> +NULL, NULL, NULL, NULL);
>>> +//_x, _y, _w,
>>> _h);
>>>
>> Did you mean to leave this as is?
>>
>> The previous patch (commit f395d0abc) caused a Coverity warning
>> because you began checking if x and y are non-NULL in one place after
>> dereferencing them under different conditions earlier. This code being
>> commented out makes me wonder what was really intended.
>>
>>
> That commented line should be removed but all parameters to NULL is the
> intended behavior.
>

That's correct.  More to Matt's point, yes, we dereference them under
different conditions.  The implicit assumption (which is currently always
valid) is that if you specify width and height then you also specified X
and Y.  Prior to this patch, every caller specified x and y but only some
of them specified width/height.  As of this patch, there is now a caller
which does not specify x and y (and also leaves width/height NULL).  I
don't think there's any point in (nor would it be possible to) supporting
width/height without x/y.  I'd be happy if someone added some asserts to
that effect.

--Jason
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Re: [Mesa-dev] [PATCH 10/12] intel/blorp: Handle clearing compressed surfaces

[Lionel Landwerlin]

On 29/09/17 04:23, Matt Turner wrote:

On Fri, Sep 15, 2017 at 9:01 AM, Jason Ekstrand  wrote:

---
  src/intel/blorp/blorp_clear.c | 24 +---
  1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 0feebef..e8b1e32 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -442,14 +442,24 @@ blorp_clear(struct blorp_batch *batch,
if (batch->blorp->isl_dev->info->gen == 4 &&
(params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) {
   blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, 
);
+  }
+
+  if (isl_format_is_compressed(params.dst.surf.format)) {
+ blorp_surf_convert_to_uncompressed(batch->blorp->isl_dev, ,
+NULL, NULL, NULL, NULL);
+//_x, _y, _w, _h);

Did you mean to leave this as is?

The previous patch (commit f395d0abc) caused a Coverity warning
because you began checking if x and y are non-NULL in one place after
dereferencing them under different conditions earlier. This code being
commented out makes me wonder what was really intended.



That commented line should be removed but all parameters to NULL is the 
intended behavior.

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Re: [Mesa-dev] [PATCH 03/13] i965: Print subreg in units of type-size on ternary instructions

[Matt Turner]

On Fri, Sep 29, 2017 at 5:03 PM, Scott D Phillips
 wrote:
> Matt Turner  writes:
>
>> The instruction word contains SubRegNum[4:2] so it's in units of dwords
>> (hence the * 4 to get it in terms of bytes). Before this patch, the
>> subreg would have been wrong for DF arguments.
>
> Trying to grok the subregnum stuff here, in brw_eu_emit.c I see:
>
> static int
> get_3src_subreg_nr(struct brw_reg reg)
> {
>
>/* Normally, SubRegNum is in bytes (0..31).  However, 3-src
> * instructions use 32-bit units (components 0..7).  Since they
> * only support F/D/UD types, this doesn't lose any
> * flexibility, but uses fewer bits.
> */
>
>return reg.subnr / 4;
> }
>
> Does the code above need updated for DF registers too? Or is that
> already accounted for somehow?

Nope, it does not, but that's a good question nonetheless.

Align1 mode has SubRegNum[4:0], which means it can represent
subregister numbers from 0-31. Regular (1 and 2 source) align16
instructions only have SubRegNum[4], which means it can represent
subregister numbers of only 0 and 16.

3-source instructions, which until CNL are only available in align16
mode, use a different instruction format in order to fit the extra
source. In order to do that, they lose some flexibility available to
1-2 source instructions like the full range of datatypes. Only F, D,
UD, and DF datatypes are supported, so there's no need for subregister
bits for offsets lower than four bytes, but they do offer a bit for
replication (called RepCtrl) that picks a single value and replicates
it to all channels. For that you want more than just the SubRegNum[4]
offered by regular align16 instructions, so they made it
SubRegNum[4:2], which is capable of representing any four-byte aligned
subregister.

With doubles, you'd just never use bit 2.

The code in get_3src_subreg_nr() is just an easy hack chop off the low
two bits from reg.subnr in order to go to the SubRegNum[4:2] form.

> I'm probably just missing something. With an explanation Patches 1-3 are:
>
> Reviewed-by: Scott D Phillips 

Thanks!
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Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

[Emil Velikov]

On 2 October 2017 at 18:15, Matt Turner  wrote:
> On Mon, Oct 2, 2017 at 6:17 AM, Emil Velikov  wrote:
>> On 2 October 2017 at 07:59, Matt Turner  wrote:
>>
>>> +#include "../../../mesa/main/texcompress_s3tc_tmp.h"
>>>
>> This feels a bit dirty. If people are not too keen on the idea,
>> another approach is to have the code in src/util/
>
> This is how the ETC code is handled as well:
>
> src/gallium/auxiliary/util/u_format_etc.c:#include
> "../../../mesa/main/texcompress_etc_tmp.h"

Hmm did not see that one - never mind me then.

-Emil
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Re: [Mesa-dev] [PATCH v2 1/2] egl/wayland: Check queryImage return for wl_buffer

[Daniel Stone]

Hi Andy,

On 2 October 2017 at 17:51, Andy Furniss  wrote:
> These are still a regression for me over git revert a65db0ad1c
>
> weston-simple-egl works as does mpv opengl windowed.
>
> The issue is that kodi or fullscreen mpv is mostly junk, IIRC from an old
> bug this is to do with direct scan out and tiling.

This is a Radeon driver bug which looks to have been there for at
least quite a while now?

Weston (in its current upstream form) doesn't import dmabufs for
scanout. Without Marek's patch, everything ends up using the dmabuf
interface, which succeeds when it shouldn't, and then because Weston
won't import the dmabuf for scanout, it uses the GPU instead and this
works just fine. With Marek's patch, Weston fails to import the
buffer. With Marek's and my patch, we go back to what we did up until
a couple of months ago, using the old wl_drm interface. That can then
be used for direct scanout, and is.

Marek, Michel, any ideas? Looks like the winsys buffers we create lose
all their tiling information between client and KMS. You can test it
just by running 'weston-simple-egl -f', with whatever version of
Weston, and the two patches in this thread.

Cheers,
Daniel
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Re: [Mesa-dev] Add a travis job for meson vulkan

[Eric Anholt]

Dylan Baker  writes:

> This adds a job to travis to build the vulkan driver and run some driver 
> checks,
> and fix building on travis (which uses a particularly old Ubuntu).

This series is:

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 4/5] meson: convert gtest to an internal dependency

[Dylan Baker]

Quoting Dylan Baker (2017-10-02 09:45:05)
> Quoting Eric Engestrom (2017-10-02 08:33:14)
> > On Sunday, 2017-10-01 03:58:27 +, Dylan Baker wrote:
> > > In truth gtest is an external dependency that upstream expects you to
> > > "vendor" into your own tree. As such, it makes sense to treat it more
> > > like a dependency than an internal library, and collect it's
> > > requirements together in a dependency object.
> > > 
> > > Signed-off-by: Dylan Baker 
> > > ---
> > >  src/compiler/nir/meson.build | 4 ++--
> > >  src/gtest/meson.build| 6 ++
> > >  src/intel/compiler/meson.build   | 6 +++---
> > >  src/util/tests/string_buffer/meson.build | 4 ++--
> > >  4 files changed, 13 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> > > index c260dca5467..8a85d119530 100644
> > > --- a/src/compiler/nir/meson.build
> > > +++ b/src/compiler/nir/meson.build
> > > @@ -197,8 +197,8 @@ if with_tests
> > >  [files('tests/control_flow_tests.cpp'), nir_opcodes_h],
> > >  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> > >  include_directories : [inc_common],
> > > -dependencies : [dep_thread],
> > > -link_with : [libmesa_util, libnir, libgtest],
> > > +dependencies : [dep_thread, idep_gtest],
> > > +link_with : [libmesa_util, libnir],
> > >)
> > >  
> > >test('nir_control_flow', nir_control_flow_test)
> > > diff --git a/src/gtest/meson.build b/src/gtest/meson.build
> > > index b51504d400a..9832af93e25 100644
> > > --- a/src/gtest/meson.build
> > > +++ b/src/gtest/meson.build
> > > @@ -24,3 +24,9 @@ libgtest = static_library(
> > >include_directories : include_directories('include'),
> > >build_by_default : false,
> > >  )
> > > +
> > > +idep_gtest = declare_dependency(
> > > +  link_with : libgtest,
> > > +  include_directories : include_directories('include'),
> > > +  compile_args : ['-Wno-sign-compare'],
> > 
> > Does meson not support/provide -isystem? This might be something to ask for.
> 
> There's an open bug for it: https://github.com/mesonbuild/meson/issues/963
> 
> When I get some time I'll look at it and see if I can get something working.
> 

Actually, -isystem is implemented enough for our purposes, I'll use that instead
of setting the cflags.

Dylan

> > 
> > > +)
> > > diff --git a/src/intel/compiler/meson.build 
> > > b/src/intel/compiler/meson.build
> > > index e12fa22cf1b..41c2f6ef1db 100644
> > > --- a/src/intel/compiler/meson.build
> > > +++ b/src/intel/compiler/meson.build
> > > @@ -146,9 +146,9 @@ if with_tests
> > >[t, nir_opcodes_h, ir_expression_operation_h],
> > >'test_@0@.cpp'.format(t),
> > >include_directories : [inc_common, inc_intel],
> > > -  link_with : [libgtest, libintel_compiler, libintel_common, libnir,
> > > -   libmesa_util, libisl],
> > > -  dependencies : [dep_thread, dep_dl],
> > > +  link_with : [libintel_compiler, libintel_common, libnir, 
> > > libmesa_util,
> > > +   libisl],
> > > +  dependencies : [dep_thread, dep_dl, idep_gtest],
> > >  )
> > >  test(t, _exe)
> > >endforeach
> > > diff --git a/src/util/tests/string_buffer/meson.build 
> > > b/src/util/tests/string_buffer/meson.build
> > > index ea9b8a07dce..14dbebca7d8 100644
> > > --- a/src/util/tests/string_buffer/meson.build
> > > +++ b/src/util/tests/string_buffer/meson.build
> > > @@ -21,9 +21,9 @@
> > >  string_buffer_test = executable(
> > >'string_buffer_test',
> > >'string_buffer_test.cpp',
> > > -  dependencies : [dep_thread, dep_dl],
> > > +  dependencies : [dep_thread, dep_dl, idep_gtest],
> > >include_directories : inc_common,
> > > -  link_with : [libmesa_util, libgtest],
> > > +  link_with : [libmesa_util],
> > >  )
> > >  
> > >  test('string_buffer', string_buffer_test)
> > > -- 
> > > 2.14.1
> > > 
> 
> 
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Re: [Mesa-dev] [PATCH 01/11] radeonsi: use ac helpers for bitcasts

[Marek Olšák]

On Mon, Oct 2, 2017 at 4:02 PM, Marek Olšák  wrote:
> This reply of yours doesn't contain anything. (clipped message?)

Nevermind. I've read your reply from the mesa-dev archive.

Marek
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Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

[Matt Turner]

On Mon, Oct 2, 2017 at 6:17 AM, Emil Velikov  wrote:
> On 2 October 2017 at 07:59, Matt Turner  wrote:
>
>> +#include "../../../mesa/main/texcompress_s3tc_tmp.h"
>>
> This feels a bit dirty. If people are not too keen on the idea,
> another approach is to have the code in src/util/

This is how the ETC code is handled as well:

src/gallium/auxiliary/util/u_format_etc.c:#include
"../../../mesa/main/texcompress_etc_tmp.h"
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Re: [Mesa-dev] [PATCH 06/15] mesa: Call DXTn functions directly

[Matt Turner]

On Mon, Oct 2, 2017 at 4:23 AM, Nicolai Hähnle  wrote:
> On 02.10.2017 08:59, Matt Turner wrote:
>>
>> ---
>>   src/mesa/main/texcompress_s3tc.c | 117
>> +--
>>   1 file changed, 25 insertions(+), 92 deletions(-)
>>
>> diff --git a/src/mesa/main/texcompress_s3tc.c
>> b/src/mesa/main/texcompress_s3tc.c
>> index e08ed23d3a..e74e4c402a 100644
>> --- a/src/mesa/main/texcompress_s3tc.c
>> +++ b/src/mesa/main/texcompress_s3tc.c
>> @@ -43,78 +43,11 @@
>>   #include "util/format_srgb.h"
>> -#if defined(_WIN32) || defined(WIN32)
>> -#define DXTN_LIBNAME "dxtn.dll"
>> -#define RTLD_LAZY 0
>> -#define RTLD_GLOBAL 0
>> -#elif defined(__CYGWIN__)
>> -#define DXTN_LIBNAME "cygtxc_dxtn.dll"
>> -#else
>> -#define DXTN_LIBNAME "libtxc_dxtn.so"
>> -#endif
>> -
>> -typedef void (*dxtFetchTexelFuncExt)( GLint srcRowstride, const GLubyte
>> *pixdata, GLint col, GLint row, GLvoid *texelOut );
>> -
>> -static dxtFetchTexelFuncExt fetch_ext_rgb_dxt1 = NULL;
>> -static dxtFetchTexelFuncExt fetch_ext_rgba_dxt1 = NULL;
>> -static dxtFetchTexelFuncExt fetch_ext_rgba_dxt3 = NULL;
>> -static dxtFetchTexelFuncExt fetch_ext_rgba_dxt5 = NULL;
>> -
>> -typedef void (*dxtCompressTexFuncExt)(GLint srccomps, GLint width,
>> -  GLint height, const GLubyte
>> *srcPixData,
>> -  GLenum destformat, GLubyte *dest,
>> -  GLint dstRowStride);
>> -
>> -static dxtCompressTexFuncExt ext_tx_compress_dxtn = NULL;
>> -
>> -static void *dxtlibhandle = NULL;
>> -
>> -
>>   void
>>   _mesa_init_texture_s3tc( struct gl_context *ctx )
>>   {
>>  /* called during context initialization */
>> -   ctx->Mesa_DXTn = GL_FALSE;
>> -   if (!dxtlibhandle) {
>> -  dxtlibhandle = _mesa_dlopen(DXTN_LIBNAME, 0);
>> -  if (!dxtlibhandle) {
>> -_mesa_warning(ctx, "couldn't open " DXTN_LIBNAME ", software DXTn
>> "
>> -   "compression/decompression unavailable");
>> -  }
>> -  else {
>> - /* the fetch functions are not per context! Might be
>> problematic... */
>> - fetch_ext_rgb_dxt1 = (dxtFetchTexelFuncExt)
>> -_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgb_dxt1");
>> - fetch_ext_rgba_dxt1 = (dxtFetchTexelFuncExt)
>> -_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt1");
>> - fetch_ext_rgba_dxt3 = (dxtFetchTexelFuncExt)
>> -_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt3");
>> - fetch_ext_rgba_dxt5 = (dxtFetchTexelFuncExt)
>> -_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt5");
>> - ext_tx_compress_dxtn = (dxtCompressTexFuncExt)
>> -_mesa_dlsym(dxtlibhandle, "tx_compress_dxtn");
>> -
>> - if (!fetch_ext_rgb_dxt1 ||
>> - !fetch_ext_rgba_dxt1 ||
>> - !fetch_ext_rgba_dxt3 ||
>> - !fetch_ext_rgba_dxt5 ||
>> - !ext_tx_compress_dxtn) {
>> -   _mesa_warning(ctx, "couldn't reference all symbols in "
>> -  DXTN_LIBNAME ", software DXTn compression/decompression "
>> -  "unavailable");
>> -fetch_ext_rgb_dxt1 = NULL;
>> -fetch_ext_rgba_dxt1 = NULL;
>> -fetch_ext_rgba_dxt3 = NULL;
>> -fetch_ext_rgba_dxt5 = NULL;
>> -ext_tx_compress_dxtn = NULL;
>> -_mesa_dlclose(dxtlibhandle);
>> -dxtlibhandle = NULL;
>> - }
>> -  }
>> -   }
>> -   if (dxtlibhandle) {
>> -  ctx->Mesa_DXTn = GL_TRUE;
>> -   }
>> +   ctx->Mesa_DXTn = GL_TRUE;
>>   }
>> /**
>> @@ -159,8 +92,8 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS)
>>dst = dstSlices[0];
>>   -   if (ext_tx_compress_dxtn) {
>> -  (*ext_tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
>> +   if (tx_compress_dxtn) {
>> +  (*tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
>> GL_COMPRESSED_RGB_S3TC_DXT1_EXT,
>> dst, dstRowStride);
>>  }
>> @@ -217,8 +150,8 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS)
>>dst = dstSlices[0];
>>   -   if (ext_tx_compress_dxtn) {
>> -  (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
>> +   if (tx_compress_dxtn) {
>> +  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
>> GL_COMPRESSED_RGBA_S3TC_DXT1_EXT,
>> dst, dstRowStride);
>>  }
>> @@ -274,8 +207,8 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS)
>>dst = dstSlices[0];
>>   -   if (ext_tx_compress_dxtn) {
>> -  (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
>> +   if (tx_compress_dxtn) {
>> +  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
>
>
> Does the function pointer syntax compile when tx_compress_dxtn is not a
> function pointer? Just in case you haven't done it, please use git rebase -x
> to make sure each individual step in the series compiles.

It does, yes :)

[Mesa-dev] [PATCH] travis: add meson build for vulkan drivers.

[Dylan Baker]

v2: - use -isystem`pwd` instead of cp to include fake linux header (Eric, Emil)

Signed-off-by: Dylan Baker 
---
 .travis.yml | 36 
 1 file changed, 36 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index d9a8bf5a9d4..ca766917f25 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -27,6 +27,7 @@ env:
 - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
 - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
 - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
+- PATH="$HOME/prefix/bin:$PATH"
 
 matrix:
   include:
@@ -393,10 +394,34 @@ matrix:
 - libexpat1-dev
 - libx11-xcb-dev
 - libelf-dev
+- env:
+- LABEL="meson Vulkan"
+- BUILD=meson
+- MESON_OPTIONS="-Dbuild-tests=true"
+  addons:
+apt:
+  sources:
+- llvm-toolchain-trusty-3.9
+  packages:
+# LLVM packaging is broken and misses these dependencies
+- libedit-dev
+# From sources above
+- llvm-3.9-dev
+# Common
+- xz-utils
+- libexpat1-dev
+- libelf-dev
+- python3-pip
 
 install:
   - pip install --user mako
 
+  # Install the latest meson from pip, since the version in the ubuntu repos is
+  # often quite old.
+  - if test "x$BUILD" = xmeson; then
+  pip3 install --user meson;
+fi
+
   # Since libdrm gets updated in configure.ac regularly, try to pick up the
   # latest version from there.
   - for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
@@ -471,6 +496,11 @@ install:
   - tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
   - (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && 
make install)
 
+  # Meson requires ninja >= 1.6, but trusty has 1.3.x
+  - wget 
https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
+  - unzip ninja-linux.zip
+  - mv ninja $HOME/prefix/bin/
+
   # Generate the header since one is missing on the Travis instance
   - mkdir -p linux
   - printf "%s\n" \
@@ -510,3 +540,9 @@ script:
   test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
   scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
 fi
+
+  - if test "x$BUILD" = xmeson; then
+  export CC="$CC -isystem`pwd`";
+  meson _build $MESON_OPTIONS;
+  ninja -C _build test;
+fi
-- 
2.14.1

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Re: [Mesa-dev] [PATCH 05/15] mesa: Remove fprintf referring to libdxtn

[Matt Turner]

On Mon, Oct 2, 2017 at 4:20 AM, Nicolai Hähnle  wrote:
> On 02.10.2017 08:59, Matt Turner wrote:
>>
>> When this file is included by Gallium, the fprintf causes it to fail to
>> compile. This is an unreachable error case, and we shouldn't be calling
>> fprintf directly.
>> ---
>>   src/mesa/main/texcompress_s3tc_tmp.h | 1 -
>>   1 file changed, 1 deletion(-)
>>
>> diff --git a/src/mesa/main/texcompress_s3tc_tmp.h
>> b/src/mesa/main/texcompress_s3tc_tmp.h
>> index 3abce6e904..4fec4a6b4a 100644
>> --- a/src/mesa/main/texcompress_s3tc_tmp.h
>> +++ b/src/mesa/main/texcompress_s3tc_tmp.h
>> @@ -983,7 +983,6 @@ static void tx_compress_dxtn(GLint srccomps, GLint
>> width, GLint height, const GL
>> }
>> break;
>>  default:
>> -  fprintf(stderr, "libdxtn: Bad dstFormat %d in tx_compress_dxtn\n",
>> destFormat);
>
>
> Maybe replace by an assert(false);?

Sure. Thanks!
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[Mesa-dev] [Bug 101832] [PATCH][regression][bisect] Xorg fails to start after f50aa21456d82c8cb6fbaa565835f1acc1720a5d

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101832

Laurent carlier  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #15 from Laurent carlier  ---
Fixed with commit 21e271024d8e050b75361c2da2e5783100f2e87b

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[Mesa-dev] [Bug 102847] swr fail to build with llvm-5.0.0

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102847

Laurent carlier  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #5 from Laurent carlier  ---
(In reply to Juan A. Suarez from comment #4)
> Patch https://patchwork.freedesktop.org/patch/177834/ has been landed
> upstream.
> 
> Does it fix this issue?

yes, it's fixed

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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Eric Engestrom]

On Monday, 2017-10-02 14:16:02 +, Trevor (CIMdata) wrote:
> Hello Emil,
> Yes, I did see the AppVeyor integraton for MSVC. It could be quite
> easy to add the MinGW scope to the metrix.
> 
> I don’t really know how to ‘upsteam’ the patches I use mostly because
> I am not the author. Do I just submit a PR? Anyway to help George with
> his patch – which fixes the MinGW build – I have done the CI script,
> AppVeyor.yml and set up AV repo. My source if free and w/o license.

Just FYI, it's a common misconception that "no license" means "license
to do anything", but what it really means is "whatever the default is in
the legislation of the country/state the author happens to have been in
when they wrote this", which is usually close to impossible to know for
everyone else.

If your point is to distribute your code freely, consider the MIT
license, or look at https://choosealicense.com


> Please feel free to use it if you wish. Many thanks!
> 
> Cheers,
> 
> Trevor SANDY
> +33 682 100 571
> 
> From: Emil Velikov
> Sent: 02 October 2017 16:04
> To: Trevor Sandy
> Cc: Kyriazis, George; mesa-dev@lists.freedesktop.org
> Subject: Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository
> 
> Hi Trevor,
> 
> On 2 October 2017 at 13:48, Trevor Sandy  wrote:
> > Hi George,
> >
> > You might be interested to know I have set up a CI env on AppVeyor for MinGW
> > builds.
> >
> > Here is the GitHub repo: https://github.com/trevorsandy/osmesa_mingw_av.
> > Follow the badge in the README to the AppVeyor instance.
> >
> > You can demo your patches quite easily - see the README.md on how to extract
> > source that can be used by my build script. Or change set the version to
> > download and build its source bundle. Perhaps later on I'll add the ability
> > to get build content (tag, branch, commit etc...) directly from Mesa's git
> > repo.
> >
> The upstream Mesa repository has AppVeyor integration, admittedly it
> builds only with MSVC.
> 
> If you want for things to work, I strongly recommend upstreaming your patches.
> Otherwise it will be in a perpetual state of brokenness and you'll
> have to dedicate even more resources as time goes by.
> 
> Thanks
> Emil
> 
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Re: [Mesa-dev] [PATCH v2 2/3] vulkan/wsi: Report the correct min/maxImageCount

[Neil Roberts]

Jason Ekstrand  writes:

> I wish...  Unfortunately, the spec says:
>
> Let *n* be the total number of images in the swapchain, *m* be the
> value of VkSurfaceCapabilitiesKHR::minImageCount, and *a* be the
> number of presentable images that the application has currently
> acquired (i.e. images acquired with vkAcquireNextImageKHR, but not yet
> presented with vkQueuePresentKHR). vkAcquireNextImageKHR *can* always
> succeed if a ≤ n - m at the time vkAcquireNextImageKHR is called.
> vkAcquireNextImageKHR *should* not be called if a > n - m with a
> timeout of UINT64_MAX; in such a case, vkAcquireNextImageKHR *may*
> block indefinitely.
>
> Because this is based on the number of images in the swapchain and the
> VkSurfaceCapabilitiesKHR field, if we return a swapchain with more
> images, n will be larger but not m so that just means that they can
> acquire more images, not that we've reserved more. Arguably, that's a
> spec bug and I'll file one and see where it goes. However, it's
> definitely what the spec says today. :-(

Fair enough. Thanks for the explanation.

Regards,
- Neil

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Re: [Mesa-dev] [PATCH 3/3] st/va: add RGB support to vlVaPutSurface

[Andy Furniss]

Tested-by: Andy Furniss 

Leo Liu wrote:

---
  src/gallium/state_trackers/va/surface.c | 14 +-
  1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/va/surface.c 
b/src/gallium/state_trackers/va/surface.c
index 643cdcd54a..4c2f4b5452 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -280,6 +280,7 @@ vlVaPutSurface(VADriverContextP ctx, VASurfaceID 
surface_id, void* draw, short s
 struct vl_screen *vscreen;
 struct u_rect src_rect, *dirty_area;
 struct u_rect dst_rect = {destx, destx + destw, desty, desty + desth};
+   enum pipe_format format;
 VAStatus status;
  
 if (!ctx)

@@ -318,8 +319,19 @@ vlVaPutSurface(VADriverContextP ctx, VASurfaceID 
surface_id, void* draw, short s
 src_rect.x1 = srcw + srcx;
 src_rect.y1 = srch + srcy;
  
+   format = surf->buffer->buffer_format;

+
 vl_compositor_clear_layers(>cstate);
-   vl_compositor_set_buffer_layer(>cstate, >compositor, 0, surf->buffer, 
_rect, NULL, VL_COMPOSITOR_WEAVE);
+
+   if (format == PIPE_FORMAT_B8G8R8A8_UNORM || format == 
PIPE_FORMAT_B8G8R8X8_UNORM ||
+   format == PIPE_FORMAT_R8G8B8A8_UNORM || format == 
PIPE_FORMAT_R8G8B8X8_UNORM) {
+  struct pipe_sampler_view **views;
+
+  views = surf->buffer->get_sampler_view_planes(surf->buffer);
+  vl_compositor_set_rgba_layer(>cstate, >compositor, 0, views[0], 
_rect, NULL, NULL);
+   } else
+  vl_compositor_set_buffer_layer(>cstate, >compositor, 0, 
surf->buffer, _rect, NULL, VL_COMPOSITOR_WEAVE);
+
 vl_compositor_set_layer_dst_area(>cstate, 0, _rect);
 vl_compositor_render(>cstate, >compositor, surf_draw, 
dirty_area, true);
  



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Re: [Mesa-dev] [PATCH v2 1/2] egl/wayland: Check queryImage return for wl_buffer

[Andy Furniss]

These are still a regression for me over git revert a65db0ad1c

weston-simple-egl works as does mpv opengl windowed.

The issue is that kodi or fullscreen mpv is mostly junk, IIRC from an 
old bug this is to do with direct scan out and tiling.


Daniel Stone wrote:

When creating a wl_buffer from a DRIImage, we extract all the DRIImage
information via queryImage. Check whether or not it actually succeeds,
either bailing out if the query was critical, or providing sensible
fallbacks for information which was not available in older DRIImage
versions.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't 
implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Reported-by: Andy Furniss 
Cc: Marek Olšák 
Signed-off-by: Daniel Stone 
---
  src/egl/drivers/dri2/platform_wayland.c | 56 -
  1 file changed, 41 insertions(+), 15 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 011dddfabf..04c04cc304 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -678,23 +678,37 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
   __DRIimage *image)
  {
 struct wl_buffer *ret;
+   EGLBoolean query;
 int width, height, fourcc, num_planes;
  
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, );

-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
-   _planes);
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, 
);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT,
+);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC,
+);
+   if (!query)
+  return NULL;
+
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
+   _planes);
+   if (!query)
+  num_planes = 1;
  
 if (dri2_dpy->wl_dmabuf && dri2_dpy->image->base.version >= 15) {

struct zwp_linux_buffer_params_v1 *params;
int mod_hi, mod_lo;
int i;
  
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,

-  _hi);
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
-  _lo);
+  query = dri2_dpy->image->queryImage(image,
+  __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
+  _hi);
+  query &= dri2_dpy->image->queryImage(image,
+   __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
+   _lo);
+  if (!query) {
+ mod_hi = DRM_FORMAT_MOD_INVALID >> 32;
+ mod_lo = DRM_FORMAT_MOD_INVALID & 0x;
+  }
  
/* We don't need a wrapper for wl_dmabuf objects, because we have to

 * create the intermediate params object; we can set the queue on this,
@@ -705,7 +719,8 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  
for (i = 0; i < num_planes; i++) {

   __DRIimage *p_image;
- int stride, offset, fd;
+ int stride, offset;
+ int fd = -1;
  
   if (i == 0)

  p_image = image;
@@ -716,14 +731,25 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  return NULL;
   }
  
- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_FD, );

- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_STRIDE,
- );
- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_OFFSET,
- );
+ query = dri2_dpy->image->queryImage(p_image,
+ __DRI_IMAGE_ATTRIB_FD,
+ );
+ query &= dri2_dpy->image->queryImage(p_image,
+  __DRI_IMAGE_ATTRIB_STRIDE,
+  );
+ query &= dri2_dpy->image->queryImage(p_image,
+  __DRI_IMAGE_ATTRIB_OFFSET,
+  );
   if (image != p_image)
  dri2_dpy->image->destroyImage(p_image);
  
+ if (!query) {

+if (fd >= 0)
+   close(fd);
+zwp_linux_buffer_params_v1_destroy(params);
+return NULL;
+ }
+
   zwp_linux_buffer_params_v1_add(params, fd, i, offset, stride,
  mod_hi, mod_lo);
 

Re: [Mesa-dev] [PATCH 5/5] travis: add meson build for vulkan drivers.

[Dylan Baker]

Quoting Emil Velikov (2017-10-02 09:13:49)
> On 2 October 2017 at 16:51, Eric Engestrom  wrote:
> > On Sunday, 2017-10-01 03:58:28 +, Dylan Baker wrote:
> >> Signed-off-by: Dylan Baker 
> >> ---
> >>  .travis.yml | 36 
> >>  1 file changed, 36 insertions(+)
> >>
> >> diff --git a/.travis.yml b/.travis.yml
> >> index d9a8bf5a9d4..e8fff1b66ab 100644
> >> --- a/.travis.yml
> >> +++ b/.travis.yml
> >> @@ -27,6 +27,7 @@ env:
> >>  - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
> >>  - 
> >> PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
> >>  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
> >> +- PATH="$HOME/prefix/bin:$PATH"
> >>
> >>  matrix:
> >>include:
> >> @@ -393,10 +394,34 @@ matrix:
> >>  - libexpat1-dev
> >>  - libx11-xcb-dev
> >>  - libelf-dev
> >> +- env:
> >> +- LABEL="meson Vulkan"
> >> +- BUILD=meson
> >> +- MESON_OPTIONS="-Dbuild-tests=true"
> >> +  addons:
> >> +apt:
> >> +  sources:
> >> +- llvm-toolchain-trusty-3.9
> >> +  packages:
> >> +# LLVM packaging is broken and misses these dependencies
> >> +- libedit-dev
> >> +# From sources above
> >> +- llvm-3.9-dev
> >> +# Common
> >> +- xz-utils
> >> +- libexpat1-dev
> >> +- libelf-dev
> >> +- python3-pip
> >>
> >>  install:
> >>- pip install --user mako
> >>
> >> +  # Install the latest meson from pip, since the version in the ubuntu 
> >> repos is
> >> +  # often quite old.
> >> +  - if test "x$BUILD" = xmeson; then
> >> +  pip3 install --user meson;
> >> +fi
> >> +
> >># Since libdrm gets updated in configure.ac regularly, try to pick up 
> >> the
> >># latest version from there.
> >>- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
> >> @@ -471,6 +496,11 @@ install:
> >>- tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
> >>- (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix 
> >> && make install)
> >>
> >> +  # Meson requires ninja >= 1.6, but trusty has 1.3.x
> >> +  - wget 
> >> https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
> >> +  - unzip ninja-linux.zip
> >> +  - mv ninja $HOME/prefix/bin/
> >> +
> >># Generate the header since one is missing on the Travis instance
> >>- mkdir -p linux
> >>- printf "%s\n" \
> >> @@ -510,3 +540,9 @@ script:
> >>test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
> >>scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
> >>  fi
> >> +
> >> +  - if test "x$BUILD" = xmeson; then
> >> +  cp -r linux src/intel/vulkan/;
> >
> > Is this needed? This just looks weird because it's not needed for
> > the other build systems.
> >
> It's the equivalent of "export CC="$CC -isystem`pwd`"
> 
> Handling should be identical, regardless of the build system - be that
> cp or export.
> 
> -Emil

Oh, duh, I just missed that when I was reading the make path. That's a much
nicer way to handle it than with cp, I'll use the -isystem instead.

Dylan


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Re: [Mesa-dev] [PATCH] radv: make radv_dynamic_state_copy() static

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On 2 Oct 2017 12:26, "Samuel Pitoiset"  wrote:

> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 2 +-
>  src/amd/vulkan/radv_private.h| 4 
>  2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_
> buffer.c
> index 19b3b24a4b..61ea11c12a 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -78,7 +78,7 @@ const struct radv_dynamic_state default_dynamic_state = {
> },
>  };
>
> -void
> +static void
>  radv_dynamic_state_copy(struct radv_dynamic_state *dest,
> const struct radv_dynamic_state *src,
> uint32_t copy_mask)
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 825a9710f7..5cab407211 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -745,10 +745,6 @@ struct radv_dynamic_state {
>
>  extern const struct radv_dynamic_state default_dynamic_state;
>
> -void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
> -const struct radv_dynamic_state *src,
> -uint32_t copy_mask);
> -
>  const char *
>  radv_get_debug_option_name(int id);
>
> --
> 2.14.2
>
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Re: [Mesa-dev] [PATCH 4/5] meson: convert gtest to an internal dependency

[Dylan Baker]

Quoting Eric Engestrom (2017-10-02 08:33:14)
> On Sunday, 2017-10-01 03:58:27 +, Dylan Baker wrote:
> > In truth gtest is an external dependency that upstream expects you to
> > "vendor" into your own tree. As such, it makes sense to treat it more
> > like a dependency than an internal library, and collect it's
> > requirements together in a dependency object.
> > 
> > Signed-off-by: Dylan Baker 
> > ---
> >  src/compiler/nir/meson.build | 4 ++--
> >  src/gtest/meson.build| 6 ++
> >  src/intel/compiler/meson.build   | 6 +++---
> >  src/util/tests/string_buffer/meson.build | 4 ++--
> >  4 files changed, 13 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> > index c260dca5467..8a85d119530 100644
> > --- a/src/compiler/nir/meson.build
> > +++ b/src/compiler/nir/meson.build
> > @@ -197,8 +197,8 @@ if with_tests
> >  [files('tests/control_flow_tests.cpp'), nir_opcodes_h],
> >  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> >  include_directories : [inc_common],
> > -dependencies : [dep_thread],
> > -link_with : [libmesa_util, libnir, libgtest],
> > +dependencies : [dep_thread, idep_gtest],
> > +link_with : [libmesa_util, libnir],
> >)
> >  
> >test('nir_control_flow', nir_control_flow_test)
> > diff --git a/src/gtest/meson.build b/src/gtest/meson.build
> > index b51504d400a..9832af93e25 100644
> > --- a/src/gtest/meson.build
> > +++ b/src/gtest/meson.build
> > @@ -24,3 +24,9 @@ libgtest = static_library(
> >include_directories : include_directories('include'),
> >build_by_default : false,
> >  )
> > +
> > +idep_gtest = declare_dependency(
> > +  link_with : libgtest,
> > +  include_directories : include_directories('include'),
> > +  compile_args : ['-Wno-sign-compare'],
> 
> Does meson not support/provide -isystem? This might be something to ask for.

There's an open bug for it: https://github.com/mesonbuild/meson/issues/963

When I get some time I'll look at it and see if I can get something working.

> 
> > +)
> > diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
> > index e12fa22cf1b..41c2f6ef1db 100644
> > --- a/src/intel/compiler/meson.build
> > +++ b/src/intel/compiler/meson.build
> > @@ -146,9 +146,9 @@ if with_tests
> >[t, nir_opcodes_h, ir_expression_operation_h],
> >'test_@0@.cpp'.format(t),
> >include_directories : [inc_common, inc_intel],
> > -  link_with : [libgtest, libintel_compiler, libintel_common, libnir,
> > -   libmesa_util, libisl],
> > -  dependencies : [dep_thread, dep_dl],
> > +  link_with : [libintel_compiler, libintel_common, libnir, 
> > libmesa_util,
> > +   libisl],
> > +  dependencies : [dep_thread, dep_dl, idep_gtest],
> >  )
> >  test(t, _exe)
> >endforeach
> > diff --git a/src/util/tests/string_buffer/meson.build 
> > b/src/util/tests/string_buffer/meson.build
> > index ea9b8a07dce..14dbebca7d8 100644
> > --- a/src/util/tests/string_buffer/meson.build
> > +++ b/src/util/tests/string_buffer/meson.build
> > @@ -21,9 +21,9 @@
> >  string_buffer_test = executable(
> >'string_buffer_test',
> >'string_buffer_test.cpp',
> > -  dependencies : [dep_thread, dep_dl],
> > +  dependencies : [dep_thread, dep_dl, idep_gtest],
> >include_directories : inc_common,
> > -  link_with : [libmesa_util, libgtest],
> > +  link_with : [libmesa_util],
> >  )
> >  
> >  test('string_buffer', string_buffer_test)
> > -- 
> > 2.14.1
> > 


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Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

[Nicolai Hähnle]

On 02.10.2017 15:17, Emil Velikov wrote:

On 2 October 2017 at 07:59, Matt Turner  wrote:


+#include "../../../mesa/main/texcompress_s3tc_tmp.h"


This feels a bit dirty. If people are not too keen on the idea,
another approach is to have the code in src/util/


I like that idea.

Cheers,
Nicolai




-Emil
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Aber vergiss niemals, wie sie sein sollte.
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[Mesa-dev] [PATCH v2 2/2] egl/wayland: Don't use dmabuf with no modifiers

[Daniel Stone]

The dmabuf interface requires a valid modifier to be sent. If we don't
explicitly get a modifier from the driver, we can't know what to send;
it must be inferred from legacy side-channels (or assumed to linear, if
none exists).

If we have no modifier, then we can only have a single-plane format
anyway, so fall back to the old wl_drm buffer import path.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't 
implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Reported-by: Andy Furniss 
Cc: Marek Olšák 
---
 src/egl/drivers/dri2/platform_wayland.c | 18 +++---
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 04c04cc304..14db55ca74 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -680,6 +680,7 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
struct wl_buffer *ret;
EGLBoolean query;
int width, height, fourcc, num_planes;
+   uint64_t modifier = DRM_FORMAT_MOD_INVALID;
 
query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, 
);
query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT,
@@ -694,10 +695,8 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
if (!query)
   num_planes = 1;
 
-   if (dri2_dpy->wl_dmabuf && dri2_dpy->image->base.version >= 15) {
-  struct zwp_linux_buffer_params_v1 *params;
+   if (dri2_dpy->image->base.version >= 15) {
   int mod_hi, mod_lo;
-  int i;
 
   query = dri2_dpy->image->queryImage(image,
   __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
@@ -705,10 +704,15 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
   query &= dri2_dpy->image->queryImage(image,
__DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
_lo);
-  if (!query) {
- mod_hi = DRM_FORMAT_MOD_INVALID >> 32;
- mod_lo = DRM_FORMAT_MOD_INVALID & 0x;
+  if (query) {
+ modifier = (uint64_t) mod_hi << 32;
+ modifier |= (uint64_t) (mod_lo & 0x);
   }
+   }
+
+   if (dri2_dpy->wl_dmabuf && modifier != DRM_FORMAT_MOD_INVALID) {
+  struct zwp_linux_buffer_params_v1 *params;
+  int i;
 
   /* We don't need a wrapper for wl_dmabuf objects, because we have to
* create the intermediate params object; we can set the queue on this,
@@ -751,7 +755,7 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  }
 
  zwp_linux_buffer_params_v1_add(params, fd, i, offset, stride,
-mod_hi, mod_lo);
+modifier >> 32, modifier & 0x);
  close(fd);
   }
 
-- 
2.14.2

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[Mesa-dev] [PATCH v2 1/2] egl/wayland: Check queryImage return for wl_buffer

[Daniel Stone]

When creating a wl_buffer from a DRIImage, we extract all the DRIImage
information via queryImage. Check whether or not it actually succeeds,
either bailing out if the query was critical, or providing sensible
fallbacks for information which was not available in older DRIImage
versions.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't 
implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Reported-by: Andy Furniss 
Cc: Marek Olšák 
Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 56 -
 1 file changed, 41 insertions(+), 15 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 011dddfabf..04c04cc304 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -678,23 +678,37 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  __DRIimage *image)
 {
struct wl_buffer *ret;
+   EGLBoolean query;
int width, height, fourcc, num_planes;
 
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
-   _planes);
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, 
);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT,
+);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC,
+);
+   if (!query)
+  return NULL;
+
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
+   _planes);
+   if (!query)
+  num_planes = 1;
 
if (dri2_dpy->wl_dmabuf && dri2_dpy->image->base.version >= 15) {
   struct zwp_linux_buffer_params_v1 *params;
   int mod_hi, mod_lo;
   int i;
 
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
-  _hi);
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
-  _lo);
+  query = dri2_dpy->image->queryImage(image,
+  __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
+  _hi);
+  query &= dri2_dpy->image->queryImage(image,
+   __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
+   _lo);
+  if (!query) {
+ mod_hi = DRM_FORMAT_MOD_INVALID >> 32;
+ mod_lo = DRM_FORMAT_MOD_INVALID & 0x;
+  }
 
   /* We don't need a wrapper for wl_dmabuf objects, because we have to
* create the intermediate params object; we can set the queue on this,
@@ -705,7 +719,8 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
 
   for (i = 0; i < num_planes; i++) {
  __DRIimage *p_image;
- int stride, offset, fd;
+ int stride, offset;
+ int fd = -1;
 
  if (i == 0)
 p_image = image;
@@ -716,14 +731,25 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
 return NULL;
  }
 
- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_FD, );
- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_STRIDE,
- );
- dri2_dpy->image->queryImage(p_image, __DRI_IMAGE_ATTRIB_OFFSET,
- );
+ query = dri2_dpy->image->queryImage(p_image,
+ __DRI_IMAGE_ATTRIB_FD,
+ );
+ query &= dri2_dpy->image->queryImage(p_image,
+  __DRI_IMAGE_ATTRIB_STRIDE,
+  );
+ query &= dri2_dpy->image->queryImage(p_image,
+  __DRI_IMAGE_ATTRIB_OFFSET,
+  );
  if (image != p_image)
 dri2_dpy->image->destroyImage(p_image);
 
+ if (!query) {
+if (fd >= 0)
+   close(fd);
+zwp_linux_buffer_params_v1_destroy(params);
+return NULL;
+ }
+
  zwp_linux_buffer_params_v1_add(params, fd, i, offset, stride,
 mod_hi, mod_lo);
  close(fd);
-- 
2.14.2

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Re: [Mesa-dev] [PATCH v2] meson: change vulkan icd config to - instead of _

[Dylan Baker]

Quoting Eric Engestrom (2017-10-02 02:49:51)
> On Saturday, 2017-09-30 01:00:56 +, Dylan Baker wrote:
> > Just to be consistent.
> > 
> > v2: - update meson.build too
> > 
> > Signed-off-by: Dylan Baker 
> > ---
> >  meson.build   | 2 +-
> >  meson_options.txt | 4 ++--
> >  2 files changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/meson.build b/meson.build
> > index add27b5dbac..2e1de2b2e20 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -22,7 +22,7 @@ project('mesa', ['c', 'cpp'], version : '17.3.0-devel', 
> > license : 'MIT',
> >  default_options : ['c_std=c99'])
> >  
> >  with_dri3 = true  # XXX: need a switch for this
> > -with_vulkan_icd_dir = get_option('vulkan_icd_dir')
> > +with_vulkan_icd_dir = get_option('vulkan-icd-dir')
> >  with_tests = get_option('build-tests')
> >  with_valgrind = get_option('valgrind')
> >  
> > diff --git a/meson_options.txt b/meson_options.txt
> > index 082ade7f480..d0f7cc9c7ed 100644
> > --- a/meson_options.txt
> > +++ b/meson_options.txt
> > @@ -22,9 +22,9 @@ option('platforms',  type : 'string',  value : 
> > 'x11,wayland',
> > description : 'comma separated list of window systems to support. 
> > wayland, x11, surfaceless, drm, etc.')
> >  option('vulkan-drivers', type : 'string',  value : 'intel,amd',
> > description : 'comma separated list of vulkan drivers to build.')
> > -option('shader-cache',type : 'boolean', value : true,
> > +option('shader-cache',   type : 'boolean', value : true,
> 
> Unrelated change (why have more than one space btw?)

Originally I had them all colomized and they looked pretty, but then I added
descriptions. I have a patch to remove the extra spaces, so I'll drop this
change.

Dylan

> 
> Series is:
> Reviewed-by: Eric Engestrom 
> 
> > description : 'Build with on-disk shader cache support')
> > -option('vulkan_icd_dir', type : 'string',  value : '',
> > +option('vulkan-icd-dir', type : 'string',  value : '',
> > description : 'Location relative to prefix to put vulkan icds on 
> > install. Default: $datadir/vulkan/icd.d')
> >  option('valgrind',   type : 'boolean', value : true,
> > description : 'Build with valgrind support if possible')
> > -- 
> > 2.14.1
> > 


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[Mesa-dev] [ANNOUNCE] mesa 17.2.2

[Juan A. Suarez Romero]

Mesa 17.2.2 is now available.

In this release we have:

In build and integration system, we add a dependency on libunwind when
running make distcheck, as this is optional for libgallium but we want
to catch any problem. As consequence, also force LLVM 3.3 in Travis
when building Gallium ST Other, as this is the minimum required version
we want to test. On the other hand, we link libmesautil into
u_atomic_test, as this is required by platforms without particular
atomic operations. In this sense, there's a patch to implement
__sync_val_compare_and_swap_8, required by 32-bit PowerPC platforms.
Finally, there is also a fix to build in armel devices.

State tracker gets a couple of patches, one that fixes boolean
comparison involving 64-bit unsigned integers, and another that fixes a
postprocessing issue.

Vulkan's Wayland WSI gets several fixes related with display handling,
that was causing crashes.

Intel ANV driver gets a couple of fixes, one about copying descriptors
and another for the view transformation.

Intel i965 driver gets also a couple of fixes, one that fixes a crash
in Haswell devices when uploading stencil textures using BLORP, and a
couple more regarding ARB_shader_atomic_counter_ops implementation.

Broadcom VC4 driver gets several use-after-free fixes, as well as
another couple more to fix issues in allocator and shadow resources.

AMD RADV driver gets several fixes to optimize NIR conditionals, fix
problems when doing statistics/occlusion queries, and also a workaround
fix for GFX9 scissor.

Radeonsi driver gets also several fixes related with OpenGL ES: a
workaround for gather4 on integer cube maps, a fix for array textures
layer coordinate, and another fix involved with nearest mip selection.

There are also several patches common to all AMD drivers that fixes
several cases in texture filtering.

Finally, we have other fixes for SWR, Etnaviv, NV20, the GLSL linker,
and EGL/DRI2

Last, but not least, now we support LLVM 5.0 in Gallium drivers.


Alexandru-Liviu Prodea (1):
  Scons: Add LLVM 5.0 support

Bas Nieuwenhuizen (1):
  radv: Check for GFX9 for 1D arrays in image_size intrinsic.

Boris Brezillon (1):
  broadcom/vc4: Fix infinite retry in vc4_bo_alloc()

Dave Airlie (3):
  radv/nir: call opt_remove_phis after trivial continues.
  ac/surface: handle S8 on gfx9
  st/glsl->tgsi: fix u64 to bool comparisons.

David Airlie (1):
  radv: add gfx9 scissor workaround

Emil Velikov (2):
  docs: add sha256 checksums for 17.2.1
  automake: enable libunwind in `make distcheck'

Eric Anholt (4):
  broadcom/vc4: Fix use-after-free for flushing when writing to a texture.
  broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear.
  broadcom/vc4: Fix use-after-free when deleting a program.
  broadcom/vc4: Keep pipe_sampler_view->texture matching the original 
texture.

Gert Wollny (2):
  travis: force llvm-3.3 for "make Gallium ST Other"
  travis: Add libunwind-dev to gallium/make builds

Grazvydas Ignotas (1):
  configure: check if -latomic is needed for __atomic_*

Ian Romanick (1):
  nv20: Fix GL_CLAMP

Jason Ekstrand (6):
  i965/blorp: Set r8stencil_needs_update when writing stencil
  vulkan/wsi/wayland: Stop printing out the DRM device
  vulkan/wsi/wayland: Refactor wsi_wl_display code
  vulkan/wsi/wayland: Stop caching Wayland displays
  vulkan/wsi/wayland: Copy wl_proxy objects from oldSwapchain if available
  vulkan/wsi/wayland: Return better error messages

Juan A. Suarez Romero (5):
  cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR 
initialization bug"
  cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size 
intrinsic."
  cherry-ignore: add "radv: copy the number of viewports/scissors at 
pipeline bind time"
  Update version to 17.2.2
  docs: add release notes for 17.2.2

Józef Kucia (1):
  anv: Fix descriptors copying

Kenneth Graunke (2):
  i965/vec4: Actually handle atomic op intrinsics.
  i965/vec4: Fix swizzles on atomic sources.

Leo Liu (1):
  st/va/postproc: use video original size for postprocessing

Lucas Stach (1):
  etnaviv: fix 16bpp clears

Matt Turner (2):
  util: Link libmesautil into u_atomic_test
  util/u_atomic: Add implementation of __sync_val_compare_and_swap_8

Nicolai Hähnle (9):
  radeonsi: workaround for gather4 on integer cube maps
  amd/common: round cube array slice in ac_prepare_cube_coords
  amd/common: add workaround for cube map array layer clamping
  glsl/linker: fix output variable overlap check
  radeonsi: fix array textures layer coordinate
  radeonsi: set MIP_POINT_PRECLAMP to 0
  amd/addrlib: fix missing va_end() after va_copy()
  amd/common: move ac_build_phi from radeonsi
  radeonsi: fix a regression in integer cube map handling

Samuel Iglesias Gonsálvez (1):
  anv: fix viewport transformation for z component

Samuel 

Re: [Mesa-dev] [PATCH 5/5] travis: add meson build for vulkan drivers.

[Emil Velikov]

On 2 October 2017 at 16:51, Eric Engestrom  wrote:
> On Sunday, 2017-10-01 03:58:28 +, Dylan Baker wrote:
>> Signed-off-by: Dylan Baker 
>> ---
>>  .travis.yml | 36 
>>  1 file changed, 36 insertions(+)
>>
>> diff --git a/.travis.yml b/.travis.yml
>> index d9a8bf5a9d4..e8fff1b66ab 100644
>> --- a/.travis.yml
>> +++ b/.travis.yml
>> @@ -27,6 +27,7 @@ env:
>>  - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
>>  - 
>> PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
>>  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
>> +- PATH="$HOME/prefix/bin:$PATH"
>>
>>  matrix:
>>include:
>> @@ -393,10 +394,34 @@ matrix:
>>  - libexpat1-dev
>>  - libx11-xcb-dev
>>  - libelf-dev
>> +- env:
>> +- LABEL="meson Vulkan"
>> +- BUILD=meson
>> +- MESON_OPTIONS="-Dbuild-tests=true"
>> +  addons:
>> +apt:
>> +  sources:
>> +- llvm-toolchain-trusty-3.9
>> +  packages:
>> +# LLVM packaging is broken and misses these dependencies
>> +- libedit-dev
>> +# From sources above
>> +- llvm-3.9-dev
>> +# Common
>> +- xz-utils
>> +- libexpat1-dev
>> +- libelf-dev
>> +- python3-pip
>>
>>  install:
>>- pip install --user mako
>>
>> +  # Install the latest meson from pip, since the version in the ubuntu 
>> repos is
>> +  # often quite old.
>> +  - if test "x$BUILD" = xmeson; then
>> +  pip3 install --user meson;
>> +fi
>> +
>># Since libdrm gets updated in configure.ac regularly, try to pick up the
>># latest version from there.
>>- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
>> @@ -471,6 +496,11 @@ install:
>>- tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
>>- (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && 
>> make install)
>>
>> +  # Meson requires ninja >= 1.6, but trusty has 1.3.x
>> +  - wget 
>> https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
>> +  - unzip ninja-linux.zip
>> +  - mv ninja $HOME/prefix/bin/
>> +
>># Generate the header since one is missing on the Travis instance
>>- mkdir -p linux
>>- printf "%s\n" \
>> @@ -510,3 +540,9 @@ script:
>>test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
>>scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
>>  fi
>> +
>> +  - if test "x$BUILD" = xmeson; then
>> +  cp -r linux src/intel/vulkan/;
>
> Is this needed? This just looks weird because it's not needed for
> the other build systems.
>
It's the equivalent of "export CC="$CC -isystem`pwd`"

Handling should be identical, regardless of the build system - be that
cp or export.

-Emil
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Re: [Mesa-dev] [PATCH] egl/wayland: Don't use dmabuf with no modifiers

[Daniel Stone]

Hey Emil,

On 2 October 2017 at 17:08, Emil Velikov  wrote:
> On 2 October 2017 at 16:55, Daniel Stone  wrote:
>> The dmabuf interface requires a valid modifier to be sent. If we don't
>> explicitly get a modifier from the driver, we can't know what to send;
>> it must be inferred from legacy side-channels (or assumed to linear, if
>> none exists).
>>
>> If we have no modifier, then we can only have a single-plane format
>> anyway, so fall back to the old wl_drm buffer import path.
>
> IIRC one my earlier questions was about this. The reply was that
> dmabuf should work fine with single-plane formats.

Should but doesn't, at least with Weston. :P Not sure about Mutter.

Either way, given that one of the primary testing targets is broken,
and we get no real advantage from using the dmabuf interface here,
might as well just revert it for now.

> Is that the root issue or it's the missing queryImage() error handling?
>
> Can I suggest separating the two?

OK.

>> Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver 
>> doesn't implement them")
> I think this should be
> Fixes: 02cc3593727 ("egl/wayland: Use linux-dmabuf interface for buffers")

I'm pretty sure it only came up after Marek's change? I can try to
bisect and see I guess, but yeah. Might as well take both of them,
that way stable@ should notice and pull in Marek's fix, which is also
entirely valid.

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH] egl/wayland: Don't use dmabuf with no modifiers

[Emil Velikov]

On 2 October 2017 at 16:55, Daniel Stone  wrote:
> The dmabuf interface requires a valid modifier to be sent. If we don't
> explicitly get a modifier from the driver, we can't know what to send;
> it must be inferred from legacy side-channels (or assumed to linear, if
> none exists).
>
> If we have no modifier, then we can only have a single-plane format
> anyway, so fall back to the old wl_drm buffer import path.
>
IIRC one my earlier questions was about this. The reply was that
dmabuf should work fine with single-plane formats.
Is that the root issue or it's the missing queryImage() error handling?

Can I suggest separating the two?

> Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver 
> doesn't implement them")
I think this should be
Fixes: 02cc3593727 ("egl/wayland: Use linux-dmabuf interface for buffers")

Thanks
Emil
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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

--- Comment #5 from Emil Velikov  ---
(In reply to alexander from comment #4)
> How to upgrade the version of the Shader?

That's not it works. Can you provide a more complete log/output from the game?
Alternatively getting some connection between the game <> Mesa devs is a nice
idea.

Some questions for the FS17 devs:
 - does the game use OpenGL 3.2 or later with Compat context?
If so I strongly recommend using a Core one.

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[Mesa-dev] [PATCH] egl/wayland: Don't use dmabuf with no modifiers

[Daniel Stone]

The dmabuf interface requires a valid modifier to be sent. If we don't
explicitly get a modifier from the driver, we can't know what to send;
it must be inferred from legacy side-channels (or assumed to linear, if
none exists).

If we have no modifier, then we can only have a single-plane format
anyway, so fall back to the old wl_drm buffer import path.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't 
implement them")
Reported-by: Andy Furniss 
Cc: Marek Olšák 
---
 src/egl/drivers/dri2/platform_wayland.c | 45 +++--
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 011dddfabf..b2c41507d1 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -678,23 +678,42 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  __DRIimage *image)
 {
struct wl_buffer *ret;
+   GLboolean query;
int width, height, fourcc, num_planes;
+   uint64_t modifier;
+
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, 
);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT,
+);
+   query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC,
+);
+   if (!query)
+  return NULL;
 
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
-   _planes);
+   query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NUM_PLANES,
+   _planes);
+   if (!query)
+  num_planes = 1;
 
-   if (dri2_dpy->wl_dmabuf && dri2_dpy->image->base.version >= 15) {
-  struct zwp_linux_buffer_params_v1 *params;
+   modifier = DRM_FORMAT_MOD_INVALID;
+   if (dri2_dpy->image->base.version >= 15) {
   int mod_hi, mod_lo;
-  int i;
 
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
-  _hi);
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
-  _lo);
+  query = dri2_dpy->image->queryImage(image,
+  __DRI_IMAGE_ATTRIB_MODIFIER_UPPER,
+  _hi);
+  query &= dri2_dpy->image->queryImage(image,
+   __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
+   _lo);
+  if (query) {
+ modifier = (uint64_t) mod_hi << 32;
+ modifier |= (uint64_t) (mod_lo & 0x);
+  }
+   }
+
+   if (dri2_dpy->wl_dmabuf && modifier != DRM_FORMAT_MOD_INVALID) {
+  struct zwp_linux_buffer_params_v1 *params;
+  int i;
 
   /* We don't need a wrapper for wl_dmabuf objects, because we have to
* create the intermediate params object; we can set the queue on this,
@@ -725,7 +744,7 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
 dri2_dpy->image->destroyImage(p_image);
 
  zwp_linux_buffer_params_v1_add(params, fd, i, offset, stride,
-mod_hi, mod_lo);
+modifier >> 32, modifier & 0x);
  close(fd);
   }
 
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 6/7] i965: Reported supported context priorities to EGL/DRI

[Kenneth Graunke]

On Monday, October 2, 2017 2:44:13 AM PDT Chris Wilson wrote:
> Quoting Kenneth Graunke (2017-09-29 22:59:56)
> > On Friday, September 29, 2017 1:03:14 PM PDT Chris Wilson wrote:
> > > Quoting Kenneth Graunke (2017-09-29 20:55:53)
> > > > On Friday, September 29, 2017 3:25:09 AM PDT Chris Wilson wrote:
> > > > > Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to
> > > > > report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on 
> > > > > the
> > > > > the default context. The kernel will validate the request to change 
> > > > > the
> > > > > property, so we get an accurate reflection of available support 
> > > > > (based on
> > > > > kernel version and privilege) and we should only have to do it once
> > > > > during screen setup -- although the SETPARAM should be fast, they are
> > > > > still an ioctl each.
> > > > > 
> > > > > Signed-off-by: Chris Wilson 
> > > > > Cc: Kenneth Graunke 
> > > > > Reviewed-by: Emil Velikov 
> > > > > ---
> > > > >  src/mesa/drivers/dri/i965/intel_screen.c | 13 +
> > > > >  1 file changed, 13 insertions(+)
> > > > > 
> > > > > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
> > > > > b/src/mesa/drivers/dri/i965/intel_screen.c
> > > > > index 22d9f19298..112935a580 100644
> > > > > --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > > > > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > > > > @@ -1373,6 +1373,19 @@ brw_query_renderer_integer(__DRIscreen 
> > > > > *dri_screen,
> > > > > case __DRI2_RENDERER_HAS_TEXTURE_3D:
> > > > >value[0] = 1;
> > > > >return 0;
> > > > > +   case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
> > > > > +  value[0] = 0;
> > > > > +  if (brw_hw_context_set_priority(screen->bufmgr,
> > > > > +   0, BRW_CONTEXT_HIGH_PRIORITY) == 
> > > > > 0)
> > > > > + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
> > > > > +  if (brw_hw_context_set_priority(screen->bufmgr,
> > > > > +   0, BRW_CONTEXT_LOW_PRIORITY) == 0)
> > > > > + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
> > > > > +  /* reset to default last, just in case */
> > > > > +  if (brw_hw_context_set_priority(screen->bufmgr,
> > > > > +   0, BRW_CONTEXT_MEDIUM_PRIORITY) 
> > > > > == 0)
> > > > > + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
> > > > > +  return 0;
> > > > > default:
> > > > >return driQueryRendererIntegerCommon(dri_screen, param, value);
> > > > > }
> > > > > 
> > > > 
> > > > Interesting, you're setting the priority of the default context (which
> > > > we never use), in order to test whether it works?  Does the kernel
> > > > actually set anything in that case, or does it just ignore it?
> > > 
> > > It sets it. It's just an integer and applied if the context is ever used
> > > for execbuf. As the kernel does apply the change, we reset to the
> > > default value as the last step. Although it is not stated, we do assume
> > > the query is only performed once at screen creation, so shouldn't be any
> > > concurrency issues..
> > 
> > That sounds bad, though, context 0 is the global default context.  So
> > this could affect the rest of the system.  You still have concurrency
> > issues with e.g. VAAPI running in another process, no?
> 
> Global? No, per-fd default context. The context is a slice of driver
> state (that also may happen to hold a copy of the logical GPU state).
> -Chris

Oh, okay, if it's a per-fd default context that should probably be okay.
Nobody ought to be using the default one anyway.

--Ken


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Re: [Mesa-dev] [PATCH 4/7] i965: Record the presence of the kernel scheduler

[Kenneth Graunke]

On Monday, October 2, 2017 1:52:12 AM PDT Joonas Lahtinen wrote:
> On Fri, 2017-09-29 at 12:52 -0700, Kenneth Graunke wrote:
> > On Friday, September 29, 2017 3:25:07 AM PDT Chris Wilson wrote:
> > > Mention to the debug log if the kernel scheduler is enabled; and in
> > > particular if it has preemption enabled.
> > > 
> > > Signed-off-by: Chris Wilson 
> > > Cc: Joonas Lahtinen 
> > > Cc: Ben Widawsky 
> > > Reviewed-by: Joonas Lahtinen 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_screen.c | 11 +++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
> > > b/src/mesa/drivers/dri/i965/intel_screen.c
> > > index bd1365f232..22d9f19298 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > > @@ -2516,6 +2516,17 @@ __DRIconfig **intelInitScreen2(__DRIscreen 
> > > *dri_screen)
> > >  
> > > intel_screen_init_surface_formats(screen);
> > >  
> > > +   if (INTEL_DEBUG & DEBUG_SUBMIT) {
> > 
> > How about:
> > 
> >if (INTEL_DEBUG & (DEBUG_SUBMIT | DEBUG_BAT)) {
> 
> Assuming that's DEBUG_BATCH (not some new Basic Acceptance Testing
> variable), that works too :)
> 
> Regards, Joonas

Ah yes, sorry, INTEL_DEBUG="bat" turns into INTEL_DEBUG & DEBUG_BATCH :)

--Ken


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Re: [Mesa-dev] [PATCH 5/5] travis: add meson build for vulkan drivers.

[Eric Engestrom]

On Sunday, 2017-10-01 03:58:28 +, Dylan Baker wrote:
> Signed-off-by: Dylan Baker 
> ---
>  .travis.yml | 36 
>  1 file changed, 36 insertions(+)
> 
> diff --git a/.travis.yml b/.travis.yml
> index d9a8bf5a9d4..e8fff1b66ab 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -27,6 +27,7 @@ env:
>  - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
>  - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
>  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
> +- PATH="$HOME/prefix/bin:$PATH"
>  
>  matrix:
>include:
> @@ -393,10 +394,34 @@ matrix:
>  - libexpat1-dev
>  - libx11-xcb-dev
>  - libelf-dev
> +- env:
> +- LABEL="meson Vulkan"
> +- BUILD=meson
> +- MESON_OPTIONS="-Dbuild-tests=true"
> +  addons:
> +apt:
> +  sources:
> +- llvm-toolchain-trusty-3.9
> +  packages:
> +# LLVM packaging is broken and misses these dependencies
> +- libedit-dev
> +# From sources above
> +- llvm-3.9-dev
> +# Common
> +- xz-utils
> +- libexpat1-dev
> +- libelf-dev
> +- python3-pip
>  
>  install:
>- pip install --user mako
>  
> +  # Install the latest meson from pip, since the version in the ubuntu repos 
> is
> +  # often quite old.
> +  - if test "x$BUILD" = xmeson; then
> +  pip3 install --user meson;
> +fi
> +
># Since libdrm gets updated in configure.ac regularly, try to pick up the
># latest version from there.
>- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
> @@ -471,6 +496,11 @@ install:
>- tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
>- (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && 
> make install)
>  
> +  # Meson requires ninja >= 1.6, but trusty has 1.3.x
> +  - wget 
> https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
> +  - unzip ninja-linux.zip
> +  - mv ninja $HOME/prefix/bin/
> +
># Generate the header since one is missing on the Travis instance
>- mkdir -p linux
>- printf "%s\n" \
> @@ -510,3 +540,9 @@ script:
>test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
>scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
>  fi
> +
> +  - if test "x$BUILD" = xmeson; then
> +  cp -r linux src/intel/vulkan/;

Is this needed? This just looks weird because it's not needed for
the other build systems.

Other than that, the series is:
Reviewed-by: Eric Engestrom 

And thanks for doing this, this will help catch conversion
failures/regressions :)

> +  meson _build $MESON_OPTIONS;
> +  ninja -C _build test;
> +fi
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 7/7] wayland-egl: rework and simplify wl_egl_window initialization

[Emil Velikov]

On 29 September 2017 at 21:40, Miguel Angel Vico  wrote:
>> Miguel I believe the comment correctly describes the design plan, while
>> addressing Dan's comment that things look a bit ugly.
>
> Yes. Thank you.
>
> Also, the whole series:
>
> Reviewed-by: Miguel A. Vico 
>
Smashing, thanks guys.
Pushed the series to master.

-Emil
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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

--- Comment #4 from alexander  ---
(In reply to Emil Velikov from comment #2)
> Implementing GL_NV_texture_compression_vtc in Mesa might be problematic
> since the extension IP status is "NVIDIA Proprietary".
How to upgrade the version of the Shader?

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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

--- Comment #3 from alexander  ---
Created attachment 134620
  --> https://bugs.freedesktop.org/attachment.cgi?id=134620=edit
Log FS17

Wine FS17 incorrectly defines my CPU. In fact AMD-A8 6410 with AMD Radeon R5
Graphics 4 core. I have an HP laptop.

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Re: [Mesa-dev] [PATCH] st/dri: don't expose modifiers in EGL if the driver doesn't implement them

[Daniel Stone]

Hi Andy,

On 27 September 2017 at 20:34, Andy Furniss  wrote:
> Marek Olšák wrote:
>> Sorry too late, I pushed it.
>>
>> I don't know if stable is affected.
>
> It regresses things starting on radeonsi using weston eg.
>
> mpv -
>
> [vo/opengl/wayland] error occurred on the display fd: closing file
> descriptor
>
> kodi -
>
> terminate called after throwing an instance of 'std::system_error'
>   what():  wl_display_dispatch_pending: Protocol error
>
> weston-simple-egl -
>
> [destroyed object]: error 7: importing the supplied dmabufs failed
> Error sending request: Broken pipe
> has EGL_EXT_buffer_age and EGL_EXT_swap_buffers_with_damage

Yeah, I've spotted that too. There's certainly a Mesa bug somewhere
(which I'm about to send a patch for), and also probably a Weston bug
too.

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH 4/5] meson: convert gtest to an internal dependency

[Eric Engestrom]

On Sunday, 2017-10-01 03:58:27 +, Dylan Baker wrote:
> In truth gtest is an external dependency that upstream expects you to
> "vendor" into your own tree. As such, it makes sense to treat it more
> like a dependency than an internal library, and collect it's
> requirements together in a dependency object.
> 
> Signed-off-by: Dylan Baker 
> ---
>  src/compiler/nir/meson.build | 4 ++--
>  src/gtest/meson.build| 6 ++
>  src/intel/compiler/meson.build   | 6 +++---
>  src/util/tests/string_buffer/meson.build | 4 ++--
>  4 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index c260dca5467..8a85d119530 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -197,8 +197,8 @@ if with_tests
>  [files('tests/control_flow_tests.cpp'), nir_opcodes_h],
>  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
>  include_directories : [inc_common],
> -dependencies : [dep_thread],
> -link_with : [libmesa_util, libnir, libgtest],
> +dependencies : [dep_thread, idep_gtest],
> +link_with : [libmesa_util, libnir],
>)
>  
>test('nir_control_flow', nir_control_flow_test)
> diff --git a/src/gtest/meson.build b/src/gtest/meson.build
> index b51504d400a..9832af93e25 100644
> --- a/src/gtest/meson.build
> +++ b/src/gtest/meson.build
> @@ -24,3 +24,9 @@ libgtest = static_library(
>include_directories : include_directories('include'),
>build_by_default : false,
>  )
> +
> +idep_gtest = declare_dependency(
> +  link_with : libgtest,
> +  include_directories : include_directories('include'),
> +  compile_args : ['-Wno-sign-compare'],

Does meson not support/provide -isystem? This might be something to ask for.

> +)
> diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
> index e12fa22cf1b..41c2f6ef1db 100644
> --- a/src/intel/compiler/meson.build
> +++ b/src/intel/compiler/meson.build
> @@ -146,9 +146,9 @@ if with_tests
>[t, nir_opcodes_h, ir_expression_operation_h],
>'test_@0@.cpp'.format(t),
>include_directories : [inc_common, inc_intel],
> -  link_with : [libgtest, libintel_compiler, libintel_common, libnir,
> -   libmesa_util, libisl],
> -  dependencies : [dep_thread, dep_dl],
> +  link_with : [libintel_compiler, libintel_common, libnir, libmesa_util,
> +   libisl],
> +  dependencies : [dep_thread, dep_dl, idep_gtest],
>  )
>  test(t, _exe)
>endforeach
> diff --git a/src/util/tests/string_buffer/meson.build 
> b/src/util/tests/string_buffer/meson.build
> index ea9b8a07dce..14dbebca7d8 100644
> --- a/src/util/tests/string_buffer/meson.build
> +++ b/src/util/tests/string_buffer/meson.build
> @@ -21,9 +21,9 @@
>  string_buffer_test = executable(
>'string_buffer_test',
>'string_buffer_test.cpp',
> -  dependencies : [dep_thread, dep_dl],
> +  dependencies : [dep_thread, dep_dl, idep_gtest],
>include_directories : inc_common,
> -  link_with : [libmesa_util, libgtest],
> +  link_with : [libmesa_util],
>  )
>  
>  test('string_buffer', string_buffer_test)
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH v2 2/3] vulkan/wsi: Report the correct min/maxImageCount

[Jason Ekstrand]

On Sun, Oct 1, 2017 at 10:32 PM, Neil Roberts  wrote:

> Jason Ekstrand  writes:
>
> > Hey, Neil!
>
> Hey Jason :)
>
> > Yeah... That's a bit unfortunate.  The problem is that we have no way of
> > returning a different number of images depending on the mode.  In theory,
> > we could start out at 2 and return SUBOPTIMAL and force the application
> to
> > recreate the swapchain with more images until we have enough.  That would
> > be a real pain though...  In not sure what the best option is.
>
> Hm, was there a problem with the previous approach? Ie, in the surface
> caps it always returns minImages as two but when it comes to creating
> the swapchain if the present mode is MAILBOX then it will go ahead and
> create 4 images. The parameter in the create call is also called
> “minImages” not “numImages” and the spec implies it’s ok to create more
> than were requested. It seems like that would just do the right thing.
>

I wish...  Unfortunately, the spec says:

Let *n* be the total number of images in the swapchain, *m* be the value of
VkSurfaceCapabilitiesKHR::minImageCount, and *a* be the number of
presentable images that the application has currently acquired (i.e. images
acquired with vkAcquireNextImageKHR, but not yet presented with
vkQueuePresentKHR). vkAcquireNextImageKHR *can* always succeed if a ≤ n - m
at the time vkAcquireNextImageKHR is called. vkAcquireNextImageKHR *should*
not be called if a > n - m with a timeout of UINT64_MAX; in such a case,
vkAcquireNextImageKHR *may* block indefinitely.

Because this is based on the number of images in the swapchain and the
VkSurfaceCapabilitiesKHR field, if we return a swapchain with more images,
n will be larger but not m so that just means that they can acquire more
images, not that we've reserved more.  Arguably, that's a spec bug and I'll
file one and see where it goes.  However, it's definitely what the spec
says today. :-(

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Re: [Mesa-dev] [PATCH] swr/rast: do not crash on NULL strings returned by getenv

[Emil Velikov]

On 19 September 2017 at 21:08, Rowley, Timothy O
 wrote:
> I have a bit of a preference for Eric’s version.
>
Ack. Amended and pushed to master.

-Emil
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[Mesa-dev] [Bug 102847] swr fail to build with llvm-5.0.0

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102847

--- Comment #4 from Juan A. Suarez  ---
Patch https://patchwork.freedesktop.org/patch/177834/ has been landed upstream.

Does it fix this issue?

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Re: [Mesa-dev] [PATCH v3 1/2] configure+mesa/st: unify check for -std=c++11 support and enable accordingly

[Gert Wollny]

Am Montag, den 02.10.2017, 15:16 +0100 schrieb Emil Velikov:
> 
> 
> While rebuilding most of Mesa + its tests (as illustrated in 2/2)
> only for a single test is very wasteful.
> 
> Let's not do that, pretty please?

I'm not quite sure what you mean by that. IHMO as long as mesa is
supposed to support pre c++11 compilers at least one build on travis
should account for this - especially considering that now, with g++ >=
6 enabling c++14 by default and being the compiler of choice in
Debian/stable and derivatives, there is a certain danger that c++11 or
even c++14 code creeps in without the authors and reviewers realizing
it (as [1] showed).

[1] https://bugs.freedesktop.org/show_bug.cgi?id=103002   
  (string_buffer_test.cpp:43: error:  ISO C++ forbids 
   initialization of member ‘str1’)

FWIW, personally I'd prefer if mesa would already require a c++11
capable compiler considering that with LLVM >= 3.9  the -std=c++11 flag
is already forced on all depending modules via LLVM_CXXFLAGS.

> 
> > [...]
> > 
> > > 
> 
> I'm roughly aware of the advantages, although I'm also thinking of
> the disadvantages. 
> Close to nobody is interested in reading or maintaining m4, that I
> know of. Thus having a custom one in tree is a bad idea.
Okay, the updated patch will use the AX_CHECK_COMPILE_FLAG.

Best, 
Gert 

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Re: [Mesa-dev] [Mesa-stable] [PATCH] st/dri: don't expose modifiers in EGL if the driver doesn't implement them

[Emil Velikov]

On 27 September 2017 at 20:27, Juan A. Suarez Romero
 wrote:
> On Wed, 2017-09-27 at 18:09 +0100, Emil Velikov wrote:
>> On 27 September 2017 at 17:28, Marek Olšák  wrote:
>> > On Wed, Sep 27, 2017 at 6:22 PM, Emil Velikov  
>> > wrote:
>> > > On 27 September 2017 at 16:00, Daniel Stone  wrote:
>> > > > Hi Marek,
>> > > >
>> > > > On 27 September 2017 at 15:55, Marek Olšák  wrote:
>> > > > > if (dmabuf_ret && dmabuf_ret->val.val_bool) {
>> > > > >uint64_t cap;
>> > > > >
>> > > > >if (drmGetCap(sPriv->fd, DRM_CAP_PRIME, ) == 0 &&
>> > > > >(cap & DRM_PRIME_CAP_IMPORT)) {
>> > > > >   dri2ImageExtension.createImageFromFds = dri2_from_fds;
>> > > > >   dri2ImageExtension.createImageFromDmaBufs = 
>> > > > > dri2_from_dma_bufs;
>> > > > >   dri2ImageExtension.createImageFromDmaBufs2 = 
>> > > > > dri2_from_dma_bufs2;
>> > > > >   dri2ImageExtension.queryDmaBufFormats = 
>> > > > > dri2_query_dma_buf_formats;
>> > > > > - dri2ImageExtension.queryDmaBufModifiers =
>> > > > > -dri2_query_dma_buf_modifiers;
>> > > > > + if (pscreen->query_dmabuf_modifiers) {
>> > > > > +dri2ImageExtension.queryDmaBufModifiers =
>> > > > > +   dri2_query_dma_buf_modifiers;
>> > > > > + }
>> > > >
>> > > > This should also not expose queryDmaBufFormats, since that is also
>> > > > part of EGL_EXT_image_dma_buf_import_modifiers, which is pretty
>> > > > useless without modifiers.
>> > > >
>> > >
>> > > True, it's useless. Suggestion makes the code a bit confusing though.
>> > > After all EGL already checks that all the entry points are present
>> > > before advertising the extension.
>> > >
>> > > Either way, I think we want this in stable, right?
>> >
>> > Sorry too late, I pushed it.
>> >
>>
>> No need to apologise.
>>
>> > I don't know if stable is affected.
>> >
>>
>> You're right - code was introduced around commit
>> f84bb6a9d91521de6da4c3d1ddd8de456761efaa.
>> The latter of which landed in Mesa 17.2.0-devel
>>
>
> Not sure if I'm understanding correctly. Do you mean we don't need this
> patch in stable?
>
Hmm I misread the version as "17.3.0-devel" ...
Patch is a simple NULL check so it won't hurt to have in 17.2.x

-Emil
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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Trevor Sandy]

Many thanks for the details - and the reminder on passively contributing to
wasting developers' time :-)
For the content I created, I will proceed accordingly.

I've reached out to the repo owner where I got the patches I use to
validate the MinGW build to see his opinion. If there is no conflict, I'll
be pleased to follow the details you provided to submit the patches I use.

I believe, George will provide his patch accordingly.

Cheers,

On Mon, 2 Oct 2017 at 16:47 Emil Velikov  wrote:

> On 2 October 2017 at 15:16, Trevor (CIMdata) 
> wrote:
> > Hello Emil,
> >
> > Yes, I did see the AppVeyor integraton for MSVC. It could be quite easy
> to
> > add the MinGW scope to the metrix.
> >
> >
> >
> > I don’t really know how to ‘upsteam’ the patches I use mostly because I
> am
> > not the author. Do I just submit a PR? Anyway to help George with his
> patch
> > – which fixes the MinGW build – I have done the CI script, AppVeyor.yml
> and
> > set up AV repo. My source if free and w/o license. Please feel free to
> use
> > it if you wish. Many thanks!
> >
> The top page while searching for "mesa submitting patches" gives [1].
>
> Please skim through it but in a gist:
>  - fire git format-patch(ed) patches to the list. Since I'm lazy I
> directly use git send-email $old_sha..$new_sha
>  - patches should have commit messages
>  - try to attribute the author when that's not you - see git commit
> --author="foo"
>
> Keep in mind that if a developer has to spend time X applying OOT
> patches, that's X less time for addressing other issues.
>
> Thanks
> Emil
>
> [1] https://www.mesa3d.org/submittingpatches.html
>
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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

--- Comment #2 from Emil Velikov  ---
What hardware are you using? Can you attach the FS17 log (as plain text). 

Implementing GL_NV_texture_compression_vtc in Mesa might be problematic since
the extension IP status is "NVIDIA Proprietary".

Then again, the log should give us a bit more context.


https://www.khronos.org/registry/OpenGL/extensions/NV/NV_texture_compression_vtc.txt

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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Emil Velikov]

On 2 October 2017 at 15:16, Trevor (CIMdata)  wrote:
> Hello Emil,
>
> Yes, I did see the AppVeyor integraton for MSVC. It could be quite easy to
> add the MinGW scope to the metrix.
>
>
>
> I don’t really know how to ‘upsteam’ the patches I use mostly because I am
> not the author. Do I just submit a PR? Anyway to help George with his patch
> – which fixes the MinGW build – I have done the CI script, AppVeyor.yml and
> set up AV repo. My source if free and w/o license. Please feel free to use
> it if you wish. Many thanks!
>
The top page while searching for "mesa submitting patches" gives [1].

Please skim through it but in a gist:
 - fire git format-patch(ed) patches to the list. Since I'm lazy I
directly use git send-email $old_sha..$new_sha
 - patches should have commit messages
 - try to attribute the author when that's not you - see git commit
--author="foo"

Keep in mind that if a developer has to spend time X applying OOT
patches, that's X less time for addressing other issues.

Thanks
Emil

[1] https://www.mesa3d.org/submittingpatches.html
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Re: [Mesa-dev] [PATCH 2/4] gallivm: allow additional llc options

[Ben Crocker]

- Original Message -
> From: "Nicolai Hähnle" 
> To: "Ben Crocker" , mesa-dev@lists.freedesktop.org
> Cc: "Emil Velikov" , "17.2" 
> 
> Sent: Monday, October 2, 2017 5:40:31 AM
> Subject: Re: [Mesa-dev] [PATCH 2/4] gallivm: allow additional llc options
> 
> On 28.09.2017 20:09, Ben Crocker wrote:
> > In init_native_targets, allow the passing of additional options to
> > the LLC compiler via new GALLIVM_LLC_OPTIONS environmental control.
> > This option is available only #ifdef DEBUG, initially.
> > At top, add #include  for LLVMParseCommandLineOptions()
> > declaration.
> > 
> > Cc: "17.2" 
> > 
> > Signed-off-by: Ben Crocker 
> > ---
> >   src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 21 +
> >   1 file changed, 21 insertions(+)
> > 
> > diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> > b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> > index 342cb38..0b43c96 100644
> > --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> > +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> > @@ -49,6 +49,7 @@
> >   #endif
> >   
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -122,6 +123,26 @@ static void init_native_targets()
> >  llvm::InitializeNativeTargetAsmPrinter();
> >   
> >  llvm::InitializeNativeTargetDisassembler();
> > +#if DEBUG
> > +   {
> > +  char *env_llc_options = getenv("GALLIVM_LLC_OPTIONS");
> > +  if (env_llc_options) {
> > + char *option;
> > + char *options[64] = {(char *) "llc"};  // Warning without
> > cast
> > + int   n;
> > + for (n = 0, option = strtok(env_llc_options, " "); option; n++,
> > option = strtok(NULL, " ")) {
> > +options[n + 1] = option;
> > + }
> > + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM |
> > GALLIVM_DEBUG_DUMP_BC)) {
> > +debug_printf("llc additional options (%d):\n", n);
> > +for (int i = 1; i <= n; i++)
> > +   debug_printf("\t%s\n", options[i]);
> > +debug_printf("\n");
> > + }
> > + LLVMParseCommandLineOptions(n + 1, options, NULL);
> > +  }
> > +   }
> > +#endif
> 
> Just FYI, we're also calling LLVMParseCommandLineOptions from
> ac_llvm_util.c, and that function doesn't seem to appreciate being
> called multiple times. Not really an issue here since this will surely
> only be used for llvmpipe, so:
> 

Indeed, I used the code in ac_llvm_util.c as a model for my code.
And you're right: my change is for llvmpipe only.

> Acked-by: Nicolai Hähnle 

Thanks for the review and ack

-- Ben

> 
> 
> >   }
> >   
> >   extern "C" void
> > 
> 
> 
> --
> Lerne, wie die Welt wirklich ist,
> Aber vergiss niemals, wie sie sein sollte.
> 
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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

alexander  changed:

   What|Removed |Added

 QA Contact|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org
  Component|GLX |glsl-compiler

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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

--- Comment #1 from alexander  ---
And the proprietary driver cannot be installed (does Not work).

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[Mesa-dev] [Bug 103062] Error starting game FS17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103062

Bug ID: 103062
   Summary: Error starting game FS17
   Product: Mesa
   Version: 17.2
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: GLX
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: sascha.spa...@yandex.ru
QA Contact: mesa-dev@lists.freedesktop.org

Hello, I cannot start Farming Simulator 17 to mesa. Gives a window "failed to
initialize 3D system. No shader 2.0. To update your graphics driver." But if
the driver is the newest?! Must only work on proprietary drivers, find this
error failed to log the previous game Farming Simulator 15, though the game
works, but there's an error with shaders: Shader Version: 1.30
GL_NV_texture_compression_vtc not supported
How to upgrade the version of the Shader ? Fix this bug please.

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Re: [Mesa-dev] [PATCH v3 1/2] configure+mesa/st: unify check for -std=c++11 support and enable accordingly

[Emil Velikov]

On 2 October 2017 at 15:04, Gert Wollny  wrote:
> Am Montag, den 02.10.2017, 13:37 +0100 schrieb Emil Velikov:
>> Hi Gert,
>>
>> On 19 September 2017 at 12:35, Gert Wollny 
>> wrote:
>> > Unify the CXX feature tests for C++11 support that is required for
>> > SWR, clover, and mesa/st/tests.
>> >
>>
>> Surely we'll have capable compiler in 90+% of the time, still asking
>> for C++11 for single test is an overkill.
>
> Hence my attempt to unify the test for the three cases where c++11 is
> already mandatory.
>
SWR and Clover have been around for ages and they absolutely require C++11.
While rebuilding most of Mesa + its tests (as illustrated in 2/2) only
for a single test is very wasteful.

Let's not do that, pretty please?

> [...]
>
>>
>> > ---
>> >  .travis.yml   |   1 +
>>
>> Unrelated/undocumented change?
>
> Sorry. slipped my attention.
>
>>
>> >  configure.ac  |  13 +-
>> >  m4/ax_cxx_compile_stdcxx.m4   | 987
>> > ++
>>
>> Please don't add custom m4 unless absolutely needed.
>
> The advantage of this module is that it actually tests features of the
> required standard, and if the compiler enables them by default, no flag
> is needed. The result is cached and the test already support c++14 and
> c++17.
>
> I can also use the already established AX_CHECK_COMPILE_FLAG, and if
> you say so, I'll do it, but IMHO the required changes to configure.ac
> make the code look less clean.
>
I'm roughly aware of the advantages, although I'm also thinking of the
disadvantages.
Close to nobody is interested in reading or maintaining m4, that I
know of. Thus having a custom one in tree is a bad idea.


>>
>> > --- a/configure.ac
>> > +++ b/configure.ac
>> > @@ -301,8 +301,12 @@ AX_CHECK_COMPILE_FLAG([-
>> > Wall], [CXXFLAGS="$CXXFL
>> >  AX_CHECK_COMPILE_FLAG([-fno-math-
>> > errno],   [CXXFLAGS="$CXXFLAGS -fno-math-
>> > errno"])
>> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
>> > math],[CXXFLAGS="$CXXFLAGS -fno-trapping-
>> > math"])
>> >  AX_CHECK_COMPILE_FLAG([-
>> > fvisibility=hidden],   [VISIBILITY_CXXFLAGS="-
>> > fvisibility=hidden"])
>> > +AX_CXX_COMPILE_STDCXX(11, noext, optional)
>> > +
>> >  AC_LANG_POP([C++])
>> >
>> > +AM_CONDITIONAL(HAVE_STD_CXX11, test "x$HAVE_CXX11" = "x1")
>> > +
>> >  # Flags to help ensure that certain portions of the code -- and
>> > only those
>> >  # portions -- can be built with MSVC:
>> >  # - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe,
>> > and
>> > @@ -2234,9 +2238,7 @@ if test "x$enable_opencl" = xyes; then
>> >  AC_MSG_ERROR([cannot enable OpenCL without Gallium])
>> >  fi
>> >
>> > -if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4
>> > -a $GCC_VERSION_MINOR -lt 7; then
>> > -AC_MSG_ERROR([gcc >= 4.7 is required to build clover])
>> > -fi
>> > +AX_CXX_COMPILE_STDCXX(11, noext, mandatory)
>> >
>>
>> Why check again - you already know the result.
>
> The result is cached, so calling the macro again is of no run-time
> consequence. The alternative is to replace this one-liner with a three
> line if-then statement (same if I switch to AX_CHECK_COMPILE_FLAG).
>
Surely a simple if check is not that ugly?

-Emil
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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Trevor (CIMdata)]

Hello Emil,
Yes, I did see the AppVeyor integraton for MSVC. It could be quite easy to add 
the MinGW scope to the metrix.

I don’t really know how to ‘upsteam’ the patches I use mostly because I am not 
the author. Do I just submit a PR? Anyway to help George with his patch – which 
fixes the MinGW build – I have done the CI script, AppVeyor.yml and set up AV 
repo. My source if free and w/o license. Please feel free to use it if you 
wish. Many thanks!

Cheers,

Trevor SANDY
+33 682 100 571

From: Emil Velikov
Sent: 02 October 2017 16:04
To: Trevor Sandy
Cc: Kyriazis, George; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

Hi Trevor,

On 2 October 2017 at 13:48, Trevor Sandy  wrote:
> Hi George,
>
> You might be interested to know I have set up a CI env on AppVeyor for MinGW
> builds.
>
> Here is the GitHub repo: https://github.com/trevorsandy/osmesa_mingw_av.
> Follow the badge in the README to the AppVeyor instance.
>
> You can demo your patches quite easily - see the README.md on how to extract
> source that can be used by my build script. Or change set the version to
> download and build its source bundle. Perhaps later on I'll add the ability
> to get build content (tag, branch, commit etc...) directly from Mesa's git
> repo.
>
The upstream Mesa repository has AppVeyor integration, admittedly it
builds only with MSVC.

If you want for things to work, I strongly recommend upstreaming your patches.
Otherwise it will be in a perpetual state of brokenness and you'll
have to dedicate even more resources as time goes by.

Thanks
Emil

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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Kyriazis, George]

Emil,

I’m working with Trevor to upstream the correct versions of the swr patches.

Thanks,

George

> On Oct 2, 2017, at 9:04 AM, Emil Velikov  wrote:
> 
> Hi Trevor,
> 
> On 2 October 2017 at 13:48, Trevor Sandy  wrote:
>> Hi George,
>> 
>> You might be interested to know I have set up a CI env on AppVeyor for MinGW
>> builds.
>> 
>> Here is the GitHub repo: https://github.com/trevorsandy/osmesa_mingw_av.
>> Follow the badge in the README to the AppVeyor instance.
>> 
>> You can demo your patches quite easily - see the README.md on how to extract
>> source that can be used by my build script. Or change set the version to
>> download and build its source bundle. Perhaps later on I'll add the ability
>> to get build content (tag, branch, commit etc...) directly from Mesa's git
>> repo.
>> 
> The upstream Mesa repository has AppVeyor integration, admittedly it
> builds only with MSVC.
> 
> If you want for things to work, I strongly recommend upstreaming your patches.
> Otherwise it will be in a perpetual state of brokenness and you'll
> have to dedicate even more resources as time goes by.
> 
> Thanks
> Emil

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Re: [Mesa-dev] [OS]Mesa MinGW AppVeyor Repository

[Emil Velikov]

Hi Trevor,

On 2 October 2017 at 13:48, Trevor Sandy  wrote:
> Hi George,
>
> You might be interested to know I have set up a CI env on AppVeyor for MinGW
> builds.
>
> Here is the GitHub repo: https://github.com/trevorsandy/osmesa_mingw_av.
> Follow the badge in the README to the AppVeyor instance.
>
> You can demo your patches quite easily - see the README.md on how to extract
> source that can be used by my build script. Or change set the version to
> download and build its source bundle. Perhaps later on I'll add the ability
> to get build content (tag, branch, commit etc...) directly from Mesa's git
> repo.
>
The upstream Mesa repository has AppVeyor integration, admittedly it
builds only with MSVC.

If you want for things to work, I strongly recommend upstreaming your patches.
Otherwise it will be in a perpetual state of brokenness and you'll
have to dedicate even more resources as time goes by.

Thanks
Emil
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Re: [Mesa-dev] [PATCH v3 1/2] configure+mesa/st: unify check for -std=c++11 support and enable accordingly

[Gert Wollny]

Am Montag, den 02.10.2017, 13:37 +0100 schrieb Emil Velikov:
> Hi Gert,
> 
> On 19 September 2017 at 12:35, Gert Wollny 
> wrote:
> > Unify the CXX feature tests for C++11 support that is required for
> > SWR, clover, and mesa/st/tests.
> > 
> 
> Surely we'll have capable compiler in 90+% of the time, still asking
> for C++11 for single test is an overkill.

Hence my attempt to unify the test for the three cases where c++11 is
already mandatory. 

[...]

> 
> > ---
> >  .travis.yml   |   1 +
> 
> Unrelated/undocumented change?

Sorry. slipped my attention. 

> 
> >  configure.ac  |  13 +-
> >  m4/ax_cxx_compile_stdcxx.m4   | 987
> > ++
> 
> Please don't add custom m4 unless absolutely needed.

The advantage of this module is that it actually tests features of the
required standard, and if the compiler enables them by default, no flag
is needed. The result is cached and the test already support c++14 and
c++17. 

I can also use the already established AX_CHECK_COMPILE_FLAG, and if
you say so, I'll do it, but IMHO the required changes to configure.ac
make the code look less clean. 

> 
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -301,8 +301,12 @@ AX_CHECK_COMPILE_FLAG([-
> > Wall], [CXXFLAGS="$CXXFL
> >  AX_CHECK_COMPILE_FLAG([-fno-math-
> > errno],   [CXXFLAGS="$CXXFLAGS -fno-math-
> > errno"])
> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> > math],[CXXFLAGS="$CXXFLAGS -fno-trapping-
> > math"])
> >  AX_CHECK_COMPILE_FLAG([-
> > fvisibility=hidden],   [VISIBILITY_CXXFLAGS="-
> > fvisibility=hidden"])
> > +AX_CXX_COMPILE_STDCXX(11, noext, optional)
> > +
> >  AC_LANG_POP([C++])
> > 
> > +AM_CONDITIONAL(HAVE_STD_CXX11, test "x$HAVE_CXX11" = "x1")
> > +
> >  # Flags to help ensure that certain portions of the code -- and
> > only those
> >  # portions -- can be built with MSVC:
> >  # - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe,
> > and
> > @@ -2234,9 +2238,7 @@ if test "x$enable_opencl" = xyes; then
> >  AC_MSG_ERROR([cannot enable OpenCL without Gallium])
> >  fi
> > 
> > -if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4
> > -a $GCC_VERSION_MINOR -lt 7; then
> > -AC_MSG_ERROR([gcc >= 4.7 is required to build clover])
> > -fi
> > +AX_CXX_COMPILE_STDCXX(11, noext, mandatory)
> > 
> 
> Why check again - you already know the result.

The result is cached, so calling the macro again is of no run-time
consequence. The alternative is to replace this one-liner with a three
line if-then statement (same if I switch to AX_CHECK_COMPILE_FLAG). 

> 
> >  if test "x$have_libclc" = xno; then
> >  AC_MSG_ERROR([pkg-config cannot find libclc.pc which is
> > required to build clover.
> > @@ -2518,10 +2520,7 @@ if test -n "$with_gallium_drivers"; then
> >  xswr)
> >  llvm_require_version $LLVM_REQUIRED_SWR "swr"
> > 
> > -swr_require_cxx_feature_flags "C++11" "__cplusplus >=
> > 201103L" \
> > -",-std=c++11" \
> > -SWR_CXX11_CXXFLAGS
> > -AC_SUBST([SWR_CXX11_CXXFLAGS])
> > +   AX_CXX_COMPILE_STDCXX(11, noext, mandatory)
> > 
> 
> Ditto.

As commented above. 


> 
> You'd want to update the other SWR_CXX11_CXXFLAGS reference further
> down.
I'll re-check, but I though I got all the references (and on travis all
compiled fine). 

> 
> > --- a/src/gallium/drivers/swr/Makefile.am
> > +++ b/src/gallium/drivers/swr/Makefile.am
> > @@ -22,7 +22,7 @@
> >  include Makefile.sources
> >  include $(top_srcdir)/src/gallium/Automake.inc
> > 
> > -AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX11_CXXFLAGS)
> > +AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(CXX11_FLAGS)
> > 
> >  noinst_LTLIBRARIES = libmesaswr.la
> > 
> > @@ -39,7 +39,7 @@ COMMON_CXXFLAGS = \
> > -fno-strict-aliasing \
> > $(GALLIUM_DRIVER_CFLAGS) \
> > $(LLVM_CXXFLAGS) \
> > -   $(SWR_CXX11_CXXFLAGS) \
> > +   $(CXX11_FLAGS) \
> > -I$(builddir)/rasterizer/codegen \
> > -I$(builddir)/rasterizer/core \
> > -I$(builddir)/rasterizer/jitter \
> > diff --git a/src/gallium/state_trackers/clover/Makefile.am
> > b/src/gallium/state_trackers/clover/Makefile.am
> > index 321393536d..35b43b380c 100644
> > --- a/src/gallium/state_trackers/clover/Makefile.am
> > +++ b/src/gallium/state_trackers/clover/Makefile.am
> > @@ -31,14 +31,14 @@ endif
> >  noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la
> > 
> >  libcltgsi_la_CXXFLAGS = \
> > -   -std=c++11 \
> > +   ${CXX11_FLAGS} \
> 
> Please stay consistent through the file 's/{/(';'s/}/)'

Okay, I'll recheck consistency. 

many thanks, 
Gert 
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Re: [Mesa-dev] [PATCH 01/11] radeonsi: use ac helpers for bitcasts

[Marek Olšák]

This reply of yours doesn't contain anything. (clipped message?)

Marek
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Re: [Mesa-dev] [PATCH 00/15] Import libtxc_dxtn's S3TC code into Mesa!

[Emil Velikov]

On 2 October 2017 at 07:59, Matt Turner  wrote:
> The patent on S3TC has now expired! Rejoice!
>
It's time to open that 20 year old bottle of wine ;-)

> This series imports the code from Roland's libtxc_dxtn into Mesa and cleans up
> some mess dealing with the possibility of S3TC not being available.
>
> EXT_texture_compression_s3tc and ANGLE_texture_compression_dxt are now always
> enabled where supported.
>
> Note that I did almost nothing to fix the style of the imported code. Feel 
> free
> to send patches, but I'm not interested in making those changes in this 
> series.
>
Agreed, one could polish at a later stage. Be that coding style or
performance(?).

>
> I also considered using Rich Geldreich's crunch [2], but a few things made be
> choose to start with libtxc_dxtn instead:
>
>- crunch is written bn C++ and does not look like Mesa code at all.
>
>- Higher risk. Unknown how it compares to libtxc_dxtn. I can believe
>  libtxc_dxtn does a worse job compressing, but at least we know exactly
>  what we are getting with it.
>
>- crunch actually does a lot more than just DXT1/a/3/5. Was unclear how
>  separable those pieces were from the rest.
>
Better the devil we know than the one we don't. At least to begin with.

There's a few small suggestions - feel free to take or leave, all but
the 1/15 ones.

Namely:
I really think we want to have reference to where the import came
from. That plus keeping any other changes (even if code motion) as
separate patches.

With that the series is:
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

[Emil Velikov]

On 2 October 2017 at 07:59, Matt Turner  wrote:

> +#include "../../../mesa/main/texcompress_s3tc_tmp.h"
>
This feels a bit dirty. If people are not too keen on the idea,
another approach is to have the code in src/util/

-Emil
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Re: [Mesa-dev] [PATCH 06/15] mesa: Call DXTn functions directly

[Emil Velikov]

On 2 October 2017 at 14:05, Emil Velikov  wrote:

>> -   if (ext_tx_compress_dxtn) {
>> -  (*ext_tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
>> +   if (tx_compress_dxtn) {
>> +  (*tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
> Please use something like the following. It will drop the unneeded
> checks w/o having to re-indent the whole thing.
>
>{
>   tx_compress_dxtn(3, srcWidth, srcHeight, pixels,
> ...
>
Please ignore - just saw you're handing that in 7/15.

-Emil
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Re: [Mesa-dev] [PATCH 03/15] mesa: Remove commented-out DXTn fetch code

[Emil Velikov]

On 2 October 2017 at 07:59, Matt Turner  wrote:
> Has been disabled for 12 years.
> ---
>  src/mesa/main/texcompress_s3tc_tmp.h | 80 
> 
>  1 file changed, 80 deletions(-)
>
I would have made this 2/15 since it's a bit meh to move dead code.

-Emil
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Re: [Mesa-dev] [PATCH 06/15] mesa: Call DXTn functions directly

[Emil Velikov]

On 2 October 2017 at 07:59, Matt Turner  wrote:
> ---
>  src/mesa/main/texcompress_s3tc.c | 117 
> +--
>  1 file changed, 25 insertions(+), 92 deletions(-)
>
> diff --git a/src/mesa/main/texcompress_s3tc.c 
> b/src/mesa/main/texcompress_s3tc.c
> index e08ed23d3a..e74e4c402a 100644
> --- a/src/mesa/main/texcompress_s3tc.c
> +++ b/src/mesa/main/texcompress_s3tc.c
> @@ -43,78 +43,11 @@
>  #include "util/format_srgb.h"
>
>
> -#if defined(_WIN32) || defined(WIN32)
> -#define DXTN_LIBNAME "dxtn.dll"
> -#define RTLD_LAZY 0
> -#define RTLD_GLOBAL 0
> -#elif defined(__CYGWIN__)
> -#define DXTN_LIBNAME "cygtxc_dxtn.dll"
> -#else
> -#define DXTN_LIBNAME "libtxc_dxtn.so"
> -#endif
> -
Yay, less platform specific handling ;-)


> -   if (ext_tx_compress_dxtn) {
> -  (*ext_tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
> +   if (tx_compress_dxtn) {
> +  (*tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
Please use something like the following. It will drop the unneeded
checks w/o having to re-indent the whole thing.

   {
  tx_compress_dxtn(3, srcWidth, srcHeight, pixels,
...


Thanks
Emil
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