Re: [Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

[Kenneth Graunke]

On Tuesday, November 13, 2018 2:33:59 PM PST Anuj Phogat wrote:
> L3 allocation table in h/w specification recommends using 4 KB
> granularity for programming allocation fields in L3CNTLREG.
> 
> Signed-off-by: Anuj Phogat 
> Cc: Kenneth Graunke 
> Cc: Francisco Jerez 
> Cc: Lionel Landwerlin 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h   | 1 +
>  src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 897c91aa31e..b8ada02d6eb 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>  # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
>  # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
>  # define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
> +# define GEN8_L3CNTLREG_USE_FULL_WAYS  (1 << 10)
>  
>  #define GEN10_CACHE_MODE_SS0x0e420
>  #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
> b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index 8c6c4c47481..fb9b2703a50 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct 
> gen_l3_config *cfg)
>assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && 
> !cfg->n[GEN_L3P_T]);
>  
>const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
> + (devinfo->gen == 11 ? GEN8_L3CNTLREG_USE_FULL_WAYS : 0) |
>   SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
>   SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
>   SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
> 

I agree that we ought to set this bit, in whatever solution we
ultimately come up with.


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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Francisco Jerez]

Kenneth Graunke  writes:

> On Thursday, November 15, 2018 5:51:18 PM PST Francisco Jerez wrote:
>> Anuj Phogat  writes:
>> 
>> > Use L3 configuration table specified in h/w specification.
>> >
>> > Signed-off-by: Anuj Phogat 
>> > Cc: Kenneth Graunke 
>> > Cc: Francisco Jerez 
>> > Cc: Lionel Landwerlin 
>> > ---
>> >  src/intel/common/gen_l3_config.c | 16 ++--
>> >  1 file changed, 10 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/src/intel/common/gen_l3_config.c 
>> > b/src/intel/common/gen_l3_config.c
>> > index b977c6ab136..079608198bc 100644
>> > --- a/src/intel/common/gen_l3_config.c
>> > +++ b/src/intel/common/gen_l3_config.c
>> > @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[] = 
>> > {
>> >   */
>> >  static const struct gen_l3_config icl_l3_configs[] = {
>> > /* SLM URB ALL DC  RO  IS   C   T */
>> > -   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
>> > -   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
>> > -   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
>> > -   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
>> > -   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
>> > -   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
>> > +   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
>> 
>> This configuration is inherently inefficient since it will always leave
>> a third of the L3 cache unallocated.  According to the hardware docs
>> it's only included for backwards compatibility.  I think we should
>> remove it so we don't end up using it accidentally.
>> 
>> > +   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
>> > +   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
>> > +   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
>> > +   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
>> > +   {{  0, 16,  0,  0, 12,  0,  0,  0 }},
>> 
>> The configurations above won't work right now because we aren't setting
>> up the command buffer and tile cache-related partitions in the L3
>> control registers.  You either need to hook up the new partitions (and
>> add array entries for them in gen_l3_config), or remove/comment out the
>> five lines above.
>> 
>> > +   {{  0, 16, 80,  0,  0,  0,  0,  0 }},
>> 
>> From the results of the experiments we ran it seems like the last
>> configuration above is busted due to some hardware bug.  It would make
>> sense to remove or at least comment out the line so we don't use it
>> accidentally until we get some better workaround from the hardware team.
>> 
>> > +   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
>> > +   {{  0, 16, 44,  0,  0,  0,  0,  0 }},
>> 
>> As before the above two configurations won't work due to the missing
>> partitions introduced in ICL.  With these changes in place there's
>> probably no need for PATCH 4 of this series.
>> 
>> > +   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
>> > {{  0 }}
>> >  };
>> >  
>> 
>
> So, one of the main motivations for dynamically reconfiguring the L3
> on the fly was to add/remove the SLM partition as needed.  This isn't
> required on Gen11+, as SLM is handled separately.  Furthermore, we just
> use the "ALL" configs rather than manually partitioning things between
> DC, RO, and so on.
>
> With that in mind, it seems like we basically always want to use the
> last config (32/64) - or maybe the smaller URB one (16/80).  I am not
> sure that we really need the ability to dynamically switch on the fly.
>

There's no optimal choice between the two beforehand, that's why the
hardware still provides the ability to reconfigure the L3 cache.
Different workloads can benefit from different ratios of URB to the rest
of the cache based on how bandwidth and geometry intensive they are.

> I had suggested to Anuj earlier to make brw_upload_initial_gpu_state()
> program one of the two configs directly, then remove the gen7_l3_state
> atom from the Gen11+ list.  We'd bypass all of this code entirely.  No
> more lists of things we don't want, with manipulated weights to pick the
> one thing we do want, and draw-time state flagging to re-select the same
> config every time...
>
> It seems like it would be dramatically simpler.  This code is great for
> Gen7+, I just don't think it makes sense for Gen11+.
>
> Curro, what do you think?
>

It definitely still makes sense on Gen11+ AFAICT.  And we may still need
to switch L3 partitions on the fly because of everybody's favorite ICL
performance hardware feature.  I doubt that making the allocation static
is a good plan.  What is your concern exactly?  Does it show up in your
profiling logs at all?

> --Ken


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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Kenneth Graunke]

On Thursday, November 15, 2018 5:51:18 PM PST Francisco Jerez wrote:
> Anuj Phogat  writes:
> 
> > Use L3 configuration table specified in h/w specification.
> >
> > Signed-off-by: Anuj Phogat 
> > Cc: Kenneth Graunke 
> > Cc: Francisco Jerez 
> > Cc: Lionel Landwerlin 
> > ---
> >  src/intel/common/gen_l3_config.c | 16 ++--
> >  1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/src/intel/common/gen_l3_config.c 
> > b/src/intel/common/gen_l3_config.c
> > index b977c6ab136..079608198bc 100644
> > --- a/src/intel/common/gen_l3_config.c
> > +++ b/src/intel/common/gen_l3_config.c
> > @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[] = {
> >   */
> >  static const struct gen_l3_config icl_l3_configs[] = {
> > /* SLM URB ALL DC  RO  IS   C   T */
> > -   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
> > -   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
> > -   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
> > -   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
> > -   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
> > -   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
> > +   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
> 
> This configuration is inherently inefficient since it will always leave
> a third of the L3 cache unallocated.  According to the hardware docs
> it's only included for backwards compatibility.  I think we should
> remove it so we don't end up using it accidentally.
> 
> > +   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
> > +   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
> > +   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 12,  0,  0,  0 }},
> 
> The configurations above won't work right now because we aren't setting
> up the command buffer and tile cache-related partitions in the L3
> control registers.  You either need to hook up the new partitions (and
> add array entries for them in gen_l3_config), or remove/comment out the
> five lines above.
> 
> > +   {{  0, 16, 80,  0,  0,  0,  0,  0 }},
> 
> From the results of the experiments we ran it seems like the last
> configuration above is busted due to some hardware bug.  It would make
> sense to remove or at least comment out the line so we don't use it
> accidentally until we get some better workaround from the hardware team.
> 
> > +   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16, 44,  0,  0,  0,  0,  0 }},
> 
> As before the above two configurations won't work due to the missing
> partitions introduced in ICL.  With these changes in place there's
> probably no need for PATCH 4 of this series.
> 
> > +   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
> > {{  0 }}
> >  };
> >  
> 

So, one of the main motivations for dynamically reconfiguring the L3
on the fly was to add/remove the SLM partition as needed.  This isn't
required on Gen11+, as SLM is handled separately.  Furthermore, we just
use the "ALL" configs rather than manually partitioning things between
DC, RO, and so on.

With that in mind, it seems like we basically always want to use the
last config (32/64) - or maybe the smaller URB one (16/80).  I am not
sure that we really need the ability to dynamically switch on the fly.

I had suggested to Anuj earlier to make brw_upload_initial_gpu_state()
program one of the two configs directly, then remove the gen7_l3_state
atom from the Gen11+ list.  We'd bypass all of this code entirely.  No
more lists of things we don't want, with manipulated weights to pick the
one thing we do want, and draw-time state flagging to re-select the same
config every time...

It seems like it would be dramatically simpler.  This code is great for
Gen7+, I just don't think it makes sense for Gen11+.

Curro, what do you think?

--Ken


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[Mesa-dev] [PATCH] egl: Print the actual message to the console from _eglError().

[Eric Anholt]

Previously we would print errors on the console like:

   libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitialize

When we had everything we needed for:

   libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitialize: 
DRI2: failed to find EGLDevice

(for a gbm error in my case)
---
 src/egl/main/eglcurrent.c | 32 
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/src/egl/main/eglcurrent.c b/src/egl/main/eglcurrent.c
index 7af3011b7576..479f231fb8f6 100644
--- a/src/egl/main/eglcurrent.c
+++ b/src/egl/main/eglcurrent.c
@@ -310,20 +310,28 @@ _eglDebugReport(EGLenum error, const char *funcName,
 
mtx_unlock(_eglGlobal.Mutex);
 
-   if (callback != NULL) {
-  char *buf = NULL;
+   char *message_buf = NULL;
+   if (message != NULL) {
+  va_start(args, message);
+  if (vasprintf(_buf, message, args) < 0)
+ message_buf = NULL;
+  va_end(args);
+   }
 
-  if (message != NULL) {
- va_start(args, message);
- if (vasprintf(, message, args) < 0)
-buf = NULL;
+   if (callback != NULL) {
+  callback(error, funcName, type, thr->Label, thr->CurrentObjectLabel,
+   message_buf);
+   }
 
- va_end(args);
+   if (type == EGL_DEBUG_MSG_CRITICAL_KHR || type == EGL_DEBUG_MSG_ERROR_KHR) {
+  char *func_message_buf = NULL;
+  /* Note: _eglError() is often called with msg == thr->currentFuncName */
+  if (message_buf && funcName && strcmp(message_buf, funcName) != 0) {
+ if (asprintf(_message_buf, "%s: %s", funcName, message_buf) < 0)
+func_message_buf = NULL;
   }
-  callback(error, funcName, type, thr->Label, thr->CurrentObjectLabel, 
buf);
-  free(buf);
+  _eglInternalError(error, func_message_buf ? func_message_buf : funcName);
+  free(func_message_buf);
}
-
-   if (type == EGL_DEBUG_MSG_CRITICAL_KHR || type == EGL_DEBUG_MSG_ERROR_KHR)
-  _eglInternalError(error, funcName);
+   free(message_buf);
 }
-- 
2.19.1

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Re: [Mesa-dev] [PATCH v4] i965: Fix calculation of layers array length for isl_view

[Jason Ekstrand]

Pushed.

On Thu, Nov 15, 2018 at 8:15 PM Jason Ekstrand  wrote:

> Thanks.  I'm going to push it once it gets done running through CI.
>
> On Thu, Nov 15, 2018 at 4:03 AM Danylo Piliaiev 
> wrote:
>
>> Handle all cases in calculation of layers count for isl_view
>> taking into account texture view and image unit.
>> st_convert_image was taken as a reference.
>>
>> When u->Layered is true the whole level is taken with respect to
>> image view. In other case only one layer is taken.
>>
>> v3: (Józef Kucia and Ilia Mirkin)
>> - Rewrote patch by taking st_convert_image as a reference
>> - Removed now unused get_image_num_layers function
>> - Changed commit message
>>
>> v4: (Jason Ekstrand)
>> - Added assert
>>
>> Fixes: 5a8c8903
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856
>>
>> Signed-off-by: Danylo Piliaiev 
>> Reviewed-by: Jason Ekstrand 
>> ---
>>  .../drivers/dri/i965/brw_wm_surface_state.c   | 33 ++-
>>  1 file changed, 18 insertions(+), 15 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> index 8d21cf5fa7..3286c222e5 100644
>> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> @@ -1499,18 +1499,6 @@ update_buffer_image_param(struct brw_context *brw,
>> param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
>>  }
>>
>> -static unsigned
>> -get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
>> - unsigned level)
>> -{
>> -   if (target == GL_TEXTURE_CUBE_MAP)
>> -  return 6;
>> -
>> -   return target == GL_TEXTURE_3D ?
>> -  minify(mt->surf.logical_level0_px.depth, level) :
>> -  mt->surf.logical_level0_px.array_len;
>> -}
>> -
>>  static void
>>  update_image_surface(struct brw_context *brw,
>>   struct gl_image_unit *u,
>> @@ -1541,14 +1529,29 @@ update_image_surface(struct brw_context *brw,
>>} else {
>>   struct intel_texture_object *intel_obj =
>> intel_texture_object(obj);
>>   struct intel_mipmap_tree *mt = intel_obj->mt;
>> - const unsigned num_layers = u->Layered ?
>> -get_image_num_layers(mt, obj->Target, u->Level) : 1;
>> +
>> + unsigned base_layer, num_layers;
>> + if (u->Layered) {
>> +if (obj->Target == GL_TEXTURE_3D) {
>> +   base_layer = 0;
>> +   num_layers = minify(mt->surf.logical_level0_px.depth,
>> u->Level);
>> +} else {
>> +   assert(obj->Immutable || obj->MinLayer == 0);
>> +   base_layer = obj->MinLayer;
>> +   num_layers = obj->Immutable ?
>> +obj->NumLayers :
>> +mt->surf.logical_level0_px.array_len;
>> +}
>> + } else {
>> +base_layer = obj->MinLayer + u->_Layer;
>> +num_layers = 1;
>> + }
>>
>>   struct isl_view view = {
>>  .format = format,
>>  .base_level = obj->MinLevel + u->Level,
>>  .levels = 1,
>> -.base_array_layer = obj->MinLayer + u->_Layer,
>> +.base_array_layer = base_layer,
>>  .array_len = num_layers,
>>  .swizzle = ISL_SWIZZLE_IDENTITY,
>>  .usage = ISL_SURF_USAGE_STORAGE_BIT,
>> --
>> 2.18.0
>>
>>
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[Mesa-dev] [PATCH] intel, nir: Move gl_LocalInvocationID lowering to nir_lower_system_values

[Jason Ekstrand]

It's not at all intel-specific; the formula is dictated by OpenGL and
Vulkan.  The only intel-specific thing is that we need the lowering.  As
a nice side-effect, the new version is variable-group-size ready.

Cc: Plamena Manolova 
---
 src/compiler/nir/nir.h|  1 +
 src/compiler/nir/nir_lower_system_values.c| 49 ++-
 src/intel/compiler/brw_compiler.c |  1 +
 .../compiler/brw_nir_lower_cs_intrinsics.c| 33 -
 4 files changed, 50 insertions(+), 34 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index b0cff50eaf2..1dd605010f6 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2178,6 +2178,7 @@ typedef struct nir_shader_compiler_options {
bool lower_helper_invocation;
 
bool lower_cs_local_index_from_id;
+   bool lower_cs_local_id_from_index;
 
bool lower_device_index_to_zero;
 
diff --git a/src/compiler/nir/nir_lower_system_values.c 
b/src/compiler/nir/nir_lower_system_values.c
index fbc40573579..08a9e8be44a 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -51,6 +51,45 @@ build_local_group_size(nir_builder *b)
return local_size;
 }
 
+static nir_ssa_def *
+build_local_invocation_id(nir_builder *b)
+{
+   if (b->shader->options->lower_cs_local_id_from_index) {
+  /* We lower gl_LocalInvocationID from gl_LocalInvocationIndex based
+   * on this formula:
+   *
+   *gl_LocalInvocationID.x =
+   *   gl_LocalInvocationIndex % gl_WorkGroupSize.x;
+   *gl_LocalInvocationID.y =
+   *   (gl_LocalInvocationIndex / gl_WorkGroupSize.x) %
+   *   gl_WorkGroupSize.y;
+   *gl_LocalInvocationID.z =
+   *   (gl_LocalInvocationIndex /
+   *(gl_WorkGroupSize.x * gl_WorkGroupSize.y)) %
+   *   gl_WorkGroupSize.z;
+   *
+   * However, the final % gl_WorkGroupSize.z does nothing unless we
+   * accidentally end up with a gl_LocalInvocationIndex that is too
+   * large so it can safely be omitted.
+   */
+  nir_ssa_def *local_index = nir_load_local_invocation_index(b);
+  nir_ssa_def *local_size = build_local_group_size(b);
+
+  nir_ssa_def *id_x, *id_y, *id_z;
+  id_x = nir_umod(b, local_index,
+ nir_channel(b, local_size, 0));
+  id_y = nir_umod(b, nir_udiv(b, local_index,
+ nir_channel(b, local_size, 0)),
+ nir_channel(b, local_size, 1));
+  id_z = nir_udiv(b, local_index,
+ nir_imul(b, nir_channel(b, local_size, 0),
+ nir_channel(b, local_size, 1)));
+  return nir_vec3(b, id_x, id_y, id_z);
+   } else {
+  return nir_load_local_invocation_id(b);
+   }
+}
+
 static bool
 convert_block(nir_block *block, nir_builder *b)
 {
@@ -91,7 +130,7 @@ convert_block(nir_block *block, nir_builder *b)
   */
  nir_ssa_def *group_size = build_local_group_size(b);
  nir_ssa_def *group_id = nir_load_work_group_id(b);
- nir_ssa_def *local_id = nir_load_local_invocation_id(b);
+ nir_ssa_def *local_id = build_local_invocation_id(b);
 
  sysval = nir_iadd(b, nir_imul(b, group_id, group_size), local_id);
  break;
@@ -126,6 +165,14 @@ convert_block(nir_block *block, nir_builder *b)
  break;
   }
 
+  case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
+ /* If lower_cs_local_id_from_index is true, then we derive the local
+  * index from the local id.
+  */
+ if (b->shader->options->lower_cs_local_id_from_index)
+sysval = build_local_invocation_id(b);
+ break;
+
   case SYSTEM_VALUE_LOCAL_GROUP_SIZE: {
  sysval = build_local_group_size(b);
  break;
diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index e863b08b991..fe632c5badc 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -42,6 +42,7 @@
.lower_fdiv = true,\
.lower_flrp64 = true,  \
.lower_ldexp = true,   \
+   .lower_cs_local_id_from_index = true,  \
.lower_device_index_to_zero = true,\
.native_integers = true,   \
.use_interpolated_input_intrinsics = true, \
diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c 
b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
index bfbdea0e8fa..fab5edc893f 100644
--- a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
+++ b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
@@ -70,39 +70,6 @@ lower_cs_intrinsics_convert_block(struct 
lower_intrinsics_state 

Re: [Mesa-dev] [PATCH v4] i965: Fix calculation of layers array length for isl_view

[Jason Ekstrand]

Thanks.  I'm going to push it once it gets done running through CI.

On Thu, Nov 15, 2018 at 4:03 AM Danylo Piliaiev 
wrote:

> Handle all cases in calculation of layers count for isl_view
> taking into account texture view and image unit.
> st_convert_image was taken as a reference.
>
> When u->Layered is true the whole level is taken with respect to
> image view. In other case only one layer is taken.
>
> v3: (Józef Kucia and Ilia Mirkin)
> - Rewrote patch by taking st_convert_image as a reference
> - Removed now unused get_image_num_layers function
> - Changed commit message
>
> v4: (Jason Ekstrand)
> - Added assert
>
> Fixes: 5a8c8903
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856
>
> Signed-off-by: Danylo Piliaiev 
> Reviewed-by: Jason Ekstrand 
> ---
>  .../drivers/dri/i965/brw_wm_surface_state.c   | 33 ++-
>  1 file changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 8d21cf5fa7..3286c222e5 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1499,18 +1499,6 @@ update_buffer_image_param(struct brw_context *brw,
> param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
>  }
>
> -static unsigned
> -get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
> - unsigned level)
> -{
> -   if (target == GL_TEXTURE_CUBE_MAP)
> -  return 6;
> -
> -   return target == GL_TEXTURE_3D ?
> -  minify(mt->surf.logical_level0_px.depth, level) :
> -  mt->surf.logical_level0_px.array_len;
> -}
> -
>  static void
>  update_image_surface(struct brw_context *brw,
>   struct gl_image_unit *u,
> @@ -1541,14 +1529,29 @@ update_image_surface(struct brw_context *brw,
>} else {
>   struct intel_texture_object *intel_obj =
> intel_texture_object(obj);
>   struct intel_mipmap_tree *mt = intel_obj->mt;
> - const unsigned num_layers = u->Layered ?
> -get_image_num_layers(mt, obj->Target, u->Level) : 1;
> +
> + unsigned base_layer, num_layers;
> + if (u->Layered) {
> +if (obj->Target == GL_TEXTURE_3D) {
> +   base_layer = 0;
> +   num_layers = minify(mt->surf.logical_level0_px.depth,
> u->Level);
> +} else {
> +   assert(obj->Immutable || obj->MinLayer == 0);
> +   base_layer = obj->MinLayer;
> +   num_layers = obj->Immutable ?
> +obj->NumLayers :
> +mt->surf.logical_level0_px.array_len;
> +}
> + } else {
> +base_layer = obj->MinLayer + u->_Layer;
> +num_layers = 1;
> + }
>
>   struct isl_view view = {
>  .format = format,
>  .base_level = obj->MinLevel + u->Level,
>  .levels = 1,
> -.base_array_layer = obj->MinLayer + u->_Layer,
> +.base_array_layer = base_layer,
>  .array_len = num_layers,
>  .swizzle = ISL_SWIZZLE_IDENTITY,
>  .usage = ISL_SURF_USAGE_STORAGE_BIT,
> --
> 2.18.0
>
>
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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Francisco Jerez]

Anuj Phogat  writes:

> Use L3 configuration table specified in h/w specification.
>
> Signed-off-by: Anuj Phogat 
> Cc: Kenneth Graunke 
> Cc: Francisco Jerez 
> Cc: Lionel Landwerlin 
> ---
>  src/intel/common/gen_l3_config.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/common/gen_l3_config.c 
> b/src/intel/common/gen_l3_config.c
> index b977c6ab136..079608198bc 100644
> --- a/src/intel/common/gen_l3_config.c
> +++ b/src/intel/common/gen_l3_config.c
> @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[] = {
>   */
>  static const struct gen_l3_config icl_l3_configs[] = {
> /* SLM URB ALL DC  RO  IS   C   T */
> -   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
> -   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
> -   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
> -   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
> -   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
> -   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
> +   {{  0, 32, 32,  0,  0,  0,  0,  0 }},

This configuration is inherently inefficient since it will always leave
a third of the L3 cache unallocated.  According to the hardware docs
it's only included for backwards compatibility.  I think we should
remove it so we don't end up using it accidentally.

> +   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
> +   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
> +   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
> +   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
> +   {{  0, 16,  0,  0, 12,  0,  0,  0 }},

The configurations above won't work right now because we aren't setting
up the command buffer and tile cache-related partitions in the L3
control registers.  You either need to hook up the new partitions (and
add array entries for them in gen_l3_config), or remove/comment out the
five lines above.

> +   {{  0, 16, 80,  0,  0,  0,  0,  0 }},

From the results of the experiments we ran it seems like the last
configuration above is busted due to some hardware bug.  It would make
sense to remove or at least comment out the line so we don't use it
accidentally until we get some better workaround from the hardware team.

> +   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
> +   {{  0, 16, 44,  0,  0,  0,  0,  0 }},

As before the above two configurations won't work due to the missing
partitions introduced in ICL.  With these changes in place there's
probably no need for PATCH 4 of this series.

> +   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
> {{  0 }}
>  };
>  
> -- 
> 2.17.1


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[Mesa-dev] [PATCH 4/5] loader: Stop using a local definition for an in-tree header

[Eric Anholt]

I need other types from the header now, and "gl.h is big" is not a good
reason to duplicate definitions.
---
 src/loader/loader.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/src/loader/loader.c b/src/loader/loader.c
index 461f96aa6a44..041a59212be7 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -41,6 +41,8 @@
 #ifdef MAJOR_IN_SYSMACROS
 #include 
 #endif
+#include 
+#include 
 #include "loader.h"
 
 #ifdef HAVE_LIBDRM
@@ -492,14 +494,6 @@ loader_set_logger(void (*logger)(int level, const char 
*fmt, ...))
log_ = logger;
 }
 
-/* XXX: Local definition to avoid pulling the heavyweight GL/gl.h and
- * GL/internal/dri_interface.h
- */
-
-#ifndef __DRI_DRIVER_GET_EXTENSIONS
-#define __DRI_DRIVER_GET_EXTENSIONS "__driDriverGetExtensions"
-#endif
-
 char *
 loader_get_extensions_name(const char *driver_name)
 {
-- 
2.19.1

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[Mesa-dev] [PATCH 3/5] egl: Move loader_set_logger() up to egl_dri2.c.

[Eric Anholt]

Everyone needs to call it, and platform_x11 forgot to.
---
 src/egl/drivers/dri2/egl_dri2.c | 2 ++
 src/egl/drivers/dri2/platform_android.c | 2 --
 src/egl/drivers/dri2/platform_drm.c | 2 --
 src/egl/drivers/dri2/platform_surfaceless.c | 2 --
 src/egl/drivers/dri2/platform_wayland.c | 4 
 5 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 3b63aebbf9a2..f05c39126c85 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -900,6 +900,8 @@ dri2_initialize(_EGLDriver *drv, _EGLDisplay *disp)
   return EGL_TRUE;
}
 
+   loader_set_logger(_eglLog);
+
switch (disp->Platform) {
case _EGL_PLATFORM_SURFACELESS:
   ret = dri2_initialize_surfaceless(drv, disp);
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index b3ef55896116..366a9ec14e98 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1536,8 +1536,6 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*disp)
if (disp->Options.ForceSoftware)
   return EGL_FALSE;
 
-   loader_set_logger(_eglLog);
-
dri2_dpy = calloc(1, sizeof(*dri2_dpy));
if (!dri2_dpy)
   return _eglError(EGL_BAD_ALLOC, "eglInitialize");
diff --git a/src/egl/drivers/dri2/platform_drm.c 
b/src/egl/drivers/dri2/platform_drm.c
index fb346e007332..c1ab1c9b0f6e 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -704,8 +704,6 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
if (disp->Options.ForceSoftware)
   return EGL_FALSE;
 
-   loader_set_logger(_eglLog);
-
dri2_dpy = calloc(1, sizeof *dri2_dpy);
if (!dri2_dpy)
   return _eglError(EGL_BAD_ALLOC, "eglInitialize");
diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index 1edfca246dbd..f98095616115 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -350,8 +350,6 @@ dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay 
*disp)
const char* err;
bool driver_loaded = false;
 
-   loader_set_logger(_eglLog);
-
dri2_dpy = calloc(1, sizeof *dri2_dpy);
if (!dri2_dpy)
   return _eglError(EGL_BAD_ALLOC, "eglInitialize");
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index dc16a69dfbc2..8122c8112887 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1323,8 +1323,6 @@ dri2_initialize_wayland_drm(_EGLDriver *drv, _EGLDisplay 
*disp)
_EGLDevice *dev;
struct dri2_egl_display *dri2_dpy;
 
-   loader_set_logger(_eglLog);
-
dri2_dpy = calloc(1, sizeof *dri2_dpy);
if (!dri2_dpy)
   return _eglError(EGL_BAD_ALLOC, "eglInitialize");
@@ -1986,8 +1984,6 @@ dri2_initialize_wayland_swrast(_EGLDriver *drv, 
_EGLDisplay *disp)
_EGLDevice *dev;
struct dri2_egl_display *dri2_dpy;
 
-   loader_set_logger(_eglLog);
-
dri2_dpy = calloc(1, sizeof *dri2_dpy);
if (!dri2_dpy)
   return _eglError(EGL_BAD_ALLOC, "eglInitialize");
-- 
2.19.1

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[Mesa-dev] [PATCH 1/5] glx: Remove an old DEFAULT_DRIVER_DIR default.

[Eric Anholt]

You can tell by "Mesa/configs/default" how old this is.  Your build system
really has to provide the DEFAULT_DRIVER_DIR, or other loaders will break.
---
 src/glx/dri_common.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index ab5d6c5bc03d..08923d7efd55 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -77,11 +77,6 @@ dri_message(int level, const char *f, ...)
 #define GL_LIB_NAME "libGL.so.1"
 #endif
 
-#ifndef DEFAULT_DRIVER_DIR
-/* this is normally defined in Mesa/configs/default with 
DRI_DRIVER_SEARCH_PATH */
-#define DEFAULT_DRIVER_DIR "/usr/local/lib/dri"
-#endif
-
 /**
  * Try to \c dlopen the named driver.
  *
-- 
2.19.1

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[Mesa-dev] [PATCH 5/5] loader: Factor out the common driver opening logic from each loader.

[Eric Anholt]

I copied the code from egl_dri2.c, but the functionality was equivalent
between all the loaders other than their particular environment variables.
---
 src/egl/Makefile.am |  3 +-
 src/egl/drivers/dri2/egl_dri2.c | 75 +++---
 src/egl/meson.build |  3 --
 src/gbm/Makefile.am |  1 -
 src/gbm/backends/dri/gbm_dri.c  | 96 +
 src/gbm/meson.build |  1 -
 src/glx/Makefile.am |  1 -
 src/glx/SConscript  |  1 -
 src/glx/dri_common.c| 91 +++
 src/glx/meson.build |  1 -
 src/loader/Makefile.am  |  1 +
 src/loader/loader.c | 90 +++
 src/loader/loader.h |  7 +++
 src/loader/meson.build  |  4 +-
 14 files changed, 142 insertions(+), 233 deletions(-)

diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 24a8e96a8e1e..7269912d96f3 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -119,8 +119,7 @@ AM_CFLAGS += \
-I$(top_srcdir)/src/egl/drivers/dri2 \
-I$(top_srcdir)/src/gbm/backends/dri \
-I$(top_builddir)/src/egl/wayland/wayland-drm \
-   -I$(top_srcdir)/src/egl/wayland/wayland-drm \
-   -DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\"
+   -I$(top_srcdir)/src/egl/wayland/wayland-drm
 
 nodist_libEGL_common_la_SOURCES = \
$(dri2_backend_GENERATED_FILES)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f05c39126c85..f998655d2ae0 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -483,75 +483,14 @@ static const __DRIextension **
 dri2_open_driver(_EGLDisplay *disp)
 {
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
-   const __DRIextension **extensions = NULL;
-   char path[PATH_MAX], *search_paths, *next, *end;
-   char *get_extensions_name;
-   const __DRIextension **(*get_extensions)(void);
-
-   search_paths = NULL;
-   if (geteuid() == getuid()) {
-  /* don't allow setuid apps to use LIBGL_DRIVERS_PATH */
-  search_paths = getenv("LIBGL_DRIVERS_PATH");
-   }
-   if (search_paths == NULL)
-  search_paths = DEFAULT_DRIVER_DIR;
-
-   dri2_dpy->driver = NULL;
-   end = search_paths + strlen(search_paths);
-   for (char *p = search_paths; p < end; p = next + 1) {
-  int len;
-  next = strchr(p, ':');
-  if (next == NULL)
- next = end;
-
-  len = next - p;
-#if GLX_USE_TLS
-  snprintf(path, sizeof path,
-   "%.*s/tls/%s_dri.so", len, p, dri2_dpy->driver_name);
-  dri2_dpy->driver = dlopen(path, RTLD_NOW | RTLD_GLOBAL);
-#endif
-  if (dri2_dpy->driver == NULL) {
- snprintf(path, sizeof path,
-  "%.*s/%s_dri.so", len, p, dri2_dpy->driver_name);
- dri2_dpy->driver = dlopen(path, RTLD_NOW | RTLD_GLOBAL);
- if (dri2_dpy->driver == NULL)
-_eglLog(_EGL_DEBUG, "failed to open %s: %s\n", path, dlerror());
-  }
-  /* not need continue to loop all paths once the driver is found */
-  if (dri2_dpy->driver != NULL)
- break;
-   }
-
-   if (dri2_dpy->driver == NULL) {
-  _eglLog(_EGL_WARNING,
-  "DRI2: failed to open %s (search paths %s)",
-  dri2_dpy->driver_name, search_paths);
-  return NULL;
-   }
-
-   _eglLog(_EGL_DEBUG, "DRI2: dlopen(%s)", path);
-
-   get_extensions_name = loader_get_extensions_name(dri2_dpy->driver_name);
-   if (get_extensions_name) {
-  get_extensions = dlsym(dri2_dpy->driver, get_extensions_name);
-  if (get_extensions) {
- extensions = get_extensions();
-  } else {
- _eglLog(_EGL_DEBUG, "driver does not expose %s(): %s\n",
- get_extensions_name, dlerror());
-  }
-  free(get_extensions_name);
-   }
-
-   if (!extensions)
-  extensions = dlsym(dri2_dpy->driver, __DRI_DRIVER_EXTENSIONS);
-   if (extensions == NULL) {
-  _eglLog(_EGL_WARNING,
-  "DRI2: driver exports no extensions (%s)", dlerror());
-  dlclose(dri2_dpy->driver);
-   }
+   static const char *search_path_vars[] = {
+  "LIBGL_DRIVERS_PATH",
+  NULL,
+   };
 
-   return extensions;
+   return loader_open_driver(dri2_dpy->driver_name,
+ _dpy->driver,
+ search_path_vars);
 }
 
 EGLBoolean
diff --git a/src/egl/meson.build b/src/egl/meson.build
index 8c0ffea8b40a..372842967d37 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -93,9 +93,6 @@ if with_dri2
 'drivers/dri2/egl_dri2.h',
 'drivers/dri2/egl_dri2_fallbacks.h',
   )
-  c_args_for_egl += [
-'-DDEFAULT_DRIVER_DIR="@0@"'.format(dri_search_path),
-  ]
 
   if with_platform_x11
 files_egl += files('drivers/dri2/platform_x11.c')
diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am
index 5097212cda0a..bb246ecebf52 100644
--- a/src/gbm/Makefile.am
+++ b/src/gbm/Makefile.am
@@ -42,7 +42,6 

[Mesa-dev] [PATCH 2/5] glx: Move DRI extensions pointer loading to driOpenDriver().

[Eric Anholt]

The only thing you do with a dri driver handle is get the extensions
pointer, so just fold it in to simplify the callers.
---
 src/glx/dri2_glx.c   |  8 +---
 src/glx/dri3_glx.c   |  8 +---
 src/glx/dri_common.c | 20 +++-
 src/glx/dri_common.h |  6 ++
 src/glx/dri_glx.c| 16 +++-
 src/glx/drisw_glx.c  | 17 +
 6 files changed, 23 insertions(+), 52 deletions(-)

diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 91afc3375058..d8c5ba25f04e 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1252,13 +1252,7 @@ dri2CreateScreen(int screen, struct glx_display * priv)
   driverName = loader_driverName;
}
 
-   psc->driver = driOpenDriver(driverName);
-   if (psc->driver == NULL) {
-  ErrorMessageF("driver pointer missing\n");
-  goto handle_error;
-   }
-
-   extensions = driGetDriverExtensions(psc->driver, driverName);
+   extensions = driOpenDriver(driverName, >driver);
if (extensions == NULL)
   goto handle_error;
 
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index ce60b95c71e3..298adc80ef16 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -861,13 +861,7 @@ dri3_create_screen(int screen, struct glx_display * priv)
   goto handle_error;
}
 
-   psc->driver = driOpenDriver(driverName);
-   if (psc->driver == NULL) {
-  ErrorMessageF("driver pointer missing\n");
-  goto handle_error;
-   }
-
-   extensions = driGetDriverExtensions(psc->driver, driverName);
+   extensions = driOpenDriver(driverName, >driver);
if (extensions == NULL)
   goto handle_error;
 
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 08923d7efd55..75a5e5025761 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -85,12 +85,14 @@ dri_message(int level, const char *f, ...)
  * order to find the driver.
  *
  * \param driverName - a name like "i965", "radeon", "nouveau", etc.
+ * \param out_driver_handle - Address to return the resulting dlopen() handle.
  *
  * \returns
- * A handle from \c dlopen, or \c NULL if driver file not found.
+ * The __DRIextension entrypoint table for the driver, or \c NULL if driver
+ * file not found.
  */
-_X_HIDDEN void *
-driOpenDriver(const char *driverName)
+_X_HIDDEN const __DRIextension **
+driOpenDriver(const char *driverName, void **out_driver_handle)
 {
void *glhandle, *handle;
const char *libPaths, *p, *next;
@@ -148,10 +150,18 @@ driOpenDriver(const char *driverName)
if (glhandle)
   dlclose(glhandle);
 
-   return handle;
+   const __DRIextension **extensions = driGetDriverExtensions(handle,
+  driverName);
+   if (!extensions) {
+  dlclose(handle);
+  handle = NULL;
+   }
+
+   *out_driver_handle = handle;
+   return extensions;
 }
 
-_X_HIDDEN const __DRIextension **
+static const __DRIextension **
 driGetDriverExtensions(void *handle, const char *driver_name)
 {
const __DRIextension **extensions = NULL;
diff --git a/src/glx/dri_common.h b/src/glx/dri_common.h
index 4d97ff82b4d1..363f15bf9bb2 100644
--- a/src/glx/dri_common.h
+++ b/src/glx/dri_common.h
@@ -69,10 +69,8 @@ extern void dri_message(int level, const char *f, ...) 
PRINTFLIKE(2, 3);
 #define ErrorMessageF(...) dri_message(_LOADER_WARNING, __VA_ARGS__)
 #define CriticalErrorMessageF(...) dri_message(_LOADER_FATAL, __VA_ARGS__)
 
-extern void *driOpenDriver(const char *driverName);
-
-extern const __DRIextension **
-driGetDriverExtensions(void *handle, const char *driver_name);
+extern const __DRIextension **driOpenDriver(const char *driverName,
+void **out_driver_handle);
 
 extern bool
 dri2_convert_glx_attribs(unsigned num_attribs, const uint32_t *attribs,
diff --git a/src/glx/dri_glx.c b/src/glx/dri_glx.c
index 5c4346cec0d8..6e9412d3fb17 100644
--- a/src/glx/dri_glx.c
+++ b/src/glx/dri_glx.c
@@ -199,15 +199,9 @@ clear_driver_config_cache()
 static char *
 get_driver_config(const char *driverName)
 {
-   void *handle = driOpenDriver(driverName);
-   const __DRIextension **extensions;
-
-   if (!handle)
-  return NULL;
-
+   void *handle;
char *config = NULL;
-
-   extensions = driGetDriverExtensions(handle, driverName);
+   const __DRIextension **extensions = driOpenDriver(driverName, );
if (extensions) {
   for (int i = 0; extensions[i]; i++) {
  if (strcmp(extensions[i]->name, __DRI_CONFIG_OPTIONS) != 0)
@@ -918,11 +912,7 @@ driCreateScreen(int screen, struct glx_display *priv)
   goto cleanup;
}
 
-   psc->driver = driOpenDriver(driverName);
-   if (psc->driver == NULL)
-  goto cleanup;
-
-   extensions = dlsym(psc->driver, __DRI_DRIVER_EXTENSIONS);
+   extensions = driOpenDriver(driverName, >driver);
if (extensions == NULL) {
   ErrorMessageF("driver exports no extensions (%s)\n", dlerror());
   goto cleanup;
diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index 

Re: [Mesa-dev] [PATCH] egl/dri: fix error value with unknown drm format

[Chad Versace]

On Wed 14 Nov 2018, Eric Engestrom wrote:
> On Tuesday, 2018-11-13 14:10:45 +, Lionel Landwerlin wrote:
> > According to the EGL_EXT_image_dma_buf_import spec, creating an EGL
> > image with a DRM format not supported should yield the BAD_MATCH
> > error :
> > 
> > "
> >* If  is EGL_LINUX_DMA_BUF_EXT, and the 
> > EGL_LINUX_DRM_FOURCC_EXT
> >  attribute is set to a format not supported by the EGL, 
> > EGL_BAD_MATCH
> >  is generated.
> > "
> > 
> > Signed-off-by: Lionel Landwerlin 
> > Fixes: 20de7f9f226401 ("egl/dri2: support for creating images out of dma 
> > buffers")
> 
> That matches the spec, so:
> Reviewed-by: Eric Engestrom 
> 
> That said, Topi specifically wrote this, in his commit (20de7f9f226401):
> > v4 (Chad):
> >- in case of invalid format report EGL_BAD_ATTRIBUTE instead
> >  of EGL_BAD_MATCH
> 
> So cc'ing them both so they can mention if they had a need for this?

Huh... I don't recall why I suggested EGL_BAD_ATTRIBUTE. But this patch
matches the spec.

Reviewed-by: Chad Versace 
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[Mesa-dev] [PATCH] intel/compiler: Always print flag subregister number

[Sagar Ghuge]

While disassembling the predicate always print flag subregister number
to keep grammar same across the generation for assembler tool.

Signed-off-by: Sagar Ghuge 
---
 src/intel/compiler/brw_disasm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 6c79fec0a1..a218e1451c 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1486,8 +1486,7 @@ brw_disassemble_inst(FILE *file, const struct 
gen_device_info *devinfo,
   err |= control(file, "predicate inverse", pred_inv,
  brw_inst_pred_inv(devinfo, inst), NULL);
   format(file, "f%"PRIu64, devinfo->gen >= 7 ? 
brw_inst_flag_reg_nr(devinfo, inst) : 0);
-  if (brw_inst_flag_subreg_nr(devinfo, inst))
- format(file, ".%"PRIu64, brw_inst_flag_subreg_nr(devinfo, inst));
+  format(file, ".%"PRIu64, brw_inst_flag_subreg_nr(devinfo, inst));
   if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
  err |= control(file, "predicate control align1", pred_ctrl_align1,
 brw_inst_pred_control(devinfo, inst), NULL);
-- 
2.17.1

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[Mesa-dev] [PATCH] nir: small tidy ups for nir_loop_analyze()

[Timothy Arceri]

---
 src/compiler/nir/nir_loop_analyze.c | 31 ++---
 1 file changed, 10 insertions(+), 21 deletions(-)

diff --git a/src/compiler/nir/nir_loop_analyze.c 
b/src/compiler/nir/nir_loop_analyze.c
index 9c3fd2f286..c779383b36 100644
--- a/src/compiler/nir/nir_loop_analyze.c
+++ b/src/compiler/nir/nir_loop_analyze.c
@@ -624,8 +624,7 @@ find_trip_count(loop_info_state *state)
 }
 
 static bool
-force_unroll_array_access(loop_info_state *state, nir_shader *ns,
-  nir_deref_instr *deref)
+force_unroll_array_access(loop_info_state *state, nir_deref_instr *deref)
 {
for (nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d)) {
   if (d->deref_type != nir_deref_type_array)
@@ -640,23 +639,18 @@ force_unroll_array_access(loop_info_state *state, 
nir_shader *ns,
   nir_deref_instr *parent = nir_deref_instr_parent(d);
   assert(glsl_type_is_array(parent->type) ||
  glsl_type_is_matrix(parent->type));
-  if (glsl_get_length(parent->type) == state->loop->info->trip_count) {
- state->loop->info->force_unroll = true;
+  if (glsl_get_length(parent->type) == state->loop->info->trip_count)
  return true;
-  }
 
-  if (deref->mode & state->indirect_mask) {
- state->loop->info->force_unroll = true;
+  if (deref->mode & state->indirect_mask)
  return true;
-  }
}
 
return false;
 }
 
 static bool
-force_unroll_heuristics(loop_info_state *state, nir_shader *ns,
-nir_block *block)
+force_unroll_heuristics(loop_info_state *state, nir_block *block)
 {
nir_foreach_instr(instr, block) {
   if (instr->type != nir_instr_type_intrinsic)
@@ -670,12 +664,12 @@ force_unroll_heuristics(loop_info_state *state, 
nir_shader *ns,
   if (intrin->intrinsic == nir_intrinsic_load_deref ||
   intrin->intrinsic == nir_intrinsic_store_deref ||
   intrin->intrinsic == nir_intrinsic_copy_deref) {
- if (force_unroll_array_access(state, ns,
+ if (force_unroll_array_access(state,
nir_src_as_deref(intrin->src[0])))
 return true;
 
  if (intrin->intrinsic == nir_intrinsic_copy_deref &&
- force_unroll_array_access(state, ns,
+ force_unroll_array_access(state,
nir_src_as_deref(intrin->src[1])))
 return true;
   }
@@ -745,15 +739,10 @@ get_loop_info(loop_info_state *state, nir_function_impl 
*impl)
find_trip_count(state);
 
nir_shader *ns = impl->function->shader;
-   foreach_list_typed_safe(nir_cf_node, node, node, >loop->body) {
-  if (node->type == nir_cf_node_block) {
- if (force_unroll_heuristics(state, ns, nir_cf_node_as_block(node)))
-break;
-  } else {
- nir_foreach_block_in_cf_node(block, node) {
-if (force_unroll_heuristics(state, ns, block))
-   break;
- }
+   nir_foreach_block_in_cf_node(block, >loop->cf_node) {
+  if (force_unroll_heuristics(state, block)) {
+ state->loop->info->force_unroll = true;
+ break;
   }
}
 }
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] gbm: Clarify acceptable formats for gbm_bo

[Eric Anholt]

Daniel Stone  writes:

> gbm_bo_create() was presumably meant to originally accept gbm_bo_format
> enums, but it's accepted GBM_FORMAT_* tokens since the dawn of time.
> This is good, since gbm_bo_format is rarely used and covers a lot less
> ground than GBM_FORMAT_*.
>
> Change the documentation to refer to both; this involves removing a 'see
> also' for gbm_bo_format, since we can't also use \sa to refer to a
> family of anonymous #defines.
>
> Signed-off-by: Daniel Stone 
> Reported-by: Pekka Paalanen 

Reviewed-by: Eric Anholt 


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[Mesa-dev] [PATCH] vulkan: Add VK_GOOGLE_display_timing extension (x11+display, anv+radv) [v6]

[Keith Packard]

This adds support for the VK_GOOGLE_display timing extension, which
provides two things:

 1) Detailed information about when frames are displayed, including
slack time between GPU execution and display frame.

 2) Absolute time control over swapchain queue processing. This allows
the application to request frames be displayed at specific
absolute times, using the same timebase as that provided in vblank
events.

Support for this extension has been implemented for the x11 and
display backends; adding support to other backends should be
reasonable straightforward for one familiar with those systems and
should not require any additional device-specific code.

v2:
Adjust GOOGLE_display_timing earliest value.  The
earliestPresentTime for an image cannot be before the previous
image was displayed, or even a frame later (in FIFO mode).

Make GOOGLE_display_timing use render completed time.  Switch
from VK_PIPELINE_TOP_OF_PIPE_BIT to
VK_PIPELINE_STAGE_ALL_COMMANDS_BIT so that the time reported
to applications as the end of rendering reflects the latest
possible value to ensure that applications don't underestimate
the amount of work done in the frame.

v3:
Adopt Jason Ekstrand's coding conventions.  Declare variables
at first use, eliminate extra whitespace between types and
names. Wrap lines to 80 columns.

Suggested-by: Jason Ekstrand 

v4:
Adapt to changes in MESA_query_timestamp extension

v5:
Squash core bits and anv/radv wrappers into a single patch

Suggested-by: Jason Ekstrand 

v6:
Switch from MESA_query_timestamp to EXT_calibrated_timestamps

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py   |   1 +
 src/amd/vulkan/radv_wsi.c   |  33 +++
 src/intel/vulkan/anv_extensions.py  |   1 +
 src/intel/vulkan/anv_wsi.c  |  33 +++
 src/vulkan/wsi/wsi_common.c | 303 +++-
 src/vulkan/wsi/wsi_common.h |  32 +++
 src/vulkan/wsi/wsi_common_display.c | 165 ++-
 src/vulkan/wsi/wsi_common_private.h |  35 
 src/vulkan/wsi/wsi_common_x11.c |  71 ++-
 9 files changed, 662 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 6bdf988d117..76c3ade06f0 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -119,6 +119,7 @@ EXTENSIONS = [
 Extension('VK_AMD_shader_trinary_minmax', 1, True),
 Extension('VK_GOOGLE_decorate_string',1, True),
 Extension('VK_GOOGLE_hlsl_functionality1',1, True),
+Extension('VK_GOOGLE_display_timing', 1, True),
 ]
 
 class VkVersion:
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 346fb43d675..ba24d07edfc 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -295,3 +295,36 @@ VkResult radv_GetPhysicalDevicePresentRectanglesKHR(
 surface,
 pRectCount, pRects);
 }
+
+/* VK_GOOGLE_display_timing */
+VkResult
+radv_GetRefreshCycleDurationGOOGLE(
+   VkDevice _device,
+   VkSwapchainKHR swapchain,
+   VkRefreshCycleDurationGOOGLE *pDisplayTimingProperties)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   struct radv_physical_device *pdevice = device->physical_device;
+
+   return wsi_common_get_refresh_cycle_duration(>wsi_device,
+_device,
+swapchain,
+pDisplayTimingProperties);
+}
+
+VkResult
+radv_GetPastPresentationTimingGOOGLE(VkDevice _device,
+VkSwapchainKHR swapchain,
+uint32_t *pPresentationTimingCount,
+VkPastPresentationTimingGOOGLE
+*pPresentationTimings)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   struct radv_physical_device *pdevice = device->physical_device;
+
+   return wsi_common_get_past_presentation_timing(>wsi_device,
+  _device,
+  swapchain,
+  pPresentationTimingCount,
+  pPresentationTimings);
+}
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index e9afe06bb13..8fcc4d1376e 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -130,6 +130,7 @@ EXTENSIONS = [
 Extension('VK_EXT_calibrated_timestamps', 1, True),
 Extension('VK_GOOGLE_decorate_string',1, 

[Mesa-dev] [PATCH 4/4] i965: Add support for and expose EXT_texture_sRGB_R8

[Gert Wollny]

Emulate MESA_FORMAT_R_SRGB8 by using L8_UNORM_SRGB. This is possible
because component swizzling is handled based on the mesa format and,
hence, the a r001 swizzling can be used to correct the components.

Enables and makes pass (tested on Kabylake)

  dEQP-GLES31.functional.srgb_texture_decode.skip_decode.sr8.*
  dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8*

Signed-off-by: Gert Wollny 
---
 src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
 src/mesa/drivers/dri/i965/intel_extensions.c| 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 879cb42453..77476a8c7e 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -67,6 +67,7 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format)
   [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
   [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
   [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
+  [MESA_FORMAT_R_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
   [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
   [MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
   [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index d7e02efb54..6ec6248a70 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -113,6 +113,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_texture_snorm = true;
ctx->Extensions.EXT_texture_sRGB = true;
ctx->Extensions.EXT_texture_sRGB_decode = true;
+   ctx->Extensions.EXT_texture_sRGB_R8 = true;
ctx->Extensions.EXT_texture_swizzle = true;
ctx->Extensions.EXT_texture_type_2_10_10_10_REV = true;
ctx->Extensions.EXT_vertex_array_bgra = true;
-- 
2.19.1

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[Mesa-dev] [PATCH 0/4] i965: Add support for EXT_texture_sRGB_S8

[Gert Wollny]

Dear all, 

this series adds support for the GL_SR8_EXT texture format. When you review 
please take a closer look at the second patch, to see whether the fbo 
completeness states make sense. Always returning GL_FRAMEBUFFER_UNSUPPORTED 
makes dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.sr8_ext
fail because it expects GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT (which makes 
sense), but I thought when I touch this code, I could as well go through
the hole list.

Thanks for any reviews, 
Gert 

Gert Wollny (4):
  i965: Correct L8_UNORM_SRGB table entry
  i965: be more specific about FBO completeness errors
  i965: Force zero swizzles for unused components in GL_RED and GL_RG
  i965: Add support for and expose EXT_texture_sRGB_R8

 src/intel/isl/isl_format_layout.csv   |  2 +-
 .../drivers/dri/i965/brw_surface_formats.c|  1 +
 .../drivers/dri/i965/brw_wm_surface_state.c   |  4 ++
 src/mesa/drivers/dri/i965/intel_extensions.c  |  1 +
 src/mesa/drivers/dri/i965/intel_fbo.c | 42 ++-
 5 files changed, 30 insertions(+), 20 deletions(-)

-- 
2.19.1

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[Mesa-dev] [PATCH 3/4] i965: Force zero swizzles for unused components in GL_RED and GL_RG

[Gert Wollny]

This makes it possible to use a hardware luminance format as RED format.

Signed-off-by: Gert Wollny 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8d21cf5fa7..a9307beb36 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -420,7 +420,11 @@ brw_get_texture_swizzle(const struct gl_context *ctx,
   }
   break;
case GL_RED:
+  swizzles[1] = SWIZZLE_ZERO;
+  /* fallthrough */
case GL_RG:
+  swizzles[2] = SWIZZLE_ZERO;
+  /* fallthrough */
case GL_RGB:
   if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0 ||
   img->TexFormat == MESA_FORMAT_RGB_DXT1 ||
-- 
2.19.1

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[Mesa-dev] [PATCH 2/4] i965: be more specific about FBO completeness errors

[Gert Wollny]

The driver was returning GL_FRAMEBUFFER_UNSUPPORTED for all cases of an
incomplete fbo, be a bit more specific about this following the description
of glCheckFramebufferStatus.

This helps to keeps dEQP happy when adding EXT_texture_sRGB_R8 support.

Signed-off-by: Gert Wollny 
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 42 +++
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 2bbbc34114..d657fdf8e4 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -629,7 +629,7 @@ intel_render_texture(struct gl_context * ctx,
 }
 
 
-#define fbo_incomplete(fb, ...) do {  \
+#define fbo_incomplete(fb, error_id, ...) do { 
 \
   static GLuint msg_id = 0;   \
   if (unlikely(ctx->Const.ContextFlags & GL_CONTEXT_FLAG_DEBUG_BIT)) {\
  _mesa_gl_debug(ctx, _id, \
@@ -639,7 +639,7 @@ intel_render_texture(struct gl_context * ctx,
 __VA_ARGS__); \
   }   \
   DBG(__VA_ARGS__);   \
-  fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED;   \
+  fb->_Status = error_id; \
} while (0)
 
 /**
@@ -693,7 +693,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
  d_depth != s_depth ||
  depthRb->mt_level != stencilRb->mt_level ||
 depthRb->mt_layer != stencilRb->mt_layer) {
-   fbo_incomplete(fb,
+   fbo_incomplete(fb, GL_FRAMEBUFFER_INCOMPLETE_DIMENSIONS,
"FBO incomplete: depth and stencil must match in"
"width, height, depth, LOD and layer\n");
 }
@@ -705,7 +705,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
  */
 if (depthRb->mt_level != stencilRb->mt_level ||
 depthRb->mt_layer != stencilRb->mt_layer) {
-   fbo_incomplete(fb,
+   fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: depth image level/layer %d/%d != "
"stencil image %d/%d\n",
depthRb->mt_level,
@@ -715,13 +715,14 @@ intel_validate_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
 }
   } else {
 if (!brw->has_separate_stencil) {
-   fbo_incomplete(fb, "FBO incomplete: separate stencil "
-   "unsupported\n");
+   fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
+  "FBO incomplete: separate stencil unsupported\n");
 }
 if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
-   fbo_incomplete(fb, "FBO incomplete: separate stencil is %s "
-   "instead of S8\n",
-   _mesa_get_format_name(stencil_mt->format));
+   fbo_incomplete(fb, GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT,
+  "FBO incomplete: separate stencil is %s "
+  "instead of S8\n",
+  _mesa_get_format_name(stencil_mt->format));
 }
 if (devinfo->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) {
/* Before Gen7, separate depth and stencil buffers can be used
@@ -730,8 +731,8 @@ intel_validate_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
 * [DevSNB]: This field must be set to the same value (enabled
 * or disabled) as Hierarchical Depth Buffer Enable.
 */
-   fbo_incomplete(fb, "FBO incomplete: separate stencil "
-   "without HiZ\n");
+   fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
+  "FBO incomplete: separate stencil without HiZ\n");
 }
   }
}
@@ -749,29 +750,32 @@ intel_validate_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
*/
   rb = fb->Attachment[i].Renderbuffer;
   if (rb == NULL) {
-fbo_incomplete(fb, "FBO incomplete: attachment without "
-"renderbuffer\n");
+fbo_incomplete(fb, GL_FRAMEBUFFER_INCOMPLETE_MISSING_ATTACHMENT,
+   "FBO incomplete: attachment without "
+   "renderbuffer\n");
 continue;
   }
 
   if (fb->Attachment[i].Type == GL_TEXTURE) {
 if (rb->TexImage->Border) {
-   fbo_incomplete(fb, "FBO incomplete: texture with border\n");
+   fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
+  "FBO incomplete: texture with 

[Mesa-dev] [PATCH 1/4] i965: Correct L8_UNORM_SRGB table entry

[Gert Wollny]

As the name says, the format is an sRGB format.

Signed-off-by: Gert Wollny 
---
 src/intel/isl/isl_format_layout.csv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_format_layout.csv 
b/src/intel/isl/isl_format_layout.csv
index 0b9421e3f9..a1efa66657 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -211,7 +211,7 @@ A4P4_UNORM_PALETTE0 ,   8,  1,  1,  1, , ,  
   ,  un4, ,
 R8_SSCALED  ,   8,  1,  1,  1,  ss8, , , , ,   
  ,, r, linear,
 R8_USCALED  ,   8,  1,  1,  1,  us8, , , , ,   
  ,, r, linear,
 P8_UNORM_PALETTE0   ,   8,  1,  1,  1, , , , , ,   
  , un8, p, linear,
-L8_UNORM_SRGB   ,   8,  1,  1,  1, , , , ,  un8,   
  ,, l, linear,
+L8_UNORM_SRGB   ,   8,  1,  1,  1, , , , ,  un8,   
  ,, l,   srgb,
 P8_UNORM_PALETTE1   ,   8,  1,  1,  1, , , , , ,   
  , un8, p, linear,
 P4A4_UNORM_PALETTE1 ,   8,  1,  1,  1, , , ,  un4, ,   
  , un4,pa, linear,
 A4P4_UNORM_PALETTE1 ,   8,  1,  1,  1, , , ,  un4, ,   
  , un4,ap, linear,
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_sampler

[Matt Turner]

Reviewed-by: Matt Turner 

and pushed.
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Re: [Mesa-dev] [PATCH 08/14] util: env_var_as_unsigned() helper

[Eric Engestrom]

On Monday, 2018-11-12 10:50:52 -0500, Rob Clark wrote:
> So I can drop env2u() helper from freedreno_util.h and get rid of one
> small ir3 dependency on gallium/freedreno
> 
> Signed-off-by: Rob Clark 
> ---
>  src/util/debug.c | 12 
>  src/util/debug.h |  2 ++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/src/util/debug.c b/src/util/debug.c
> index 98b1853325d..6142801ef60 100644
> --- a/src/util/debug.c
> +++ b/src/util/debug.c
> @@ -76,3 +76,15 @@ env_var_as_boolean(const char *var_name, bool 
> default_value)
>return default_value;
> }
>  }
> +
> +/**
> + * Reads an environment variable and interprets its value as a unsigned.
> + */
> +unsigned
> +env_var_as_unsigned(const char *var_name, unsigned default_value)
> +{
> +   char *str = getenv(var_name);
> +   if (str)
> +  return strtoul(str, NULL, 0);
> +   return default_value;

FOO=bar will return 0; I think returning `default_value` might be a more
predictable behaviour here for users. How about this?

   char *str = getenv(var_name);
   if (str) {
  char *end;
  unsigned long result;

  errno = 0;
  result = strtoul(str, , 0);
  if (errno == 0 && end != str && *end == '\0')
return result;
   }
   return default_value;

The check added here is essentially that strtoul didn't set an error,
had something to read, and read all the way to the end of the string. If
those aren't true, the `default_value` is returned.

With that:
Reviewed-by: Eric Engestrom 

> +}
> diff --git a/src/util/debug.h b/src/util/debug.h
> index 75ebc2ebffb..2e34ebe3421 100644
> --- a/src/util/debug.h
> +++ b/src/util/debug.h
> @@ -41,6 +41,8 @@ parse_debug_string(const char *debug,
> const struct debug_control *control);
>  bool
>  env_var_as_boolean(const char *var_name, bool default_value);
> +unsigned
> +env_var_as_unsigned(const char *var_name, unsigned default_value);
>  
>  #ifdef __cplusplus
>  } /* extern C */
> -- 
> 2.19.1
> 
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Re: [Mesa-dev] [PATCH] etnaviv: Make sure rs alignment checks match

[Lucas Stach]

Hi Guido,

Am Dienstag, den 09.10.2018, 13:50 +0200 schrieb Guido Günther:
> Hi,
> On Mon, Sep 17, 2018 at 04:06:57PM +0200, Guido Günther wrote:
> > etna_resource_alloc and etna_resource_from_handle currently use different 
> > checks.
> > This leads to
> > 
> >    etna_resource_from_handle:492: target=2, 
> > format=PIPE_FORMAT_B8G8R8X8_UNORM, 1080x1920x1, array_size=1, last_level=0, 
> > nr_samples=0, usage=0, bind=8000a, flags=0
> >    etna_resource_from_handle:541: BO stride 4320 is too small for RS engine 
> > width padding (4352, format PIPE_FORMAT_B8G8R8X8_UNORM)
> > 
> > since etna_resource_from_handle wants to be aligned to a 16 byte
> > boundary while the etna_resource_alloc does not.
> > 
> > Adjust the two checks by using a common function.
> 
> Ping?

Thanks, I've finally pushed this to Mesa master.

Regards,
Lucas

> > 
> > Broken by baff59ebf07a114f95ad66d1f54e4b1f409eebee
> > 
> > > > Signed-off-by: Guido Günther 
> > ---
> >  .../drivers/etnaviv/etnaviv_resource.c| 19 +--
> >  1 file changed, 13 insertions(+), 6 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
> > b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> > index 7fd374ae23d..f18c6ec6bfc 100644
> > --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
> > +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> > @@ -176,6 +176,15 @@ setup_miptree(struct etna_resource *rsc, unsigned 
> > paddingX, unsigned paddingY,
> > return size;
> >  }
> >  
> > +/* Is rs alignment needed? */
> > +static bool is_rs_align(struct etna_screen *screen,
> > +const struct pipe_resource *tmpl)
> > +{
> > +   return screen->specs.use_blt ? false : (
> > +  VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
> > +  !etna_resource_sampler_only(tmpl));
> > +}
> > +
> >  /* Create a new resource object, using the given template info */
> >  struct pipe_resource *
> >  etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
> > @@ -217,11 +226,9 @@ etna_resource_alloc(struct pipe_screen *pscreen, 
> > unsigned layout,
> > * resolve engine's width.  If not, we must not align resources used
> > * only for textures. If this GPU uses the BLT engine, never do RS 
> > align.
> > */
> > -  bool rs_align = screen->specs.use_blt ? false : (
> > - VIV_FEATURE(screen, chipMinorFeatures1, 
> > TEXTURE_HALIGN) ||
> > - !etna_resource_sampler_only(templat));
> > -  etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, 
> > ,
> > -   , );
> > +  etna_layout_multiple(layout, screen->specs.pixel_pipes,
> > +   is_rs_align (screen, templat),
> > +   , , );
> >    assert(paddingX && paddingY);
> > } else {
> >    /* Compressed textures are padded to their block size, but we don't 
> > have
> > @@ -519,7 +526,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
> > /* Determine padding of the imported resource. */
> > unsigned paddingX = 0, paddingY = 0;
> > etna_layout_multiple(rsc->layout, screen->specs.pixel_pipes,
> > -VIV_FEATURE(screen, chipMinorFeatures1, 
> > TEXTURE_HALIGN),
> > +is_rs_align(screen, tmpl),
> >  , , >halign);
> >  
> > if (!screen->specs.use_blt)
> > -- 
> > 2.18.0
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> ___
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> etna...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/etnaviv
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Re: [Mesa-dev] [PATCH 4/4] etnaviv: annotate variables only used in debug build

[Philipp Zabel]

On Thu, 2018-11-15 at 15:37 +0100, Lucas Stach wrote:
> Some of the status variables in the compiler are only used in asserts
> and thus may be unused in release builds. Annotate them accordingly
> to avoid 'unused but set' warnings from the compiler.
> 
> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_compiler.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
> b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> index bbc61a59fc67..386136e46836 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> @@ -477,7 +477,7 @@ static void
>  etna_compile_parse_declarations(struct etna_compile *c)
>  {
> struct tgsi_parse_context ctx = { };
> -   unsigned status = TGSI_PARSE_OK;
> +   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;

Maybe out of scope for this patch, but the initial assignment is
superfluous here and in the next two instances:

> status = tgsi_parse_init(, c->tokens);
> assert(status == TGSI_PARSE_OK);
>  
> @@ -530,7 +530,7 @@ static void
>  etna_compile_pass_check_usage(struct etna_compile *c)
>  {
> struct tgsi_parse_context ctx = { };
> -   unsigned status = TGSI_PARSE_OK;
> +   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;
> status = tgsi_parse_init(, c->tokens);
> assert(status == TGSI_PARSE_OK);
>  
> @@ -662,7 +662,7 @@ etna_compile_pass_optimize_outputs(struct etna_compile *c)
>  {
> struct tgsi_parse_context ctx = { };
> int inst_idx = 0;
> -   unsigned status = TGSI_PARSE_OK;
> +   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;
> status = tgsi_parse_init(, c->tokens);
> assert(status == TGSI_PARSE_OK);
>  
> @@ -1812,7 +1812,7 @@ static void
>  etna_compile_pass_generate_code(struct etna_compile *c)
>  {
> struct tgsi_parse_context ctx = { };
> -   unsigned status = tgsi_parse_init(, c->tokens);
> +   MAYBE_UNUSED unsigned status = tgsi_parse_init(, c->tokens);
> assert(status == TGSI_PARSE_OK);
>  
> int inst_idx = 0;

regards
Philipp
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Re: [Mesa-dev] [PATCH 3/4] etnaviv: enable full overwrite in a few more cases

[Philipp Zabel]

On Thu, 2018-11-15 at 15:37 +0100, Lucas Stach wrote:
> Take into account the render target format when checking if the color
> mask affects all channels of the RT. This allows to enable full
> override in a few cases where a non-alpha format is used.
> 
> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_blend.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_blend.c 
> b/src/gallium/drivers/etnaviv/etnaviv_blend.c
> index 1792fd0fdd67..2bf081c2e710 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_blend.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_blend.c
> @@ -114,6 +114,7 @@ etna_update_blend(struct etna_context *ctx)
> struct pipe_blend_state *pblend = ctx->blend;
> struct etna_blend_state *blend = etna_blend_state(pblend);
> const struct pipe_rt_blend_state *rt0 = >rt[0];
> +   const struct util_format_description *desc;
> uint32_t colormask;
>  
> if (pfb->cbufs[0] &&
> @@ -131,8 +132,10 @@ etna_update_blend(struct etna_context *ctx)
>  * - The color mask is 
>  * - No blending is used
>  */
> -   bool full_overwrite = ((rt0->colormask == 0xf) && blend->fo_allowed) ||
> - !pfb->cbufs[0];
> +   if (pfb->cbufs[0])
> +  desc = util_format_description(pfb->cbufs[0]->format);
> +   bool full_overwrite = !pfb->cbufs[0] || ((blend->fo_allowed &&
> + util_format_colormask_full(desc, colormask)));

Is the comment above still accurate with this change?

regards
Philipp
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Re: [Mesa-dev] [PATCH 2/4] etnaviv: use surface format directly

[Philipp Zabel]

On Thu, 2018-11-15 at 15:37 +0100, Lucas Stach wrote:
> There is no need to do the detour over the resource behind the
> surface to get the format. Use the surface format directly.
> 
> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_blend.c   | 2 +-
>  src/gallium/drivers/etnaviv/etnaviv_context.c | 9 ++---
>  2 files changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_blend.c 
> b/src/gallium/drivers/etnaviv/etnaviv_blend.c
> index 9c23411d4ff7..1792fd0fdd67 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_blend.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_blend.c
> @@ -117,7 +117,7 @@ etna_update_blend(struct etna_context *ctx)
> uint32_t colormask;
>  
> if (pfb->cbufs[0] &&
> -   translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
> +   translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {

There is another instance of this in etna_update_blend_color() below.

With that added,
Reviewed-by: Philipp Zabel 

>colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G);
>if (rt0->colormask & PIPE_MASK_R)
>   colormask |= PIPE_MASK_B;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
> b/src/gallium/drivers/etnaviv/etnaviv_context.c
> index 1c305d82a0fc..aa7425662898 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
> @@ -212,13 +212,8 @@ etna_draw_vbo(struct pipe_context *pctx, const struct 
> pipe_draw_info *info)
> ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
>  
> struct etna_shader_key key = {};
> -   struct etna_surface *cbuf = etna_surface(pfb->cbufs[0]);
> -
> -   if (cbuf) {
> -  struct etna_resource *res = etna_resource(cbuf->base.texture);
> -
> -  key.frag_rb_swap = !!translate_rs_format_rb_swap(res->base.format);
> -   }
> +   if (pfb->cbufs[0])
> +  key.frag_rb_swap = 
> !!translate_rs_format_rb_swap(pfb->cbufs[0]->format);
>  
> if (!etna_get_vs(ctx, key) || !etna_get_fs(ctx, key)) {
>BUG("compiled shaders are not okay");

regards
Philipp
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Re: [Mesa-dev] [PATCH 1/4] etnaviv: use dummy RT buffer when rendering without color buffer

[Philipp Zabel]

On Thu, 2018-11-15 at 15:37 +0100, Lucas Stach wrote:
> At least GC2000 seems to push some dirt from the PE color cache into
> the last bound render target when drawing depth only. Newer cores
> seem to behave properly and don't do this, but I have found no way
> to fix it on GC2000. Flushes and stalls don't seem to make any
> difference.
> 
> In order to stop the core from pushing the dirt into a precious real
> render target, plug in dummy buffer when rendering without a color
> buffer.
> 
> Signed-off-by: Lucas Stach 

Reviewed-by: Philipp Zabel 

regards
Philipp
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[Mesa-dev] [PATCH] i965: Fix indirect parameters draw during conditional rendering on hsw+

[Illia Iorin]

Both extensions GL_ARB_indirect_parameters and GL_NV_conditional_render
use MI_PREDICATE for their work so when conditional rendering was enabled
GL_ARB_indirect_parameters incorrectly handled already present predicate
result and didn't restore it in the end.

Instead special code path for this case was added.

for each draw call mi_math is used to compute mi_predicate_result as:
( (draw index < draw count) && stored_mi_predicate_result )

After the loop mi_predicate is restored to the original value.

Also the amount of loadings to GPU registers was reduced by moving
loadings which were constant in respect to the draw loop outside of it.

Signed-off-by: Illia Iorin 
Signed-off-by: Danylo Piliaiev 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108759
---
I haven’t tested this patch on intel CI.
I going to test this patch when piglit test
is merged https://patchwork.freedesktop.org/patch/262127/

 src/mesa/drivers/dri/i965/brw_draw.c | 108 ++-
 1 file changed, 88 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8536c04010..98d9e9c553 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -1030,6 +1030,7 @@ brw_draw_prims(struct gl_context *ctx,
unsigned i;
struct brw_context *brw = brw_context(ctx);
int predicate_state = brw->predicate.state;
+   const struct gen_device_info *devinfo = >screen->devinfo;
struct brw_transform_feedback_object *xfb_obj =
   (struct brw_transform_feedback_object *) gl_xfb_obj;
 
@@ -1072,11 +1073,9 @@ brw_draw_prims(struct gl_context *ctx,
 * to it.
 */
 
-   for (i = 0; i < nr_prims; i++) {
-  /* Implementation of ARB_indirect_parameters via predicates */
-  if (brw->draw.draw_params_count_bo) {
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
-
+   if (brw->draw.draw_params_count_bo) {
+  /* Preparing registers for ARB_indirect_parameters  */
+  if (brw->predicate.state != BRW_PREDICATE_STATE_USE_BIT) {
  /* Upload the current draw count from the draw parameters buffer to
   * MI_PREDICATE_SRC0.
   */
@@ -1085,25 +1084,94 @@ brw_draw_prims(struct gl_context *ctx,
brw->draw.draw_params_count_offset);
  /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
  brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0);
- /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
- brw_load_register_imm64(brw, MI_PREDICATE_SRC1, prims[i].draw_id);
-
- BEGIN_BATCH(1);
- if (i == 0 && brw->predicate.state != BRW_PREDICATE_STATE_USE_BIT) {
-OUT_BATCH(GEN7_MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV |
-  MI_PREDICATE_COMBINEOP_SET |
-  MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
- } else {
-OUT_BATCH(GEN7_MI_PREDICATE |
-  MI_PREDICATE_LOADOP_LOAD | MI_PREDICATE_COMBINEOP_XOR |
-  MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
- }
+  } else if (devinfo->gen >= 8 || devinfo->is_haswell) {
+ /* Upload the current MI_PREDICATE_RESULT buffer to GPR0. */
+ brw_load_register_reg64(brw, MI_PREDICATE_RESULT, HSW_CS_GPR(0));
+ /* Upload the current draw count from the draw parameters buffer to
+  * GPR1.
+  */
+ brw_load_register_mem(brw, HSW_CS_GPR(1),
+   brw->draw.draw_params_count_bo,
+   brw->draw.draw_params_count_offset);
+
+ /* Zero the top 32-bits of GPR1 */
+ brw_load_register_imm32(brw, HSW_CS_GPR(1) + 4, 0);
+  } else {
+ /* TODO
+  * Implement slow code path  on pre hsw:
+  * read value from count buffer.
+  */
+ _mesa_warning(ctx, "Usage of GL_ARB_indirect_parameters " 
+"functions during GL_NV_conditional_render "
+"unsupported on pre hsw platform");
+ brw_finish_drawing(ctx);
+ brw->predicate.state = predicate_state;
+ return;
+  }
+   }
+
+   if (brw->draw.draw_params_count_bo &&
+   (brw->predicate.state == BRW_PREDICATE_STATE_USE_BIT) &&
+   (devinfo->gen >= 8 || devinfo->is_haswell)) {
+  for (i = 0; i < nr_prims; i++) {
+
+ static const uint32_t maths[] = {
+/* Compute (draw index < draw count).
+ * We do this by subtracting and storing the carry bit.
+ */ 
+MI_MATH_ALU2(LOAD, SRCA, R2),
+MI_MATH_ALU2(LOAD, SRCB, R1),
+MI_MATH_ALU0(SUB),
+MI_MATH_ALU2(STORE, R3, CF),
+/* Compute (subtracting result & MI_PREDICAT). */ 
+MI_MATH_ALU2(LOAD, SRCA, R3),
+MI_MATH_ALU2(LOAD, SRCB, R0),
+MI_MATH_ALU0(AND),
+MI_MATH_ALU2(STORE, R3, ACCU),
+ };
+ 

[Mesa-dev] [PATCH 4/4] etnaviv: annotate variables only used in debug build

[Lucas Stach]

Some of the status variables in the compiler are only used in asserts
and thus may be unused in release builds. Annotate them accordingly
to avoid 'unused but set' warnings from the compiler.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_compiler.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
index bbc61a59fc67..386136e46836 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
@@ -477,7 +477,7 @@ static void
 etna_compile_parse_declarations(struct etna_compile *c)
 {
struct tgsi_parse_context ctx = { };
-   unsigned status = TGSI_PARSE_OK;
+   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;
status = tgsi_parse_init(, c->tokens);
assert(status == TGSI_PARSE_OK);
 
@@ -530,7 +530,7 @@ static void
 etna_compile_pass_check_usage(struct etna_compile *c)
 {
struct tgsi_parse_context ctx = { };
-   unsigned status = TGSI_PARSE_OK;
+   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;
status = tgsi_parse_init(, c->tokens);
assert(status == TGSI_PARSE_OK);
 
@@ -662,7 +662,7 @@ etna_compile_pass_optimize_outputs(struct etna_compile *c)
 {
struct tgsi_parse_context ctx = { };
int inst_idx = 0;
-   unsigned status = TGSI_PARSE_OK;
+   MAYBE_UNUSED unsigned status = TGSI_PARSE_OK;
status = tgsi_parse_init(, c->tokens);
assert(status == TGSI_PARSE_OK);
 
@@ -1812,7 +1812,7 @@ static void
 etna_compile_pass_generate_code(struct etna_compile *c)
 {
struct tgsi_parse_context ctx = { };
-   unsigned status = tgsi_parse_init(, c->tokens);
+   MAYBE_UNUSED unsigned status = tgsi_parse_init(, c->tokens);
assert(status == TGSI_PARSE_OK);
 
int inst_idx = 0;
-- 
2.19.1

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[Mesa-dev] [PATCH 2/4] etnaviv: use surface format directly

[Lucas Stach]

There is no need to do the detour over the resource behind the
surface to get the format. Use the surface format directly.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_blend.c   | 2 +-
 src/gallium/drivers/etnaviv/etnaviv_context.c | 9 ++---
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_blend.c 
b/src/gallium/drivers/etnaviv/etnaviv_blend.c
index 9c23411d4ff7..1792fd0fdd67 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_blend.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_blend.c
@@ -117,7 +117,7 @@ etna_update_blend(struct etna_context *ctx)
uint32_t colormask;
 
if (pfb->cbufs[0] &&
-   translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
+   translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {
   colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G);
   if (rt0->colormask & PIPE_MASK_R)
  colormask |= PIPE_MASK_B;
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index 1c305d82a0fc..aa7425662898 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -212,13 +212,8 @@ etna_draw_vbo(struct pipe_context *pctx, const struct 
pipe_draw_info *info)
ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
 
struct etna_shader_key key = {};
-   struct etna_surface *cbuf = etna_surface(pfb->cbufs[0]);
-
-   if (cbuf) {
-  struct etna_resource *res = etna_resource(cbuf->base.texture);
-
-  key.frag_rb_swap = !!translate_rs_format_rb_swap(res->base.format);
-   }
+   if (pfb->cbufs[0])
+  key.frag_rb_swap = !!translate_rs_format_rb_swap(pfb->cbufs[0]->format);
 
if (!etna_get_vs(ctx, key) || !etna_get_fs(ctx, key)) {
   BUG("compiled shaders are not okay");
-- 
2.19.1

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[Mesa-dev] [PATCH 1/4] etnaviv: use dummy RT buffer when rendering without color buffer

[Lucas Stach]

At least GC2000 seems to push some dirt from the PE color cache into
the last bound render target when drawing depth only. Newer cores
seem to behave properly and don't do this, but I have found no way
to fix it on GC2000. Flushes and stalls don't seem to make any
difference.

In order to stop the core from pushing the dirt into a precious real
render target, plug in dummy buffer when rendering without a color
buffer.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_context.c | 13 +
 src/gallium/drivers/etnaviv/etnaviv_context.h |  3 +++
 src/gallium/drivers/etnaviv/etnaviv_state.c   |  5 +++--
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index 3038d210e109..1c305d82a0fc 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -60,6 +60,9 @@ etna_context_destroy(struct pipe_context *pctx)
 {
struct etna_context *ctx = etna_context(pctx);
 
+   if (ctx->dummy_rt)
+  etna_bo_del(ctx->dummy_rt);
+
if (ctx->primconvert)
   util_primconvert_destroy(ctx->primconvert);
 
@@ -486,6 +489,16 @@ etna_context_create(struct pipe_screen *pscreen, void 
*priv, unsigned flags)
slab_create_child(>transfer_pool, >transfer_pool);
list_inithead(>active_hw_queries);
 
+   /* create dummy RT buffer, used when rendering with no color buffer */
+   ctx->dummy_rt = etna_bo_new(ctx->screen->dev, 64 * 64 * 4,
+   DRM_ETNA_GEM_CACHE_WC);
+   if (!ctx->dummy_rt)
+  goto fail;
+
+   ctx->dummy_rt_reloc.bo = ctx->dummy_rt;
+   ctx->dummy_rt_reloc.offset = 0;
+   ctx->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
+
return pctx;
 
 fail:
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
b/src/gallium/drivers/etnaviv/etnaviv_context.h
index 584caa77080b..6ad9f3431e15 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
@@ -190,6 +190,9 @@ struct etna_context {
 
/* list of active hardware queries */
struct list_head active_hw_queries;
+
+   struct etna_bo *dummy_rt;
+   struct etna_reloc dummy_rt_reloc;
 };
 
 static inline struct etna_context *
diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
b/src/gallium/drivers/etnaviv/etnaviv_state.c
index 87ba10b0dc98..006bf3016812 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -191,8 +191,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
   cs->TS_COLOR_STATUS_BASE.bo = NULL;
   cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 
-  for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
- cs->PE_PIPE_COLOR_ADDR[i].bo = NULL;
+  cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
+  for (int i = 0; i < ctx->specs.pixel_pipes; i++)
+ cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
}
 
if (sv->zsbuf != NULL) {
-- 
2.19.1

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[Mesa-dev] [PATCH 3/4] etnaviv: enable full overwrite in a few more cases

[Lucas Stach]

Take into account the render target format when checking if the color
mask affects all channels of the RT. This allows to enable full
override in a few cases where a non-alpha format is used.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_blend.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_blend.c 
b/src/gallium/drivers/etnaviv/etnaviv_blend.c
index 1792fd0fdd67..2bf081c2e710 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_blend.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_blend.c
@@ -114,6 +114,7 @@ etna_update_blend(struct etna_context *ctx)
struct pipe_blend_state *pblend = ctx->blend;
struct etna_blend_state *blend = etna_blend_state(pblend);
const struct pipe_rt_blend_state *rt0 = >rt[0];
+   const struct util_format_description *desc;
uint32_t colormask;
 
if (pfb->cbufs[0] &&
@@ -131,8 +132,10 @@ etna_update_blend(struct etna_context *ctx)
 * - The color mask is 
 * - No blending is used
 */
-   bool full_overwrite = ((rt0->colormask == 0xf) && blend->fo_allowed) ||
- !pfb->cbufs[0];
+   if (pfb->cbufs[0])
+  desc = util_format_description(pfb->cbufs[0]->format);
+   bool full_overwrite = !pfb->cbufs[0] || ((blend->fo_allowed &&
+ util_format_colormask_full(desc, colormask)));
blend->PE_COLOR_FORMAT =
 VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
 COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
-- 
2.19.1

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[Mesa-dev] [PATCH 1/3] radv: do not initialize DCC as cleared for MSAA textures

[Samuel Pitoiset]

This doesn't seem to work, instead always use the fully
expanded mode for MSAA textures.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8e0ed284d6..0fe90ceff7 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4327,7 +4327,14 @@ static void radv_init_color_image_metadata(struct 
radv_cmd_buffer *cmd_buffer,
 
if (radv_layout_dcc_compressed(image, dst_layout,
   dst_queue_mask)) {
-   value = 0x20202020u;
+   if (image->info.samples == 1) {
+   /* Initializing DCC as compressed for MSAA
+* textures doesn't seem to work. Be
+* conservative and always use the fully
+* expanded mode.
+*/
+   value = 0x20202020u;
+   }
need_decompress_pass = true;
}
 
-- 
2.19.1

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[Mesa-dev] [PATCH 3/3] radv: allow to use DCC for MSAA x4 and x8 with the debug option

[Samuel Pitoiset]

No CTS regressions on GFX8 now. Still some fails when resolving
DCC/MSAA textures on GFX9.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_image.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 64346aa340..a71b65edb3 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -157,12 +157,11 @@ radv_use_dcc_for_image(struct radv_device *device,
if (create_info->scanout)
return false;
 
-   /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
-* 2x can be enabled with an option.
+   /* TODO: Enable DCC/MSAA by default. This requires fixing fast color
+* clears and to investigate about performance.
 */
-   if (pCreateInfo->samples > 2 ||
-   (pCreateInfo->samples == 2 &&
-!device->physical_device->dcc_msaa_allowed))
+   if (pCreateInfo->samples >= 2 &&
+   !device->physical_device->dcc_msaa_allowed)
return false;
 
/* Determine if the formats are DCC compatible. */
-- 
2.19.1

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[Mesa-dev] [PATCH 2/3] radv: disable fast color clears for DCC and MSAA textures

[Samuel Pitoiset]

This is currently broken. My plan is to re-enable it once I
have figured why this breaks a few number of CTS.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_clear.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 35da8797f5..e15e76c619 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1145,6 +1145,9 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (!can_avoid_fast_clear_elim)
goto fail;
 
+   /* FIXME: Figure out how to do fast clears with MSAA. */
+   goto fail;
+
assert(radv_image_has_cmask(iview->image));
 
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
-- 
2.19.1

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[Mesa-dev] [PATCH 0/3] radv: some fixes for DCC/MSAA

[Samuel Pitoiset]

Hi,

This little series fixes some CTS when DCC is enabled for MSAA textures.
It will be easier for me to improve the thing if the current implementation
doesn't introduce any CTS regressions.

This is still disabled by default for now anyways.

Please review,
Thanks!

Samuel Pitoiset (3):
  radv: do not initialize DCC as cleared for MSAA textures
  radv: disable fast color clears for DCC and MSAA textures
  radv: allow to use DCC for MSAA x4 and x8 with the debug option

 src/amd/vulkan/radv_cmd_buffer.c | 9 -
 src/amd/vulkan/radv_image.c  | 9 -
 src/amd/vulkan/radv_meta_clear.c | 3 +++
 3 files changed, 15 insertions(+), 6 deletions(-)

-- 
2.19.1

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Re: [Mesa-dev] [PATCH] intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_sampler

[Jason Ekstrand]

Rb

On November 15, 2018 00:42:45 Sagar Ghuge  wrote:


Both BRW_SFID_SAMPLER and GEN6_SFID_DATAPORT_SAMPLER_CACHE are getting
disassembled as "sampler", which is misleading for assembler tool.

Signed-off-by: Sagar Ghuge 
---
src/intel/compiler/brw_disasm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index cfccdea3b8..6c79fec0a1 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -289,7 +289,7 @@ static const char *const gen6_sfid[16] = {
   [BRW_SFID_MESSAGE_GATEWAY]  = "gateway",
   [BRW_SFID_URB]  = "urb",
   [BRW_SFID_THREAD_SPAWNER]   = "thread_spawner",
-   [GEN6_SFID_DATAPORT_SAMPLER_CACHE]  = "sampler",
+   [GEN6_SFID_DATAPORT_SAMPLER_CACHE]  = "dp_sampler",
   [GEN6_SFID_DATAPORT_RENDER_CACHE]   = "render",
   [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
   [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
--
2.17.1

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[Mesa-dev] [PATCH v5] virgl: native fence fd support

[Robert Foss]

Following the support for fences on the virtio driver add support
for native fence on virgl. This was somewhat based on the freedeno one.

Signed-off-by: Gustavo Padovan 
Signed-off-by: Robert Foss 
Reviewed-by: Emil Velikov 
---

Sorry about the spam, but I realized Emils r-b wasn't
included in v4.

This patch has been tested using Qemu & Virglrenderer.

Linux virtgpu fences branch:
https://gitlab.collabora.com/robertfoss/linux/tree/virtio_fences_v5

This branch:
https://gitlab.collabora.com/robertfoss/mesa/tree/virtio_fences_v5

Changes since v4:
 - Add Reviewed-by: Emil Velikov 

Changes since v3:
 - Emil: Replaced driver_version() winsys func. with supports_fence variable
 - Emil: Replaced virgl_fence_server_sync() assert with it
 - Emil: Refactored virgl_fence_server_sync() to use sync_accumulate()

Changes since v2:
 - Add fence creation on flush

 src/gallium/drivers/virgl/virgl_context.c | 46 --
 src/gallium/drivers/virgl/virgl_screen.c  | 12 ++-
 src/gallium/drivers/virgl/virgl_winsys.h  | 14 +++-
 .../winsys/virgl/drm/virgl_drm_winsys.c   | 84 ++-
 .../winsys/virgl/drm/virgl_drm_winsys.h   |  2 +
 src/gallium/winsys/virgl/drm/virtgpu_drm.h| 14 +++-
 .../winsys/virgl/vtest/virgl_vtest_winsys.c   | 10 ++-
 7 files changed, 166 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index 96932c473d8..9be7775abd3 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -21,6 +21,7 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include "pipe/p_shader_tokens.h"
 
 #include "pipe/p_context.h"
@@ -709,13 +710,20 @@ static void virgl_draw_vbo(struct pipe_context *ctx,
 
 }
 
-static void virgl_flush_eq(struct virgl_context *ctx, void *closure)
+static void virgl_flush_eq(struct virgl_context *ctx, void *closure,
+  struct pipe_fence_handle **fence)
 {
struct virgl_screen *rs = virgl_screen(ctx->base.screen);
+   int out_fence_fd = -1;
 
/* send the buffer to the remote side for decoding */
ctx->num_transfers = ctx->num_draws = 0;
-   rs->vws->submit_cmd(rs->vws, ctx->cbuf);
+
+   rs->vws->submit_cmd(rs->vws, ctx->cbuf, ctx->cbuf->in_fence_fd,
+   ctx->cbuf->needs_out_fence_fd ? _fence_fd : NULL);
+
+   if (fence)
+  *fence = rs->vws->cs_create_fence(rs->vws, out_fence_fd);
 
virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 
@@ -728,11 +736,10 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
enum pipe_flush_flags flags)
 {
struct virgl_context *vctx = virgl_context(ctx);
-   struct virgl_screen *rs = virgl_screen(ctx->screen);
struct virgl_buffer *buf, *tmp;
 
-   if (fence)
-  *fence = rs->vws->cs_create_fence(rs->vws);
+   if (flags & PIPE_FLUSH_FENCE_FD)
+   vctx->cbuf->needs_out_fence_fd = true;
 
LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, >to_flush_bufs, flush_list) {
   struct pipe_resource *res = >base.u.b;
@@ -742,7 +749,13 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
   pipe_resource_reference(, NULL);
 
}
-   virgl_flush_eq(vctx, vctx);
+   virgl_flush_eq(vctx, vctx, fence);
+
+   if (vctx->cbuf->in_fence_fd != -1) {
+  close(vctx->cbuf->in_fence_fd);
+  vctx->cbuf->in_fence_fd = -1;
+   }
+   vctx->cbuf->needs_out_fence_fd = false;
 }
 
 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context 
*ctx,
@@ -1016,6 +1029,23 @@ static void virgl_set_shader_buffers(struct pipe_context 
*ctx,
virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
 }
 
+static void virgl_create_fence_fd(struct pipe_context *ctx,
+   struct pipe_fence_handle **fence, int fd)
+{
+   struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+   *fence = rs->vws->cs_create_fence(rs->vws, fd);
+}
+
+static void virgl_fence_server_sync(struct pipe_context *ctx,
+   struct pipe_fence_handle *fence)
+{
+   struct virgl_context *vctx = virgl_context(ctx);
+   struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+   rs->vws->fence_server_sync(rs->vws, vctx->cbuf, fence);
+}
+
 static void virgl_set_shader_images(struct pipe_context *ctx,
 enum pipe_shader_type shader,
 unsigned start_slot, unsigned count,
@@ -1108,7 +1138,7 @@ virgl_context_destroy( struct pipe_context *ctx )
vctx->framebuffer.zsbuf = NULL;
vctx->framebuffer.nr_cbufs = 0;
virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
-   virgl_flush_eq(vctx, vctx);
+   virgl_flush_eq(vctx, vctx, NULL);
 
rs->vws->cmd_buf_destroy(vctx->cbuf);
if (vctx->uploader)
@@ -1244,6 +1274,8 @@ struct pipe_context *virgl_context_create(struct 
pipe_screen *pscreen,
vctx->base.resource_copy_region = virgl_resource_copy_region;

[Mesa-dev] [ANNOUNCE] mesa 18.2.5

[Juan A. Suarez Romero]

Mesa 18.2.5 is now available.

In this release we have:

A patch for nine state tracker that fixes several crashes using nine's
thread_submit feature. There are other patches to other state trackers.

A couple of patches for Meson build system, as well as for autotools.

In the drivers side, there are a couple of fixes for RADV, one regarding
subgroups and another regarding conditional rendering. There are also fixes for
virgl, r600, and i965.

Finally, the queue contains a couple of fixes for NIR, Wayland, and other
components.


Andre Heider (1):
  st/nine: fix stack corruption due to ABI mismatch

Andrii Simiklit (1):
  i965/batch: don't ignore the 'brw_new_batch' call for a 'new batch'

Dylan Baker (2):
  meson: link gallium nine with pthreads
  meson: fix libatomic tests

Emil Velikov (2):
  egl/glvnd: correctly report errors when vendor cannot be found
  m4: add Werror when checking for compiler flags

Eric Engestrom (6):
  svga: add missing meson build dependency
  clover: add missing meson build dependency
  wsi/wayland: use proper VkResult type
  wsi/wayland: only finish() a successfully init()ed display
  configure: install KHR/khrplatform.h when needed
  meson: install KHR/khrplatform.h when needed

Gert Wollny (1):
  virgl/vtest-winsys: Use virgl version of bind flags

Jonathan Gray (1):
  intel/tools: include stdarg.h in error2aub

Juan A. Suarez Romero (5):
  docs: add sha256 checksums for 18.2.4
  cherry-ignore: add explicit 18.3 only nominations
  cherry-ignore: i965/batch: avoid reverting batch buffer if saved state is 
an empty
  Update version to 18.2.5
  docs: add release notes for 18.2.5

Lionel Landwerlin (1):
  anv/android: mark gralloc allocated BOs as external

Marek Olšák (3):
  ac: fix ac_build_fdiv for f64
  st/va: fix incorrect use of resource_destroy
  include: update GL & GLES headers (v2)

Matt Turner (2):
  util/ralloc: Switch from DEBUG to NDEBUG
  util/ralloc: Make sizeof(linear_header) a multiple of 8

Olivier Fourdan (1):
  wayland/egl: Resize EGL surface on update buffer for swrast

Rhys Perry (1):
  glsl_to_tgsi: don't create 64-bit integer MAD/FMA

Samuel Pitoiset (2):
  radv: disable conditional rendering for vkCmdCopyQueryPoolResults()
  radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+

Sergii Romantsov (1):
  autotools: library-dependency when no sse and 32-bit

Timothy Arceri (4):
  st/mesa: calculate buffer size correctly for packed uniforms
  st/glsl_to_nir: fix next_stage gathering
  nir: add glsl_type_is_integer() helper
  nir: don't pack varyings ints with floats unless flat

Vadym Shovkoplias (1):
  glsl/linker: Fix out variables linking during single stage

Vinson Lee (1):
  r600/sb: Fix constant logical operand in assert.

git tag: mesa-18.2.5

https://mesa.freedesktop.org/archive/mesa-18.2.5.tar.gz
MD5:  b13964a76d4855d0dfb4d93ff61221bb  mesa-18.2.5.tar.gz
SHA1: cbec6e9aed1ebfac1ee8f7c1e00e854ec53044df  mesa-18.2.5.tar.gz
SHA256: dddc28928b6f4083a0d5120b58c1c8e2dc189ab5c14299c08a386607fdbbdce7  
mesa-18.2.5.tar.gz
SHA512: 
3c6ef3d3ea4c4efd3cf853b5188846b38f307e0729e8941c6ddb948524663bd0349706468ad6da95ad82b3d639bf1ee8aacc078987d370d1553b7119c9e51956
  mesa-18.2.5.tar.gz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.2.5.tar.gz.sig

https://mesa.freedesktop.org/archive/mesa-18.2.5.tar.xz
MD5:  b31a43ebb8b37fb704a9a75c90bbd71b  mesa-18.2.5.tar.xz
SHA1: 1ada7d5fc5fabca63c78396b5afa587b94b9f2e0  mesa-18.2.5.tar.xz
SHA256: b12c32872832e5353155e1e8026e1f1ab75bba9dc5b178d712045684d26c2b73  
mesa-18.2.5.tar.xz
SHA512: 
dd454c720241dffa61f3380be62479979a43004b2a52293b817bd3ea95f75960edee680e7380a13fae09b67a90dc0393e4a022d543db91b2f142f2468a9661f0
  mesa-18.2.5.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.2.5.tar.xz.sig



signature.asc
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[Mesa-dev] [PATCH v6 8/8] mesa/main: Expose EXT_sRGB_write_control

[Gert Wollny]

From: Gert Wollny 

Use EXT_framebuffer_sRGB to expose EXT_sRGB_write_control on GLES. Remove
the checks for desktion GL in the enable calls, since EXT_framebuffer_sRGB
now also indicates support for switching the linear-sRGB color
space conversion on GLES.

This patch enables and makes pass (tested on r600, virgl, softpipe and i965):

  dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_enabled*

When extension is manually disabled via MESA_EXTENSION_OVERRIDE

  
dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_unsupported_enum

passes as expected. 
(Since the test needlessly checks for the GLES version 3.2 a manual override 
MESA_GLES_VERSION_OVERRIDE=3.2 is needed for some drivers)

No regressions were observed with the dEQP 2, 3, and 31 test suites.

Thanks to Ilia Mirkin for all the helpful discussions that guided me while 
reworking this series.

Signed-off-by: Gert Wollny 
---
 src/mesa/main/enable.c   | 4 
 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/get_hash_params.py | 4 +++-
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index bd3e493da5..d03ffc9d80 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1125,8 +1125,6 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap, 
GLboolean state)
 
   /* GL3.0 - GL_framebuffer_sRGB */
   case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx))
-goto invalid_enum_error;
  CHECK_EXTENSION(EXT_framebuffer_sRGB, cap);
  _mesa_set_framebuffer_srgb(ctx, state);
  return;
@@ -1765,8 +1763,6 @@ _mesa_IsEnabled( GLenum cap )
 
   /* GL3.0 - GL_framebuffer_sRGB */
   case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx))
-goto invalid_enum_error;
  CHECK_EXTENSION(EXT_framebuffer_sRGB);
  return ctx->Color.sRGBEnabled;
 
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index a516a1b17f..ea9f54ecdc 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -266,6 +266,7 @@ EXT(EXT_shader_integer_mix  , 
EXT_shader_integer_mix
 EXT(EXT_shader_io_blocks, dummy_true   
  ,  x ,  x ,  x ,  31, 2014)
 EXT(EXT_shader_samples_identical, EXT_shader_samples_identical 
  , GLL, GLC,  x ,  31, 2015)
 EXT(EXT_shadow_funcs, ARB_shadow   
  , GLL,  x ,  x ,  x , 2002)
+EXT(EXT_sRGB_write_control  , EXT_framebuffer_sRGB 
  ,   x,  x ,  x ,  30, 2013)
 EXT(EXT_stencil_two_side, EXT_stencil_two_side 
  , GLL,  x ,  x ,  x , 2001)
 EXT(EXT_stencil_wrap, dummy_true   
  , GLL,  x ,  x ,  x , 2002)
 EXT(EXT_subtexture  , dummy_true   
  , GLL,  x ,  x ,  x , 1995)
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 1840db6ebb..8de634e90a 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -463,6 +463,9 @@ descriptor=[
   [ "MIN_FRAGMENT_INTERPOLATION_OFFSET", 
"CONTEXT_FLOAT(Const.MinFragmentInterpolationOffset), 
extra_ARB_gpu_shader5_or_OES_sample_variables" ],
   [ "MAX_FRAGMENT_INTERPOLATION_OFFSET", 
"CONTEXT_FLOAT(Const.MaxFragmentInterpolationOffset), 
extra_ARB_gpu_shader5_or_OES_sample_variables" ],
   [ "FRAGMENT_INTERPOLATION_OFFSET_BITS", 
"CONST(FRAGMENT_INTERPOLATION_OFFSET_BITS), 
extra_ARB_gpu_shader5_or_OES_sample_variables" ],
+
+# GL_EXT_framebuffer_EXT  / GLES 3.0 + EXT_sRGB_write_control
+  [ "FRAMEBUFFER_SRGB_EXT", "CONTEXT_BOOL(Color.sRGBEnabled), 
extra_EXT_framebuffer_sRGB" ],
 ]},
 
 { "apis": ["GLES", "GLES2"], "params": [
@@ -934,7 +937,6 @@ descriptor=[
   [ "RGBA_FLOAT_MODE_ARB", "BUFFER_FIELD(Visual.floatMode, TYPE_BOOLEAN), 
extra_core_ARB_color_buffer_float_and_new_buffers" ],
 
 # GL3.0 / GL_EXT_framebuffer_sRGB
-  [ "FRAMEBUFFER_SRGB_EXT", "CONTEXT_BOOL(Color.sRGBEnabled), 
extra_EXT_framebuffer_sRGB" ],
   [ "FRAMEBUFFER_SRGB_CAPABLE_EXT", "BUFFER_INT(Visual.sRGBCapable), 
extra_EXT_framebuffer_sRGB_and_new_buffers" ],
 
 # GL 3.1
-- 
2.18.1

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[Mesa-dev] [PATCH v6 3/8] mesa:main: Add flag for EXT_sRGB to gl_extensions

[Gert Wollny]

From: Gert Wollny 

EXT_sRGB is an (incomplete) GLES extension that provides support for sRGB
framebuffer attachments, hence it can be used to check for this support
as an alternative to EXT_framebuffer_sRGB that provides the same
functionality but also sRGB write control support.

However, since EXT_sRGB  is incomplete and superseded by GLES 3.0 it will
not be exposed as an extension.

Signed-off-by: Gert Wollny 
---
 src/mesa/main/mtypes.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 656e1226f9..4ee55266e5 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4253,6 +4253,7 @@ struct gl_extensions
GLboolean EXT_semaphore_fd;
GLboolean EXT_shader_integer_mix;
GLboolean EXT_shader_samples_identical;
+   GLboolean EXT_sRGB;
GLboolean EXT_stencil_two_side;
GLboolean EXT_texture_array;
GLboolean EXT_texture_compression_latc;
-- 
2.18.1

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[Mesa-dev] [PATCH v6 5/8] mesa/st: rework support for sRGB framebuffer attachements

[Gert Wollny]

From: Gert Wollny 

For GLES sRGB framebuffer attachemnt support is provided in two steps:
(1) sRGB attachments like described in EXT_sRGB (and GLES 3.0) that enable
linear to sRGB color space transformation automatically, and (2) the ability
to switch formats of the render target surface between sRGB and linear
that introduces full support for EXT_framebuffer_sRGB.

Set and use the according flags to reflect these two levels of sRGB support.

Also handle the difference between desktop GL and GLES regarding how the 
linear-sRGB conversion is enabled: on desktop GL for a sRGB framebuffer 
attachment the linear-sRGB conversion is turned off by default, and for GLES 
it is turned on. This needs to be taken into account when initially creating 
a surface, i.e. on desktop GL creation of a sRGB surface is preferred, but on
GLES sRGB surfaces are only created when explicitly requested.

v2: - always enable the extension when sRGB is supported (Ilia Mirkin).
- Correct handling by moving extension initialization to the
  place where gallium/st actually takes care of this. This also
  fixes properly disabling the extension via MESA_EXTENSION_OVERRIDE
- reinstate check for desktop GL and add check for the extension
  when creating the framebuffer

v3: - Only create sRGB renderbuffers based on Visual.srgbCapable when
  on desktop GL.

v4: - Use PIPE_FORMAT_B8G8R8A8_SRGB to check for the capability, since this
  is also the format that is used top check for EGL_KHR_gl_colorspace
  support.  virgl on a GLES host usually doesn't provide this format but
  one can make it available to signal that the host supports this
  extension.

v5: - drop check for PIPE_FORMAT_B8G8R8A8_SRGB in favour of using the new 
  PIPE_CAP_SRGB_WRITE_CONTROL cap flag.
- enable EXT_sRGB based on the sRGB formats supported and 
  EXT_framebuffer_sRGB by checking for the caps .

v6: - Use the CAPS name PIPE_CAP_DEST_SURFACE_SRGB_CONTROL

Signed-off-by: Gert Wollny 
---
 src/mesa/state_tracker/st_cb_fbo.c |  4 +--
 src/mesa/state_tracker/st_extensions.c |  6 -
 src/mesa/state_tracker/st_format.c |  2 +-
 src/mesa/state_tracker/st_manager.c| 37 --
 4 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_fbo.c 
b/src/mesa/state_tracker/st_cb_fbo.c
index 0e535257cb..49a989f126 100644
--- a/src/mesa/state_tracker/st_cb_fbo.c
+++ b/src/mesa/state_tracker/st_cb_fbo.c
@@ -139,7 +139,7 @@ st_renderbuffer_alloc_storage(struct gl_context * ctx,
/* If an sRGB framebuffer is unsupported, sRGB formats behave like linear
 * formats.
 */
-   if (!ctx->Extensions.EXT_framebuffer_sRGB) {
+   if (!ctx->Extensions.EXT_sRGB) {
   internalFormat = _mesa_get_linear_internalformat(internalFormat);
}
 
@@ -656,7 +656,7 @@ st_validate_attachment(struct gl_context *ctx,
/* If the encoding is sRGB and sRGB rendering cannot be enabled,
 * check for linear format support instead.
 * Later when we create a surface, we change the format to a linear one. */
-   if (!ctx->Extensions.EXT_framebuffer_sRGB &&
+   if (!ctx->Extensions.EXT_sRGB &&
_mesa_get_format_color_encoding(texFormat) == GL_SRGB) {
   const mesa_format linearFormat = _mesa_get_srgb_format_linear(texFormat);
   format = st_mesa_format_to_pipe_format(st_context(ctx), linearFormat);
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 16889074f6..15f22ecf15 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -786,7 +786,7 @@ void st_init_extensions(struct pipe_screen *screen,
   PIPE_FORMAT_B10G10R10A2_UINT },
  GL_TRUE }, /* at least one format must be supported */
 
-  { { o(EXT_framebuffer_sRGB) },
+  { { o(EXT_sRGB) },
 { PIPE_FORMAT_A8B8G8R8_SRGB,
   PIPE_FORMAT_B8G8R8A8_SRGB,
   PIPE_FORMAT_R8G8B8A8_SRGB },
@@ -1316,6 +1316,10 @@ void st_init_extensions(struct pipe_screen *screen,
   extensions->ARB_texture_buffer_object_rgb32 &&
   extensions->ARB_shader_image_load_store;
 
+   extensions->EXT_framebuffer_sRGB =
+ screen->get_param(screen, PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) &&
+ extensions->EXT_sRGB;
+
/* Unpacking a varying in the fragment shader costs 1 texture indirection.
 * If the number of available texture indirections is very limited, then we
 * prefer to disable varying packing rather than run the risk of varying
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index caddd76c5d..aacb878828 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -2457,7 +2457,7 @@ st_QuerySamplesForFormat(struct gl_context *ctx, GLenum 
target,
/* If an sRGB framebuffer is unsupported, sRGB formats behave like linear
 * formats.
 */
-   if (!ctx->Extensions.EXT_framebuffer_sRGB) {
+   

[Mesa-dev] [PATCH v6 7/8] mesa/main/version: Lower the requirements for GLES 3.0

[Gert Wollny]

From: Gert Wollny 

GLES 3.0 does not actually require support for EXT_framebuffer_sRGB, it
only needs support for sRGB attachments to framebuffers and framebuffer
objects as defined in ARB_framebuffer_objects.

v2: Clarify that ARB_framebuffer_objects is needed.

Signed-off-by: Gert Wollny 
---
Note, that for GLES 2.0 one would actually need to check for 
EXT_framebuffer_object here, but this extension is not handled in mesa.
ARB_framebuffer_objects = EXT_framebuffer_object + 
  multi-sample target + 
  differently sizes attachments. 
 src/mesa/main/version.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 610ba2f08c..5709d283f3 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -512,8 +512,8 @@ compute_version_es2(const struct gl_extensions *extensions,
  extensions->ARB_texture_float &&
  extensions->ARB_texture_rg &&
  extensions->ARB_depth_buffer_float &&
- /* extensions->ARB_framebuffer_object && */
- extensions->EXT_framebuffer_sRGB &&
+ extensions->ARB_framebuffer_object &&
+ extensions->EXT_sRGB &&
  extensions->EXT_packed_float &&
  extensions->EXT_texture_array &&
  extensions->EXT_texture_shared_exponent &&
-- 
2.18.1

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[Mesa-dev] [PATCH v6 6/8] mesa/main: Use flag for EXT_sRGB instead of EXT_framebuffer_sRGB where possible

[Gert Wollny]

From: Gert Wollny 

All drivers that support EXT_framebuffer_sRGB also support EXT_sRGB, but
in order to keep this commit minimal, and not to break any drivers both
flags are checked.

v2: - Use only EXT_sRGB (Ilia Mirkin)
- Move adding the flag EXT_sRGB to gl_extensions to a separate patch

Signed-off-by: Gert Wollny 
---
 src/mesa/main/fbobject.c| 2 +-
 src/mesa/main/formatquery.c | 2 +-
 src/mesa/main/framebuffer.c | 2 +-
 src/mesa/main/teximage.c| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 68e0daf342..7d45ce43f4 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -4253,7 +4253,7 @@ get_framebuffer_attachment_parameter(struct gl_context 
*ctx,
  }
   }
   else {
- if (ctx->Extensions.EXT_framebuffer_sRGB) {
+ if (ctx->Extensions.EXT_sRGB) {
 *params =
_mesa_get_format_color_encoding(att->Renderbuffer->Format);
  }
diff --git a/src/mesa/main/formatquery.c b/src/mesa/main/formatquery.c
index 84b5f512ba..3b0f6dafad 100644
--- a/src/mesa/main/formatquery.c
+++ b/src/mesa/main/formatquery.c
@@ -1241,7 +1241,7 @@ _mesa_GetInternalformativ(GLenum target, GLenum 
internalformat, GLenum pname,
   break;
 
case GL_SRGB_WRITE:
-  if (!_mesa_has_EXT_framebuffer_sRGB(ctx) ||
+  if (!ctx->Extensions.EXT_sRGB ||
   !_mesa_is_color_format(internalformat)) {
  goto end;
   }
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index 10dd2fde44..0abfdd8390 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -459,7 +459,7 @@ _mesa_update_framebuffer_visual(struct gl_context *ctx,
 fb->Visual.rgbBits = fb->Visual.redBits
+ fb->Visual.greenBits + fb->Visual.blueBits;
 if (_mesa_get_format_color_encoding(fmt) == GL_SRGB)
-fb->Visual.sRGBCapable = ctx->Extensions.EXT_framebuffer_sRGB;
+fb->Visual.sRGBCapable = ctx->Extensions.EXT_sRGB;
 break;
  }
   }
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 6805b47c72..3c9c8ada99 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -2438,7 +2438,7 @@ copytexture_error_check( struct gl_context *ctx, GLuint 
dimensions,
   bool rb_is_srgb = false;
   bool dst_is_srgb = false;
 
-  if (ctx->Extensions.EXT_framebuffer_sRGB &&
+  if (ctx->Extensions.EXT_sRGB &&
   _mesa_get_format_color_encoding(rb->Format) == GL_SRGB) {
  rb_is_srgb = true;
   }
-- 
2.18.1

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[Mesa-dev] [PATCH v6 1/8] Gallium: Add new CAPS to indicate whether a driver can switch SRGB write

[Gert Wollny]

From: Gert Wollny 

Add a new cap that indicates whether the drivers supports
enabling/disabling the conversion from linear space to sRGB
for a framebuffer attachment. In Driver terms that this CAP indicates
whether the driver can switch between a linear and and a sRGB surface
format for draw destinations without changing the surface itself.

v2: rename CAP to DEST_SURFACE_SRGB_CONTROL to reflect its
purpouse better (pointed out by Ilia Mirkin)
Signed-off-by: Gert Wollny 
---
 src/gallium/auxiliary/util/u_screen.c | 3 +++
 src/gallium/docs/source/screen.rst| 3 +++
 src/gallium/include/pipe/p_defines.h  | 1 +
 3 files changed, 7 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_screen.c 
b/src/gallium/auxiliary/util/u_screen.c
index 73dbbee94a..b737375ee0 100644
--- a/src/gallium/auxiliary/util/u_screen.c
+++ b/src/gallium/auxiliary/util/u_screen.c
@@ -326,6 +326,9 @@ u_pipe_screen_get_param_defaults(struct pipe_screen 
*pscreen,
case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
   return 2047;
 
+   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
+  return 1;
+
default:
   unreachable("bad PIPE_CAP_*");
}
diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 0abd164494..dbdf9e94d1 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -477,6 +477,9 @@ subpixel precision bias in bits during conservative 
rasterization.
   0 means no limit.
 * ``PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET``: The maximum supported value for
   of pipe_vertex_element::src_offset.
+* ``PIPE_CAP_DEST_SURFACE_SRGB_CONTROL``: Indicates whether the drivers
+  supports switching the format between sRGB and linear for a surface that is
+  used as destination in draw and blit calls.
 
 .. _pipe_capf:
 
diff --git a/src/gallium/include/pipe/p_defines.h 
b/src/gallium/include/pipe/p_defines.h
index 693f041b1d..c8eaad0104 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -826,6 +826,7 @@ enum pipe_cap
PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS,
PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET,
PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET,
+   PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
 };
 
 /**
-- 
2.18.1

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[Mesa-dev] [PATCH v6 2/8] virgl: Set sRGB write control CAP based on host capabilities

[Gert Wollny]

From: Gert Wollny 

v2: - Use the renamed CAPS
- add assertions to make sure that mesa doesn't try to switch
  destination surface formats when it is not supported. (Ilia Mirkin)

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/virgl/virgl_context.c | 10 ++
 src/gallium/drivers/virgl/virgl_hw.h  |  1 +
 src/gallium/drivers/virgl/virgl_screen.c  |  2 ++
 3 files changed, 13 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index 96932c473d..f26edc277f 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -245,6 +245,11 @@ static struct pipe_surface *virgl_create_surface(struct 
pipe_context *ctx,
if (!surf)
   return NULL;
 
+   assert(ctx->screen->get_param(ctx->screen,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
+  (util_format_is_srgb(templ->format) ==
+   util_format_is_srgb(resource->format)));
+
res->clean = FALSE;
handle = virgl_object_assign_handle();
pipe_reference_init(>base.reference, 1);
@@ -961,6 +966,11 @@ static void virgl_blit(struct pipe_context *ctx,
struct virgl_resource *dres = virgl_resource(blit->dst.resource);
struct virgl_resource *sres = virgl_resource(blit->src.resource);
 
+   assert(ctx->screen->get_param(ctx->screen,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
+  (util_format_is_srgb(blit->dst.resource->format) ==
+util_format_is_srgb(blit->dst.format)));
+
dres->clean = FALSE;
virgl_encode_blit(vctx, dres, sres,
 blit);
diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index e682c750e7..7b4c063f35 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -232,6 +232,7 @@ enum virgl_formats {
 #define VIRGL_CAP_TEXTURE_BARRIER  (1 << 12)
 #define VIRGL_CAP_TGSI_COMPONENTS  (1 << 13)
 #define VIRGL_CAP_GUEST_MAY_INIT_LOG   (1 << 14)
+#define VIRGL_CAP_SRGB_WRITE_CONTROL   (1 << 15)
 
 /* virgl bind flags - these are compatible with mesa 10.5 gallium.
  * but are fixed, no other should be passed to virgl either.
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index e71883b06f..6fbe711cbd 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -341,6 +341,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
   return 0;
case PIPE_CAP_NATIVE_FENCE_FD:
   return 0;
+   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
+  return vscreen->caps.caps.v2.capability_bits & 
VIRGL_CAP_SRGB_WRITE_CONTROL;
default:
   return u_pipe_screen_get_param_defaults(screen, param);
}
-- 
2.18.1

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[Mesa-dev] [PATCH v6 4/8] i965: Set flag for EXT_sRGB

[Gert Wollny]

From: Gert Wollny 

Signed-off-by: Gert Wollny 
---
 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index d7e02efb54..ca369e39f2 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -104,6 +104,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_point_parameters = true;
ctx->Extensions.EXT_provoking_vertex = true;
ctx->Extensions.EXT_render_snorm = true;
+   ctx->Extensions.EXT_sRGB = true;
ctx->Extensions.EXT_stencil_two_side = true;
ctx->Extensions.EXT_texture_array = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
-- 
2.18.1

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[Mesa-dev] [PATCH v6 0/8] Add and enable extension EXT_sRGB_write_control

[Gert Wollny]

From: Gert Wollny 

Dear all, 

after the RFC and Ilias comments I reworked the series another time.  
Changes with respect to the RFC are 
  - renaming the new CAP 
  - reordering of the patches that no double checking of 
EXT_sRGB and EXT_framebuffer_sRGB is needed. 

thanks for reviewing, 
Gert

Gert Wollny (8):
  Gallium: Add new CAPS to indicate whether a driver can switch SRGB
write
  virgl: Set sRGB write control CAP based on host capabilities
  mesa:main: Add flag for EXT_sRGB to gl_extensions
  i965: Set flag for EXT_sRGB
  mesa/st: rework support for sRGB framebuffer attachements
  mesa/main: Use flag for EXT_sRGB instead of EXT_framebuffer_sRGB where
possible
  mesa/main/version: Lower the requirements for GLES 3.0
  mesa/main: Expose EXT_sRGB_write_control

 src/gallium/auxiliary/util/u_screen.c|  3 ++
 src/gallium/docs/source/screen.rst   |  3 ++
 src/gallium/drivers/virgl/virgl_context.c| 10 ++
 src/gallium/drivers/virgl/virgl_hw.h |  1 +
 src/gallium/drivers/virgl/virgl_screen.c |  2 ++
 src/gallium/include/pipe/p_defines.h |  1 +
 src/mesa/drivers/dri/i965/intel_extensions.c |  1 +
 src/mesa/main/enable.c   |  4 ---
 src/mesa/main/extensions_table.h |  1 +
 src/mesa/main/fbobject.c |  2 +-
 src/mesa/main/formatquery.c  |  2 +-
 src/mesa/main/framebuffer.c  |  2 +-
 src/mesa/main/get_hash_params.py |  4 ++-
 src/mesa/main/mtypes.h   |  1 +
 src/mesa/main/teximage.c |  2 +-
 src/mesa/main/version.c  |  4 +--
 src/mesa/state_tracker/st_cb_fbo.c   |  4 +--
 src/mesa/state_tracker/st_extensions.c   |  6 +++-
 src/mesa/state_tracker/st_format.c   |  2 +-
 src/mesa/state_tracker/st_manager.c  | 37 
 20 files changed, 63 insertions(+), 29 deletions(-)

-- 
2.18.1

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[Mesa-dev] [PATCH v4] virgl: native fence fd support

[Robert Foss]

Following the support for fences on the virtio driver add support
for native fence on virgl. This was somewhat based on the freedeno one.

Signed-off-by: Gustavo Padovan 
Signed-off-by: Robert Foss 
---

This patch has been tested using Qemu & Virglrenderer.

Linux virtgpu fences branch:
https://gitlab.collabora.com/robertfoss/linux/tree/virtio_fences_v5

This branch:
https://gitlab.collabora.com/robertfoss/mesa/tree/virtio_fences_v4

Changes since v3:
 - Emil: Replaced driver_version() winsys func. with supports_fence variable
 - Emil: Replaced virgl_fence_server_sync() assert with it
 - Emil: Refactored virgl_fence_server_sync() to use sync_accumulate()

Changes since v2:
 - Add fence creation on flush


 src/gallium/drivers/virgl/virgl_context.c | 46 --
 src/gallium/drivers/virgl/virgl_screen.c  | 12 ++-
 src/gallium/drivers/virgl/virgl_winsys.h  | 14 +++-
 .../winsys/virgl/drm/virgl_drm_winsys.c   | 84 ++-
 .../winsys/virgl/drm/virgl_drm_winsys.h   |  2 +
 src/gallium/winsys/virgl/drm/virtgpu_drm.h| 14 +++-
 .../winsys/virgl/vtest/virgl_vtest_winsys.c   | 10 ++-
 7 files changed, 166 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index 96932c473d8..9be7775abd3 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -21,6 +21,7 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include "pipe/p_shader_tokens.h"
 
 #include "pipe/p_context.h"
@@ -709,13 +710,20 @@ static void virgl_draw_vbo(struct pipe_context *ctx,
 
 }
 
-static void virgl_flush_eq(struct virgl_context *ctx, void *closure)
+static void virgl_flush_eq(struct virgl_context *ctx, void *closure,
+  struct pipe_fence_handle **fence)
 {
struct virgl_screen *rs = virgl_screen(ctx->base.screen);
+   int out_fence_fd = -1;
 
/* send the buffer to the remote side for decoding */
ctx->num_transfers = ctx->num_draws = 0;
-   rs->vws->submit_cmd(rs->vws, ctx->cbuf);
+
+   rs->vws->submit_cmd(rs->vws, ctx->cbuf, ctx->cbuf->in_fence_fd,
+   ctx->cbuf->needs_out_fence_fd ? _fence_fd : NULL);
+
+   if (fence)
+  *fence = rs->vws->cs_create_fence(rs->vws, out_fence_fd);
 
virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 
@@ -728,11 +736,10 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
enum pipe_flush_flags flags)
 {
struct virgl_context *vctx = virgl_context(ctx);
-   struct virgl_screen *rs = virgl_screen(ctx->screen);
struct virgl_buffer *buf, *tmp;
 
-   if (fence)
-  *fence = rs->vws->cs_create_fence(rs->vws);
+   if (flags & PIPE_FLUSH_FENCE_FD)
+   vctx->cbuf->needs_out_fence_fd = true;
 
LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, >to_flush_bufs, flush_list) {
   struct pipe_resource *res = >base.u.b;
@@ -742,7 +749,13 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
   pipe_resource_reference(, NULL);
 
}
-   virgl_flush_eq(vctx, vctx);
+   virgl_flush_eq(vctx, vctx, fence);
+
+   if (vctx->cbuf->in_fence_fd != -1) {
+  close(vctx->cbuf->in_fence_fd);
+  vctx->cbuf->in_fence_fd = -1;
+   }
+   vctx->cbuf->needs_out_fence_fd = false;
 }
 
 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context 
*ctx,
@@ -1016,6 +1029,23 @@ static void virgl_set_shader_buffers(struct pipe_context 
*ctx,
virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
 }
 
+static void virgl_create_fence_fd(struct pipe_context *ctx,
+   struct pipe_fence_handle **fence, int fd)
+{
+   struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+   *fence = rs->vws->cs_create_fence(rs->vws, fd);
+}
+
+static void virgl_fence_server_sync(struct pipe_context *ctx,
+   struct pipe_fence_handle *fence)
+{
+   struct virgl_context *vctx = virgl_context(ctx);
+   struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+   rs->vws->fence_server_sync(rs->vws, vctx->cbuf, fence);
+}
+
 static void virgl_set_shader_images(struct pipe_context *ctx,
 enum pipe_shader_type shader,
 unsigned start_slot, unsigned count,
@@ -1108,7 +1138,7 @@ virgl_context_destroy( struct pipe_context *ctx )
vctx->framebuffer.zsbuf = NULL;
vctx->framebuffer.nr_cbufs = 0;
virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
-   virgl_flush_eq(vctx, vctx);
+   virgl_flush_eq(vctx, vctx, NULL);
 
rs->vws->cmd_buf_destroy(vctx->cbuf);
if (vctx->uploader)
@@ -1244,6 +1274,8 @@ struct pipe_context *virgl_context_create(struct 
pipe_screen *pscreen,
vctx->base.resource_copy_region = virgl_resource_copy_region;
vctx->base.flush_resource = virgl_flush_resource;
vctx->base.blit =  virgl_blit;
+   vctx->base.create_fence_fd = virgl_create_fence_fd;
+   

Re: [Mesa-dev] [PATCH 0/8] intel: Move shared/SSBO access lowering to NIR

[Samuel Iglesias Gonsálvez]

On 14/11/2018 22:38, Jason Ekstrand wrote:
> I just sent one more, "nir/lower_io: Add shared to get_io_offset_src"
> that's required for the pass to apply properly to shared vairables.
> 

I have reviewed it too.

> Do we have any testing of shared variables with anything other than 32
> bits?  Do we even test 64 bits?  I'm begining to think that there are
> basically zero tests for anything other than 32-bit. :(
> 

We checked CTS and piglit and we have not found any OpenGL or Vulkan
shared variable test with anything other than 32 bits :-(

Sam

> On Wed, Nov 14, 2018 at 5:48 AM Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
> 
> Thanks a lot for this work. Patches 1-7 are,
> 
>   Reviewed-by: Samuel Iglesias Gonsálvez  >
> 
> I will review patch 8 later, probably tomorrow.
> 
> Sam
> 
> On 14/11/2018 00:23, Jason Ekstrand wrote:
> > In order to properly do all the different kinds of SSBO and SLM
> writes that
> > we have in GL and Vulkan, we have to do some lowering.  The hardware
> > doesn't have instructions for writing a N-bit vecM with an arbitrary
> > write-mask.  Instead, we have byte scattered messages which work on a
> > scalar byte, word, or dword at an unaligned address and untyped
> surface
> > messages which work on a 32-bit vecN.  All SSBO and SLM access has
> to be
> > lowered to one of these two things.
> >
> > Previously we did this in the back-end and had separate copies for
> fs and
> > vec4.  This works but it was fairly heavily tied to the
> fs_surface_builder
> > and the way we emit typed load/store ops.  I've been interested in
> wiring
> > up the A64 messages for doing "global" reads and writes and they
> will need
> > exactly the same lowering but I'm not at all convinced I want to
> shove them
> > through the same emit_untyped_read/write helpers we have today. 
> In any
> > case, this lets us share code between vec4 and fs and I think the
> > implementation is over-all cleaner for it.  This series has a few
> other
> > advantages beyond just code sharing:
> >
> >  1) The new splitting code acts on ranges of bytes and is able to
> combine
> >     loads/stores in more cases than the old code could.  For
> example, an
> >     indirect u8vec3 load is now just a single dword load where we
> throw
> >     away the last 16 bits.  Another example is that a u16vec4
> write with a
> >     YZ writemask is now written with a single unaligned dword store.
> >
> >  2) OpBitcast in SPIR-V now works correctly on 8-bit types.
> >
> >  3) Writes to 8 and 16-bit shared variables should now work.
> >
> > Cc: Samuel Iglesias Gonsálvez  >
> > Cc: Jose Maria Casanova Crespo  >
> >
> > Jason Ekstrand (8):
> >   nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16
> >   nir/builder: Assert that intN_t immediates fit
> >   nir/builder: Add iadd_imm and imul_imm helpers
> >   nir/builder: Add a nir_pack/unpack/bitcast helpers
> >   nir/spirv: Force 32-bit for UBO and SSBO Booleans
> >   nir/glsl: Force 32-bit for UBO and SSBO Booleans
> >   nir: Add alignment parameters to SSBO, UBO, and shared access
> >   intel/compiler: Lower SSBO and shared loads/stores in NIR
> >
> >  src/compiler/glsl/glsl_to_nir.cpp             |  31 +-
> >  src/compiler/nir/nir.h                        |  41 ++
> >  src/compiler/nir/nir_builder.h                | 142 +++
> >  src/compiler/nir/nir_intrinsics.py            |  26 +-
> >  src/compiler/nir/nir_lower_alu_to_scalar.c    |   1 +
> >  src/compiler/nir/nir_lower_atomics_to_ssbo.c  |   4 +
> >  src/compiler/nir/nir_lower_io.c               |   5 +-
> >  src/compiler/nir/nir_print.c                  |   2 +
> >  src/compiler/spirv/spirv_to_nir.c             |   2 +
> >  src/compiler/spirv/vtn_alu.c                  | 101 ++---
> >  src/compiler/spirv/vtn_variables.c            |  30 +-
> >  src/intel/Makefile.sources                    |   1 +
> >  src/intel/compiler/brw_fs_nir.cpp             | 381
> --
> >  src/intel/compiler/brw_nir.c                  |   2 +
> >  src/intel/compiler/brw_nir.h                  |   2 +
> >  .../brw_nir_lower_mem_access_bit_sizes.c      | 313 ++
> >  src/intel/compiler/brw_vec4_nir.cpp           | 126 +-
> >  src/intel/compiler/meson.build                |   1 +
> >  18 files changed, 702 insertions(+), 509 deletions(-)
> >  create mode 100644
> src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c
> >
> 



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Re: [Mesa-dev] [PATCH 1/2] radv/winsys: remove the max IBs per submit limit for the fallback path

[Bas Nieuwenhuizen]

Nice, seems to halve CPU cost of submitting 100 command buffers in 1
submit with the simultaneous use flag set.

Reviewed-by: Bas Nieuwenhuizen 

for the series.
On Thu, Nov 15, 2018 at 11:27 AM Samuel Pitoiset
 wrote:
>
> The chained submission is the fastest path and it should now
> be used more often than before. This removes some EOP events.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 103 ++
>  1 file changed, 55 insertions(+), 48 deletions(-)
>
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
> b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> index abc4f3903d..f2d07a54db 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> @@ -865,66 +865,73 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct 
> radeon_winsys_ctx *_ctx,
> struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
> struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
> amdgpu_bo_list_handle bo_list;
> -   struct amdgpu_cs_request request;
> -   bool emit_signal_sem = sem_info->cs_emit_signal;
> +   struct amdgpu_cs_request request = {};
> +   struct amdgpu_cs_ib_info *ibs;
> +   struct radv_amdgpu_cs *cs0;
> +   unsigned number_of_ibs;
> +
> assert(cs_count);
> +   cs0 = radv_amdgpu_cs(cs_array[0]);
>
> -   for (unsigned i = 0; i < cs_count;) {
> -   struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
> -   struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
> -   struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs 
> : initial_preamble_cs;
> -   unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - 
> !!preamble_cs,
> -   cs_count - i);
> +   /* Compute the number of IBs for this submit. */
> +   number_of_ibs = cs_count + !!initial_preamble_cs;
>
> -   memset(, 0, sizeof(request));
> +   /* Create a buffer object list. */
> +   r = radv_amdgpu_create_bo_list(cs0->ws, _array[0], cs_count, NULL, 
> 0,
> +  initial_preamble_cs, radv_bo_list,
> +  _list);
> +   if (r) {
> +   fprintf(stderr, "amdgpu: buffer list creation failed "
> +   "for the fallback submission (%d)\n", r);
> +   return r;
> +   }
>
> -   r = radv_amdgpu_create_bo_list(cs0->ws, _array[i], cnt, 
> NULL, 0,
> -  preamble_cs, radv_bo_list, 
> _list);
> -   if (r) {
> -   fprintf(stderr, "amdgpu: buffer list creation failed "
> -   "for the fallback submission (%d)\n", 
> r);
> -   return r;
> -   }
> +   ibs = malloc(number_of_ibs * sizeof(*ibs));
> +   if (!ibs) {
> +   if (bo_list)
> +   amdgpu_bo_list_destroy(bo_list);
> +   return -ENOMEM;
> +   }
>
> -   request.ip_type = cs0->hw_ip;
> -   request.ring = queue_idx;
> -   request.resources = bo_list;
> -   request.number_of_ibs = cnt + !!preamble_cs;
> -   request.ibs = ibs;
> -   request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, 
> queue_idx);
> +   /* Configure the CS request. */
> +   if (initial_preamble_cs)
> +   ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
>
> -   if (preamble_cs) {
> -   ibs[0] = radv_amdgpu_cs(preamble_cs)->ib;
> -   }
> +   for (unsigned i = 0; i < cs_count; i++) {
> +   struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
>
> -   for (unsigned j = 0; j < cnt; ++j) {
> -   struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i 
> + j]);
> -   ibs[j + !!preamble_cs] = cs->ib;
> +   ibs[i + !!initial_preamble_cs] = cs->ib;
>
> -   if (cs->is_chained) {
> -   *cs->ib_size_ptr -= 4;
> -   cs->is_chained = false;
> -   }
> +   if (cs->is_chained) {
> +   *cs->ib_size_ptr -= 4;
> +   cs->is_chained = false;
> }
> +   }
>
> -   sem_info->cs_emit_signal = (i == cs_count - cnt) ? 
> emit_signal_sem : false;
> -   r = radv_amdgpu_cs_submit(ctx, , sem_info);
> -   if (r) {
> -   if (r == -ENOMEM)
> -   fprintf(stderr, "amdgpu: Not enough memory 
> for command submission.\n");
> -   else
> -   fprintf(stderr, "amdgpu: The CS has been 
> rejected, "
> -   

Re: [Mesa-dev] [PATCH] nir/lower_io: Add shared to get_io_offset_src

[Samuel Iglesias Gonsálvez]

Reviewed-by: Samuel Iglesias Gonsálvez 

On 14/11/2018 22:36, Jason Ekstrand wrote:
> ---
>  src/compiler/nir/nir_lower_io.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
> index f3377eaec8f..64424307812 100644
> --- a/src/compiler/nir/nir_lower_io.c
> +++ b/src/compiler/nir/nir_lower_io.c
> @@ -538,6 +538,7 @@ nir_get_io_offset_src(nir_intrinsic_instr *instr)
> switch (instr->intrinsic) {
> case nir_intrinsic_load_input:
> case nir_intrinsic_load_output:
> +   case nir_intrinsic_load_shared:
> case nir_intrinsic_load_uniform:
>return >src[0];
> case nir_intrinsic_load_ubo:
> @@ -546,6 +547,7 @@ nir_get_io_offset_src(nir_intrinsic_instr *instr)
> case nir_intrinsic_load_per_vertex_output:
> case nir_intrinsic_load_interpolated_input:
> case nir_intrinsic_store_output:
> +   case nir_intrinsic_store_shared:
>return >src[1];
> case nir_intrinsic_store_ssbo:
> case nir_intrinsic_store_per_vertex_output:
> 





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Re: [Mesa-dev] [PATCH 8/8] intel/compiler: Lower SSBO and shared loads/stores in NIR

[Samuel Iglesias Gonsálvez]

On 14/11/2018 00:23, Jason Ekstrand wrote:
> We have a bunch of code to do this in the back-end compiler but it's
> fairly specific to typed surface messages and the way we emit them.
> This breaks it out into NIR were it's easier to do things a bit more
> generally.  It also means we can easily share the code between the bec4

vec4

Reviewed-by: Samuel Iglesias Gonsálvez 

> and FS back-ends if we wish.
> ---
>  src/intel/Makefile.sources|   1 +
>  src/intel/compiler/brw_fs_nir.cpp | 381 --
>  src/intel/compiler/brw_nir.c  |   2 +
>  src/intel/compiler/brw_nir.h  |   2 +
>  .../brw_nir_lower_mem_access_bit_sizes.c  | 313 ++
>  src/intel/compiler/brw_vec4_nir.cpp   | 126 +-
>  src/intel/compiler/meson.build|   1 +
>  7 files changed, 421 insertions(+), 405 deletions(-)
>  create mode 100644 src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c
> 
> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> index 4da887f7ed2..5e7d32293b7 100644
> --- a/src/intel/Makefile.sources
> +++ b/src/intel/Makefile.sources
> @@ -85,6 +85,7 @@ COMPILER_FILES = \
>   compiler/brw_nir_attribute_workarounds.c \
>   compiler/brw_nir_lower_cs_intrinsics.c \
>   compiler/brw_nir_lower_image_load_store.c \
> + compiler/brw_nir_lower_mem_access_bit_sizes.c \
>   compiler/brw_nir_opt_peephole_ffma.c \
>   compiler/brw_nir_tcs_workarounds.c \
>   compiler/brw_packed_float.c \
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index 2b36171136e..84d0c6be6c3 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -26,6 +26,7 @@
>  #include "brw_fs_surface_builder.h"
>  #include "brw_nir.h"
>  #include "util/u_math.h"
> +#include "util/bitscan.h"
>  
>  using namespace brw;
>  using namespace brw::surface_access;
> @@ -2250,107 +2251,6 @@ fs_visitor::get_indirect_offset(nir_intrinsic_instr 
> *instr)
> return get_nir_src(*offset_src);
>  }
>  
> -static void
> -do_untyped_vector_read(const fs_builder ,
> -   const fs_reg dest,
> -   const fs_reg surf_index,
> -   const fs_reg offset_reg,
> -   unsigned num_components)
> -{
> -   if (type_sz(dest.type) <= 2) {
> -  assert(dest.stride == 1);
> -  boolean is_const_offset = offset_reg.file == BRW_IMMEDIATE_VALUE;
> -
> -  if (is_const_offset) {
> - uint32_t start = offset_reg.ud & ~3;
> - uint32_t end = offset_reg.ud + num_components * type_sz(dest.type);
> - end = ALIGN(end, 4);
> - assert (end - start <= 16);
> -
> - /* At this point we have 16-bit component/s that have constant
> -  * offset aligned to 4-bytes that can be read with untyped_reads.
> -  * untyped_read message requires 32-bit aligned offsets.
> -  */
> - unsigned first_component = (offset_reg.ud & 3) / type_sz(dest.type);
> - unsigned num_components_32bit = (end - start) / 4;
> -
> - fs_reg read_result =
> -emit_untyped_read(bld, surf_index, brw_imm_ud(start),
> -  1 /* dims */,
> -  num_components_32bit,
> -  BRW_PREDICATE_NONE);
> - shuffle_from_32bit_read(bld, dest, read_result, first_component,
> - num_components);
> -  } else {
> - fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
> - for (unsigned i = 0; i < num_components; i++) {
> -if (i == 0) {
> -   bld.MOV(read_offset, offset_reg);
> -} else {
> -   bld.ADD(read_offset, offset_reg,
> -   brw_imm_ud(i * type_sz(dest.type)));
> -}
> -/* Non constant offsets are not guaranteed to be aligned 32-bits
> - * so they are read using one byte_scattered_read message
> - * for each component.
> - */
> -fs_reg read_result =
> -   emit_byte_scattered_read(bld, surf_index, read_offset,
> -1 /* dims */, 1,
> -type_sz(dest.type) * 8 /* bit_size 
> */,
> -BRW_PREDICATE_NONE);
> -bld.MOV(offset(dest, bld, i),
> -subscript (read_result, dest.type, 0));
> - }
> -  }
> -   } else if (type_sz(dest.type) == 4) {
> -  fs_reg read_result = emit_untyped_read(bld, surf_index, offset_reg,
> - 1 /* dims */,
> - num_components,
> - BRW_PREDICATE_NONE);
> -  read_result.type = dest.type;
> -  for (unsigned i = 0; i < num_components; i++)
> - 

Re: [Mesa-dev] [ANNOUNCE] Mesa 18.2.5 release candidate

[Juan A. Suarez Romero]

On Tue, 2018-11-13 at 16:26 -0800, Matt Turner wrote:
> On Mon, Nov 12, 2018 at 8:35 AM Juan A. Suarez Romero
>  wrote:
> > Hello list,
> > 
> > The candidate for the Mesa 18.2.5 is now available. Currently we have:
> >  - 25 queued
> >  - 0 nominated (outstanding)
> >  - and 2 rejected patch
> 
> If it's not a big deal if would be convenient for me (for Gentoo) to
> have the following patches included in 18.2.5:
> 
> efb1ccadca89 ("util/ralloc: Make sizeof(linear_header) a multiple of 8")
>  - Maybe needs 7e3748c268cd ("util/ralloc: Switch from DEBUG to NDEBUG")
> 
> 4eab98b66e7d ("meson: fix libatomic tests")
> 
> and the patches to fix https://bugs.freedesktop.org/show_bug.cgi?id=105328#c8
> 
> Emil says that the needed commits are
> 
> 87c156183cd6 ("configure: install KHR/khrplatform.h when needed")
> e02f061b690d ("meson: install KHR/khrplatform.h when needed")
> f7d42ee7d319 ("include: update GL & GLES headers (v2)")
> 
> If they slip to 18.2.6 it's okay.
> 

Sorry for the delay. We had some troubles with the CI, but we have included
these commits in next 18.2.5 release.

Thanks!

J.A.

> Thanks!
> Matt
> 

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[Mesa-dev] [PATCH 2/2] radv/winsys: remove the max IBs per submit limit for the sysmem path

[Samuel Pitoiset]

This path will be eventually improved later but as it's only
used on SI (or with RADV_DEBUG=noibs), I'm not sure if that
matters much.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 46 ---
 1 file changed, 29 insertions(+), 17 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index f2d07a54db..d4de944753 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -295,15 +295,6 @@ static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, 
size_t min_size)
/* The maximum size in dwords has been reached,
 * try to allocate a new one.
 */
-   if (cs->num_old_cs_buffers + 1 >= 
AMDGPU_CS_MAX_IBS_PER_SUBMIT) {
-   /* TODO: Allow to submit more than 4 IBs. */
-   fprintf(stderr, "amdgpu: Maximum number of IBs "
-   "per submit reached.\n");
-   cs->failed = true;
-   cs->base.cdw = 0;
-   return;
-   }
-
cs->old_cs_buffers =
realloc(cs->old_cs_buffers,
(cs->num_old_cs_buffers + 1) * 
sizeof(*cs->old_cs_buffers));
@@ -966,30 +957,46 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
assert(cs_count);
 
for (unsigned i = 0; i < cs_count;) {
-   struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = 
{0};
-   unsigned number_of_ibs = 1;
-   struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = 
{0};
+   struct amdgpu_cs_ib_info *ibs;
+   struct radeon_winsys_bo **bos;
struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : 
initial_preamble_cs;
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
+   unsigned number_of_ibs;
uint32_t *ptr;
unsigned cnt = 0;
unsigned size = 0;
unsigned pad_words = 0;
 
-   if (cs->num_old_cs_buffers > 0) {
+   /* Compute the number of IBs for this submit. */
+   number_of_ibs = cs->num_old_cs_buffers + 1;
+
+   ibs = malloc(number_of_ibs * sizeof(*ibs));
+   if (!ibs)
+   return -ENOMEM;
+
+   bos = malloc(number_of_ibs * sizeof(*bos));
+   if (!bos) {
+   free(ibs);
+   return -ENOMEM;
+   }
+
+   if (number_of_ibs > 1) {
/* Special path when the maximum size in dwords has
 * been reached because we need to handle more than one
 * IB per submit.
 */
-   unsigned new_cs_count = cs->num_old_cs_buffers + 1;
-   struct radeon_cmdbuf 
*new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
+   struct radeon_cmdbuf **new_cs_array;
unsigned idx = 0;
 
+   new_cs_array = malloc(cs->num_old_cs_buffers *
+ sizeof(*new_cs_array));
+   assert(new_cs_array);
+
for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
new_cs_array[idx++] = >old_cs_buffers[j];
new_cs_array[idx++] = cs_array[i];
 
-   for (unsigned j = 0; j < new_cs_count; j++) {
+   for (unsigned j = 0; j < number_of_ibs; j++) {
struct radeon_cmdbuf *rcs = new_cs_array[j];
bool needs_preamble = preamble_cs && j == 0;
unsigned size = 0;
@@ -1027,8 +1034,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
ibs[j].ib_mc_address = 
radv_buffer_get_va(bos[j]);
}
 
-   number_of_ibs = new_cs_count;
cnt++;
+   free(new_cs_array);
} else {
if (preamble_cs)
size += preamble_cs->cdw;
@@ -1077,6 +1084,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
if (r) {
fprintf(stderr, "amdgpu: buffer list creation failed "
"for the sysmem submission (%d)\n", r);
+   free(ibs);
+   free(bos);
return r;
}
 
@@ -1106,6 

[Mesa-dev] [PATCH 1/2] radv/winsys: remove the max IBs per submit limit for the fallback path

[Samuel Pitoiset]

The chained submission is the fastest path and it should now
be used more often than before. This removes some EOP events.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 103 ++
 1 file changed, 55 insertions(+), 48 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index abc4f3903d..f2d07a54db 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -865,66 +865,73 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct 
radeon_winsys_ctx *_ctx,
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
amdgpu_bo_list_handle bo_list;
-   struct amdgpu_cs_request request;
-   bool emit_signal_sem = sem_info->cs_emit_signal;
+   struct amdgpu_cs_request request = {};
+   struct amdgpu_cs_ib_info *ibs;
+   struct radv_amdgpu_cs *cs0;
+   unsigned number_of_ibs;
+
assert(cs_count);
+   cs0 = radv_amdgpu_cs(cs_array[0]);
 
-   for (unsigned i = 0; i < cs_count;) {
-   struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
-   struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
-   struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : 
initial_preamble_cs;
-   unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - 
!!preamble_cs,
-   cs_count - i);
+   /* Compute the number of IBs for this submit. */
+   number_of_ibs = cs_count + !!initial_preamble_cs;
 
-   memset(, 0, sizeof(request));
+   /* Create a buffer object list. */
+   r = radv_amdgpu_create_bo_list(cs0->ws, _array[0], cs_count, NULL, 0,
+  initial_preamble_cs, radv_bo_list,
+  _list);
+   if (r) {
+   fprintf(stderr, "amdgpu: buffer list creation failed "
+   "for the fallback submission (%d)\n", r);
+   return r;
+   }
 
-   r = radv_amdgpu_create_bo_list(cs0->ws, _array[i], cnt, 
NULL, 0,
-  preamble_cs, radv_bo_list, 
_list);
-   if (r) {
-   fprintf(stderr, "amdgpu: buffer list creation failed "
-   "for the fallback submission (%d)\n", 
r);
-   return r;
-   }
+   ibs = malloc(number_of_ibs * sizeof(*ibs));
+   if (!ibs) {
+   if (bo_list)
+   amdgpu_bo_list_destroy(bo_list);
+   return -ENOMEM;
+   }
 
-   request.ip_type = cs0->hw_ip;
-   request.ring = queue_idx;
-   request.resources = bo_list;
-   request.number_of_ibs = cnt + !!preamble_cs;
-   request.ibs = ibs;
-   request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, 
queue_idx);
+   /* Configure the CS request. */
+   if (initial_preamble_cs)
+   ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
 
-   if (preamble_cs) {
-   ibs[0] = radv_amdgpu_cs(preamble_cs)->ib;
-   }
+   for (unsigned i = 0; i < cs_count; i++) {
+   struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
 
-   for (unsigned j = 0; j < cnt; ++j) {
-   struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + 
j]);
-   ibs[j + !!preamble_cs] = cs->ib;
+   ibs[i + !!initial_preamble_cs] = cs->ib;
 
-   if (cs->is_chained) {
-   *cs->ib_size_ptr -= 4;
-   cs->is_chained = false;
-   }
+   if (cs->is_chained) {
+   *cs->ib_size_ptr -= 4;
+   cs->is_chained = false;
}
+   }
 
-   sem_info->cs_emit_signal = (i == cs_count - cnt) ? 
emit_signal_sem : false;
-   r = radv_amdgpu_cs_submit(ctx, , sem_info);
-   if (r) {
-   if (r == -ENOMEM)
-   fprintf(stderr, "amdgpu: Not enough memory for 
command submission.\n");
-   else
-   fprintf(stderr, "amdgpu: The CS has been 
rejected, "
-   "see dmesg for more 
information.\n");
-   }
+   request.ip_type = cs0->hw_ip;
+   request.ring = queue_idx;
+   request.resources = bo_list;
+   request.number_of_ibs = number_of_ibs;
+   request.ibs = ibs;
+   request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
 
-   if (bo_list)
-   amdgpu_bo_list_destroy(bo_list);
+   /* Submit the 

[Mesa-dev] [PATCH v4] i965: Fix calculation of layers array length for isl_view

[Danylo Piliaiev]

Handle all cases in calculation of layers count for isl_view
taking into account texture view and image unit.
st_convert_image was taken as a reference.

When u->Layered is true the whole level is taken with respect to
image view. In other case only one layer is taken.

v3: (Józef Kucia and Ilia Mirkin)
- Rewrote patch by taking st_convert_image as a reference
- Removed now unused get_image_num_layers function
- Changed commit message

v4: (Jason Ekstrand)
- Added assert

Fixes: 5a8c8903
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856

Signed-off-by: Danylo Piliaiev 
Reviewed-by: Jason Ekstrand 
---
 .../drivers/dri/i965/brw_wm_surface_state.c   | 33 ++-
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8d21cf5fa7..3286c222e5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1499,18 +1499,6 @@ update_buffer_image_param(struct brw_context *brw,
param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
 }
 
-static unsigned
-get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
- unsigned level)
-{
-   if (target == GL_TEXTURE_CUBE_MAP)
-  return 6;
-
-   return target == GL_TEXTURE_3D ?
-  minify(mt->surf.logical_level0_px.depth, level) :
-  mt->surf.logical_level0_px.array_len;
-}
-
 static void
 update_image_surface(struct brw_context *brw,
  struct gl_image_unit *u,
@@ -1541,14 +1529,29 @@ update_image_surface(struct brw_context *brw,
   } else {
  struct intel_texture_object *intel_obj = intel_texture_object(obj);
  struct intel_mipmap_tree *mt = intel_obj->mt;
- const unsigned num_layers = u->Layered ?
-get_image_num_layers(mt, obj->Target, u->Level) : 1;
+
+ unsigned base_layer, num_layers;
+ if (u->Layered) {
+if (obj->Target == GL_TEXTURE_3D) {
+   base_layer = 0;
+   num_layers = minify(mt->surf.logical_level0_px.depth, u->Level);
+} else {
+   assert(obj->Immutable || obj->MinLayer == 0);
+   base_layer = obj->MinLayer;
+   num_layers = obj->Immutable ?
+obj->NumLayers :
+mt->surf.logical_level0_px.array_len;
+}
+ } else {
+base_layer = obj->MinLayer + u->_Layer;
+num_layers = 1;
+ }
 
  struct isl_view view = {
 .format = format,
 .base_level = obj->MinLevel + u->Level,
 .levels = 1,
-.base_array_layer = obj->MinLayer + u->_Layer,
+.base_array_layer = base_layer,
 .array_len = num_layers,
 .swizzle = ISL_SWIZZLE_IDENTITY,
 .usage = ISL_SURF_USAGE_STORAGE_BIT,
-- 
2.18.0

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[Mesa-dev] [PATCH] radv: don't force clearing the stencil aspect for LOAD_OP_DONT_CARE

[Samuel Pitoiset]

This has been initially added for a Sascha demo (ie. deferredshadows),
but as far I can tell this seems to no longer be needed.

No CTS changes on GFX9 and I didn't find a game that is affected.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8e0ed284d6..7940a8f128 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2344,9 +2344,6 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer 
*cmd_buffer,
if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
-   if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) 
&&
-   att->stencil_load_op == 
VK_ATTACHMENT_LOAD_OP_DONT_CARE)
-   clear_aspects |= 
VK_IMAGE_ASPECT_STENCIL_BIT;
}
if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
att->stencil_load_op == 
VK_ATTACHMENT_LOAD_OP_CLEAR) {
-- 
2.19.1

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Re: [Mesa-dev] [PATCH 2/2] radv: enable primitive binning by default

[Bas Nieuwenhuizen]

On Thu, 15 Nov 2018, 10:11 Samuel Pitoiset  After doing a bunch of benchmarks, primitive binning helps
> some games like The Talos Principle (+5%) or Serious Sam 2017
> (+3%). For other titles, either it doesn't change anything or
> it hurts very few (less than 1%).
>
> This only affects GFX9.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_debug.h  | 5 ++---
>  src/amd/vulkan/radv_device.c | 3 +--
>  2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
> index 397d567961..01712bd22c 100644
> --- a/src/amd/vulkan/radv_debug.h
> +++ b/src/amd/vulkan/radv_debug.h
> @@ -57,9 +57,8 @@ enum {
> RADV_PERFTEST_NO_BATCHCHAIN  =   0x1,
> RADV_PERFTEST_SISCHED=   0x2,
> RADV_PERFTEST_LOCAL_BOS  =   0x4,
> -   RADV_PERFTEST_BINNING =   0x8,
> -   RADV_PERFTEST_OUT_OF_ORDER   =  0x10,
> -   RADV_PERFTEST_DCC_MSAA   =  0x20,
> +   RADV_PERFTEST_OUT_OF_ORDER   =   0x8,
> +   RADV_PERFTEST_DCC_MSAA   =  0x10,
>  };
>
>  bool
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index b2078975a8..617886b8d8 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -466,7 +466,6 @@ static const struct debug_control
> radv_perftest_options[] = {
> {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
> {"sisched", RADV_PERFTEST_SISCHED},
> {"localbos", RADV_PERFTEST_LOCAL_BOS},
> -   {"binning", RADV_PERFTEST_BINNING},
> {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
> {NULL, 0}
>  };
> @@ -1635,7 +1634,7 @@ VkResult radv_CreateDevice(
> }
>
> device->pbb_allowed = device->physical_device->rad_info.chip_class
> >= GFX9 &&
> -   ((device->instance->perftest_flags &
> RADV_PERFTEST_BINNING) ||
> +   (!(device->instance->debug_flags &
> RADV_DEBUG_NOBINNING) ||
>  device->physical_device->rad_info.family ==
> CHIP_RAVEN ||
>  device->physical_device->rad_info.family ==
> CHIP_RAVEN2);
>

You can remove the Raven check since it is enabled by default.


With that

Reviewed-by: Bas Nieuwenhuizen 

for the series.


> --
> 2.19.1
>
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[Mesa-dev] [Bug 108742] Battlefield 4 in Wine Freezes when joining games since ~mesa-18.2.3

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=108742

--- Comment #1 from coolo...@gmail.com ---
Seems to definitely be a mesa issue and not llvm, built mesa 18.2.0 with latest
llvm and the issue does not occur. Will attempt to bisect

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Re: [Mesa-dev] [PATCH 10/9] bin/get-pick-list.sh: handle reverts prior to the branchpoint

[Juan A. Suarez Romero]

On Wed, 2018-11-14 at 18:52 +, Emil Velikov wrote:
> On Wed, 14 Nov 2018 at 18:51, Emil Velikov  wrote:
> > From: Emil Velikov 
> > 
> > Currently we detect when a breaking commit:
> >  - has landed in stable, and
> >  - is referenced by a untagged fix in master
> > 
> > Yet we did not consider the case of breaking commit:
> >  - prior to the branchpoint, and
> >  - is referenced by a untagged fix in master
> > 
> > Addressing the latter is extremely slow since due to the size of the
> > lookup.
> > 
> > That said, we can trivially use the existing is_sha_nomination()
> > helper to catch reverts.
> > 
> > Signed-off-by: Emil Velikov 
> 
> Juan,
> Please you skim over the updated series and this add-on patch?
> They've caught a few issues that may be present in 18.2.
> 

Sorry for the delay.

Reviewed-by: Juan A. Suarez 


> Emil
> 

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Re: [Mesa-dev] [PATCH 2/9] bin/get-pick-list.sh: prefix output with "[stable] "

[Juan A. Suarez Romero]

On Thu, 2018-11-08 at 15:05 +, Emil Velikov wrote:
> From: Emil Velikov 
> 
> With later commits we'll fold all the different scripts into one.
> Add the explicit prefix, so that we know the origin of the nomination
> 
> v2:
>  - pass the sha as argument to the function
>  - drop $tag = none an else statment (Juan)
>  - grep -q instead of using a variable (Eric)
>  - print the tag and commit oneline separately (Eric)
> 
> Signed-off-by: Emil Velikov 
> Reviewed-by: Eric Engestrom 
> ---
>  bin/get-pick-list.sh | 16 
>  1 file changed, 16 insertions(+)
> 
> diff --git a/bin/get-pick-list.sh b/bin/get-pick-list.sh
> index ba741cc4114..6ab2a54dd4c 100755
> --- a/bin/get-pick-list.sh
> +++ b/bin/get-pick-list.sh
> @@ -7,6 +7,14 @@
>  # $ bin/get-pick-list.sh
>  # $ bin/get-pick-list.sh > picklist
>  # $ bin/get-pick-list.sh | tee picklist
> +#
> +# The output is as follows:
> +# [nominaiton_type] commit_sha commit summary
  ^ nomination

> +
> +is_stable_nomination()
> +{
> + git show --summary "$1" | grep -q -i -o "CC:.*mesa-stable"
> +}
>  
>  # Use the last branchpoint as our limit for the search
>  latest_branchpoint=`git merge-base origin/master HEAD`
> @@ -32,6 +40,14 @@ do
>   continue
>   fi
>  
> + tag=none

 I think we don't need this "tag=none" anymore.

> + if is_stable_nomination "$sha"; then
> + tag=stable
> + else
> + continue
> + fi
> +
> + printf "[ %8s ] " "$tag"
>   git --no-pager show --summary --oneline $sha
>  done
>  

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Re: [Mesa-dev] [PATCH 2/2] radv: force-enable primitive binning for The Talos Principle

[Samuel Pitoiset]

On 11/15/18 10:07 AM, Bas Nieuwenhuizen wrote:

On Thu, Nov 15, 2018 at 9:06 AM Samuel Pitoiset
 wrote:




On 11/15/18 12:16 AM, Bas Nieuwenhuizen wrote:

On Wed, Nov 14, 2018 at 5:32 PM Samuel Pitoiset
 wrote:




On 11/14/18 5:28 PM, Bas Nieuwenhuizen wrote:

On Wed, Nov 14, 2018 at 5:26 PM Samuel Pitoiset
 wrote:


+5% in ultra settings for both 4k and 1080p.

Signed-off-by: Samuel Pitoiset 
---
src/amd/vulkan/radv_device.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b2078975a8..5d212201ec 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -495,6 +495,9 @@ radv_handle_per_app_options(struct radv_instance *instance,
*/
   instance->perftest_flags |= RADV_PERFTEST_SISCHED;
   }
+
+   if (!(instance->debug_flags & RADV_DEBUG_NOBINNING))
+   instance->perftest_flags |= RADV_PERFTEST_BINNING;


Just enable for everything? Unless you have something where it is clearly worse.


I want to enable it incrementally and whitelist games for now. It's
still unclear if this will help all games.


IMO we really should avoid to introduce whitelisting stuff. I tested
some games and while ti certainly did not help a lot of them (Talos
confirmed helped) I saw no statistically significant regressions.


What games did you test?


The usual benchmarkable suspects: dota2, RoTR, SotTR, F12017, DoW3, talos


Yeah, I can confirm that. Primitive binning enabled by default on the list!










   } else if (!strcmp(name, "DOOM_VFR")) {
   /* Work around a Doom VFR game bug */
   instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
--
2.19.1

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[Mesa-dev] [PATCH 1/2] radv: add a debug option for disabling primitive binning

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_debug.h  | 1 +
 src/amd/vulkan/radv_device.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 9fe4c3b740..397d567961 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -50,6 +50,7 @@ enum {
RADV_DEBUG_STARTUP   = 0x10,
RADV_DEBUG_CHECKIR   = 0x20,
RADV_DEBUG_NOTHREADLLVM  = 0x40,
+   RADV_DEBUG_NOBINNING = 0x80,
 };
 
 enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 145be67c85..b2078975a8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -451,6 +451,7 @@ static const struct debug_control radv_debug_options[] = {
{"startup", RADV_DEBUG_STARTUP},
{"checkir", RADV_DEBUG_CHECKIR},
{"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
+   {"nobinning", RADV_DEBUG_NOBINNING},
{NULL, 0}
 };
 
-- 
2.19.1

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[Mesa-dev] [PATCH 2/2] radv: enable primitive binning by default

[Samuel Pitoiset]

After doing a bunch of benchmarks, primitive binning helps
some games like The Talos Principle (+5%) or Serious Sam 2017
(+3%). For other titles, either it doesn't change anything or
it hurts very few (less than 1%).

This only affects GFX9.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_debug.h  | 5 ++---
 src/amd/vulkan/radv_device.c | 3 +--
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 397d567961..01712bd22c 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -57,9 +57,8 @@ enum {
RADV_PERFTEST_NO_BATCHCHAIN  =   0x1,
RADV_PERFTEST_SISCHED=   0x2,
RADV_PERFTEST_LOCAL_BOS  =   0x4,
-   RADV_PERFTEST_BINNING =   0x8,
-   RADV_PERFTEST_OUT_OF_ORDER   =  0x10,
-   RADV_PERFTEST_DCC_MSAA   =  0x20,
+   RADV_PERFTEST_OUT_OF_ORDER   =   0x8,
+   RADV_PERFTEST_DCC_MSAA   =  0x10,
 };
 
 bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b2078975a8..617886b8d8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -466,7 +466,6 @@ static const struct debug_control radv_perftest_options[] = 
{
{"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
{"sisched", RADV_PERFTEST_SISCHED},
{"localbos", RADV_PERFTEST_LOCAL_BOS},
-   {"binning", RADV_PERFTEST_BINNING},
{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{NULL, 0}
 };
@@ -1635,7 +1634,7 @@ VkResult radv_CreateDevice(
}
 
device->pbb_allowed = device->physical_device->rad_info.chip_class >= 
GFX9 &&
-   ((device->instance->perftest_flags & 
RADV_PERFTEST_BINNING) ||
+   (!(device->instance->debug_flags & 
RADV_DEBUG_NOBINNING) ||
 device->physical_device->rad_info.family == CHIP_RAVEN 
||
 device->physical_device->rad_info.family == 
CHIP_RAVEN2);
 
-- 
2.19.1

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Re: [Mesa-dev] [PATCH 2/2] radv: force-enable primitive binning for The Talos Principle

[Bas Nieuwenhuizen]

On Thu, Nov 15, 2018 at 9:06 AM Samuel Pitoiset
 wrote:
>
>
>
> On 11/15/18 12:16 AM, Bas Nieuwenhuizen wrote:
> > On Wed, Nov 14, 2018 at 5:32 PM Samuel Pitoiset
> >  wrote:
> >>
> >>
> >>
> >> On 11/14/18 5:28 PM, Bas Nieuwenhuizen wrote:
> >>> On Wed, Nov 14, 2018 at 5:26 PM Samuel Pitoiset
> >>>  wrote:
> 
>  +5% in ultra settings for both 4k and 1080p.
> 
>  Signed-off-by: Samuel Pitoiset 
>  ---
> src/amd/vulkan/radv_device.c | 3 +++
> 1 file changed, 3 insertions(+)
> 
>  diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>  index b2078975a8..5d212201ec 100644
>  --- a/src/amd/vulkan/radv_device.c
>  +++ b/src/amd/vulkan/radv_device.c
>  @@ -495,6 +495,9 @@ radv_handle_per_app_options(struct radv_instance 
>  *instance,
> */
>    instance->perftest_flags |= 
>  RADV_PERFTEST_SISCHED;
>    }
>  +
>  +   if (!(instance->debug_flags & RADV_DEBUG_NOBINNING))
>  +   instance->perftest_flags |= 
>  RADV_PERFTEST_BINNING;
> >>>
> >>> Just enable for everything? Unless you have something where it is clearly 
> >>> worse.
> >>
> >> I want to enable it incrementally and whitelist games for now. It's
> >> still unclear if this will help all games.
> >
> > IMO we really should avoid to introduce whitelisting stuff. I tested
> > some games and while ti certainly did not help a lot of them (Talos
> > confirmed helped) I saw no statistically significant regressions.
>
> What games did you test?

The usual benchmarkable suspects: dota2, RoTR, SotTR, F12017, DoW3, talos
>
> >
> >>
> >>>
>    } else if (!strcmp(name, "DOOM_VFR")) {
>    /* Work around a Doom VFR game bug */
>    instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
>  --
>  2.19.1
> 
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Re: [Mesa-dev] [PATCH v2] i965/glsl: don't add unused aoa element to the program resource list

[Tapani Pälli]

Hi;

On 11/13/18 4:28 AM, Timothy Arceri wrote:

Sorry for not getting back sooner on this one.

I'm leaning towards a NAK on this one. This is just under 300 new lines 
of code to work around a possibly over strict piglit test. While the 
test is not wrong an implementation is also not required to optimise 
away these unused elements.


If this was actually compressing/optimising the arrays 300+ plus lines 
would probably be ok. But all this code just to hide the elements from 
the resource list seems excessive. I know I suggested this as a possible 
alternative fix to actually optimising the arrays but now that I've seen 
the result I'm not so sure this is a good idea. This is my opinion happy 
to see what others think.


This is exactly how I feel as well. Functionally correct but way too 
much code considering the issue :/ I believe we do detect elements that 
get used during complication and linking so perhaps do that and in the 
end modify resource list, remove (or mark dirty) all the unused ones?




On 21/9/18 12:03 am, asimiklit.w...@gmail.com wrote:

From: Andrii Simiklit 

It fixes a bit incorrectly implemented ARB_program_interface_query.
If input aoa element is unused in shader program
the 'glGetProgramResourceIndex' function shouldn't
return a valid resource index for it according to:
ARB_program_interface_query spec:
 " For an active variable declared as an array of an aggregate 
data type
 (structures or arrays), a separate entry will be generated 
for each

 active array element"

v2: - Fixed case where the non-AoA elements were removed form
 the program resource list.
 The KHR-GL46.enhanced_layouts.varying_structure_locations
 test is passed now
 - Fixed case where a dereference index is not constant:
 The proper array length stored in 'deref->array->type->length'
 not in 'deref->type->length'
 - Fixed the output AoA elements handling:
 The list of active input AoA elements should not be used for
 output AoA elements
 - Fixed the function name from 'enumiramte_active_elements' to
 'enumerate_active_elements'
 - Fixed errors handling during active AoA elements enumeration

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92822
Signed-off-by: Andrii Simiklit 
---
  src/compiler/Makefile.sources |   4 +-
  .../glsl/ir_collect_active_aoa_elements.cpp   | 155 ++
  .../glsl/ir_collect_active_aoa_elements.h |  52 ++
  src/compiler/glsl/linker.cpp  |  91 --
  src/compiler/glsl/meson.build |   2 +
  5 files changed, 289 insertions(+), 15 deletions(-)
  create mode 100644 src/compiler/glsl/ir_collect_active_aoa_elements.cpp
  create mode 100644 src/compiler/glsl/ir_collect_active_aoa_elements.h

diff --git a/src/compiler/Makefile.sources 
b/src/compiler/Makefile.sources

index d3b0656483..a2ba3e37f1 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -154,7 +154,9 @@ LIBGLSL_FILES = \
  glsl/serialize.cpp \
  glsl/serialize.h \
  glsl/string_to_uint_map.cpp \
-    glsl/string_to_uint_map.h
+    glsl/string_to_uint_map.h \
+    glsl/ir_collect_active_aoa_elements.cpp \
+    glsl/ir_collect_active_aoa_elements.h
  LIBGLSL_SHADER_CACHE_FILES = \
  glsl/shader_cache.cpp \
diff --git a/src/compiler/glsl/ir_collect_active_aoa_elements.cpp 
b/src/compiler/glsl/ir_collect_active_aoa_elements.cpp

new file mode 100644
index 00..df0a41ad3e
--- /dev/null
+++ b/src/compiler/glsl/ir_collect_active_aoa_elements.cpp
@@ -0,0 +1,155 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a
+ * copy of this software and associated documentation files (the 
"Software"),
+ * to deal in the Software without restriction, including without 
limitation
+ * the rights to use, copy, modify, merge, publish, distribute, 
sublicense,

+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including 
the next
+ * paragraph) shall be included in all copies or substantial portions 
of the

+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT 
SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES 
OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
ARISING

+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "ir_collect_active_aoa_elements.h"
+#include "program.h"
+#include "linker_util.h"
+#include "util/set.h"
+#include "util/u_dynarray.h"
+
+namespace
+{
+    /***
+ * Helps to collect the names 

Re: [Mesa-dev] [PATCH 2/2] radv: force-enable primitive binning for The Talos Principle

[Samuel Pitoiset]

On 11/15/18 12:16 AM, Bas Nieuwenhuizen wrote:

On Wed, Nov 14, 2018 at 5:32 PM Samuel Pitoiset
 wrote:




On 11/14/18 5:28 PM, Bas Nieuwenhuizen wrote:

On Wed, Nov 14, 2018 at 5:26 PM Samuel Pitoiset
 wrote:


+5% in ultra settings for both 4k and 1080p.

Signed-off-by: Samuel Pitoiset 
---
   src/amd/vulkan/radv_device.c | 3 +++
   1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b2078975a8..5d212201ec 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -495,6 +495,9 @@ radv_handle_per_app_options(struct radv_instance *instance,
   */
  instance->perftest_flags |= RADV_PERFTEST_SISCHED;
  }
+
+   if (!(instance->debug_flags & RADV_DEBUG_NOBINNING))
+   instance->perftest_flags |= RADV_PERFTEST_BINNING;


Just enable for everything? Unless you have something where it is clearly worse.


I want to enable it incrementally and whitelist games for now. It's
still unclear if this will help all games.


IMO we really should avoid to introduce whitelisting stuff. I tested
some games and while ti certainly did not help a lot of them (Talos
confirmed helped) I saw no statistically significant regressions.


What games did you test?








  } else if (!strcmp(name, "DOOM_VFR")) {
  /* Work around a Doom VFR game bug */
  instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
--
2.19.1

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