[Mspgcc-users] Disable watchdog timer in crt0.S BSS initialization

Hi all, I am currently updating the verification environment of the openMSP430 to support the new Redhat/TI GCC toolchain. The first thing I noticed is that the *crt0* code by default assumes that the watchdog WDTCTL register is mapped at 0x015c... Does someone knows if there is a magic switch

Re: [Mspgcc-users] Disable watchdog timer in crt0.S BSS initialization

Sorry for the confusion, I meant *.data* initialization... not *.bss* Thanks, Olivier On Wed, Dec 3, 2014 at 10:54 PM, Olivier Girard olgir...@gmail.com wrote: Hi all, I am currently updating the verification environment of the openMSP430 to support the new Redhat/TI GCC toolchain. The

Re: [Mspgcc-users] Disable watchdog timer in crt0.S BSS initialization

On Wed, Dec 3, 2014 at 3:54 PM, Olivier Girard olgir...@gmail.com wrote: Hi all, I am currently updating the verification environment of the openMSP430 to support the new Redhat/TI GCC toolchain. The first thing I noticed is that the *crt0* code by default assumes that the watchdog WDTCTL