The multiplier block in FPGA are rather fast, so running them at twice
or 4 time the clock speed could be possible. In an asic they would
actually slow down the design because of the logic depth.
On 2013-01-13 18:52, Timothy Normand Miller wrote:
The multipliers are probably going to be the
Making a DAC, you better have an idea of what's the target market for it
before even trying to make one. Considering all the one on the market I
would probably say the only interesting reason to make one is if you are
doing an asic and you need a DAC inside for some custom purpose. Else
buy
On 2012-06-06 23:15, why...@f-cpu.org wrote:
Damn mailer sent before i finished :-(
Here is the full version.
On Wed, 06 Jun 2012 22:20:26 -0400, André Pouliot wrote:
The actual flag that are supported are :
Zero
Negative
Overflow
Carry
NaN
Inf
Underflow
Div0 ( still not resolve the divide
Hi,
I'll answer each email independently for simplicity sake.
On 2012-06-06 04:07, Nicolas Boulay wrote:
Hello,
Could you add diagonal of matrix of size 2 and 4 as data type. This a
complex and quaternion datatype.
Maybe string could be added (utf-8) ? This is quite far from GPGPU but
string
On 2012-06-06 11:29, Nicolas Boulay wrote:
You could add in the instruction section the splited load.
The DRAM bus is at least 64 bits wide, some are 128 bits, but most of
the time you have 2 or 3 64 bits buses. DRAM have at least a burst of
2 elements minimum. Burst of 4 seems to vanished. So
On 2012-06-06 18:44, why...@f-cpu.org wrote:
Hello !
On Wed, 6 Jun 2012 15:35:56 -0400, Timothy Normand Miller wrote:
Andre and I had debated over whether the shader pipeline should
support condition codes (like most processors) or not (like MIPS).
With MIPS, this reduces the amount of state
On 2012-06-06 21:54, why...@f-cpu.org wrote:
Hello everybody,
here are more cents :-)
On Wed, 6 Jun 2012 21:34:33 -0400, Timothy Normand Miller wrote:
You have some good points about some ops being redundant, with respect
to a CMP instruction. But we want other instructions to produce
Hi,
I'm going to talk about some stuff related to the hardware. Unless I'm
mistaken, then Tim can correct me, Is that we are targeting no specific
hardware and go for the hardware OS project without doing hardware.
Still the logic and the functional module related to graphics gard and
GPGPU
Hi,
I think it does. Someone would need to confirm. But from what I could
find for bus mastering it would mean that a device can take control of
the PCI bus to make transfer. Mostly for DMA transfer with the main
memory. From what I remember HQ the microcontroller in the lattice chip,
is
Petter Urkedal wrote:
On 2009-10-27, Andre Pouliot wrote:
2009/10/26 Petter Urkedal urke...@nbi.dk
1. The document list both signed and unsigned additive operations.
These are equivalent, except possibly for the flags. I suggest not to
differentiate signed and unsigned additive
Petter Urkedal wrote:
On 2009-10-29, Timothy Normand Miller wrote:
On Thu, Oct 29, 2009 at 7:24 AM, André Pouliot andre.poul...@gmail.com
wrote:
Petter Urkedal wrote:
On 2009-10-27, Andre Pouliot wrote:
2009/10/26 Petter Urkedal urke...@nbi.dk
2. Do
Hi,
Yann Guidon wrote:
hello,
Andre Pouliot wrote:
Another way to view it is turn the data from a SIMD on the side. You
change any lateral dependency of the data, you bring it back
vertically. On a standard SIMD you would process different threads
even with the same instruction one after
Timothy Normand Miller wrote:
On Mon, Sep 21, 2009 at 12:17 AM, Hugh Fisher hugh.fis...@anu.edu.au wrote:
Timothy Normand Miller wrote:
One of the design details that seems to be hard to present is the MIMD
architecture. At first glance, it looks like a SIMD architecture.
But all
Hugh Fisher wrote:
Andre Pouliot wrote:
Hi everyone,
That new revision will be with programmable shader that can also be
use for
GPGPU. The current work document can be seen here:
http://docs.google.com/View?id=dfsp4qpd_41dtrrskfb
As everyone can see, it's a work in progress. We welcome
John Griessen wrote:
Timothy Normand Miller wrote:
We should come up with a name to replace IP
core. But we need to ensure that this name is not ambiguous and that
it is recognizable as being synonymous to someone who is used to the
term IP core. Starting places are things like logic block
We can go with something like :
0.1-fb-RC1 and the final release code name could be : Hatching howl
the working release could be 0.1 if we need to make correction to that
release to fix bug just go for 0.1.x version.
for the VGA with something going the same way for number:
0.2-vga-RC1 and the
Michael Meeuwisse wrote:
Then, to wrap up this overview, a fun little story about this guy. I
forgot his name, but he was enthusiastic as hell, during the
discussion grabbed his laptop and even started to take a good long
long at the schematics and told me that I should told everbody to (I
Russell Shaw wrote:
Timothy Normand Miller wrote:
On Fri, Jun 6, 2008 at 7:13 AM, Dieter [EMAIL PROTECTED]
wrote:
But we need to think of things that make us say I'd pay
$1500 to be able to do that specific thing better. They can be
relatively niche applications, though. I spoke with
I'll try to work on some stuff when I have some free time.
I'm going to start by looking in the xp10, at least to have that part
working when the first board will ship.
Timothy Normand Miller wrote:
I think it's time to get the VGA Code Sprint going again. OGD1 is
ready for pre-orders, and
approximately one year of experience doing internship writing vhdl
code for fpga. I'm currently living in Canada and I speak French and
functional English.
If you have any lead or want more information please contact me.
André Pouliot
___
Open-graphics mailing
I'll try to do a summary between the 2 chip. Fist of all, the logic cell
value is a marketing number who should never be used.
The V5SX50T is a chip containing 288 dsp block who are 25*18 multiplier
with an adder and a accumulator as I understand it. There is 32640 LUT
in the V5 but those LUT
Raphaël Jacquot wrote:
Timothy Normand Miller wrote:
time between when we place our order for 100 boards and when we get
(...)
leaves us with a $6 bill to pay before we have any revenue, and
that makes one card = 600 USD ?
- The retail price is $1500, but the first 100 pre-orders
For quite some time on the wiki there was a naming Conventions pages,
sort of a coding guideline. Since the code base is growing there is a
need to review it and for people to start using it.
The first revision as been made and more input is needed to improve it
and make it meaningful.
Following a discussion between Kenneth and me, we would like to add the
creation of a VGA core written in verilog for the GSoC ideas.
I know we were planning on doing VGA via software emulation with the HQ.
Doing it as a GSoC project also allows us to explore the design of a VGA
core without
Timothy Normand Miller wrote:
On 3/11/08, André Pouliot [EMAIL PROTECTED] wrote:
Following a discussion between Kenneth and me, we would like to add the
creation of a VGA core written in verilog for the GSoC ideas.
I know we were planning on doing VGA via software emulation with the HQ
Michael Meeuwisse wrote:
I continued digging a little, the vid_control module has vid_clock as
an input, module video_wrapper uses this module and also has vid_clock
as an input. Right now, the s3_top_level maps vid0_clock or vid1_clock
to these inputs, but these signals are somewhat odd;
For the DCM feedback, we don't care about the phase of this clock
relative to anything else, but we do need a feedback. I think you can
just wire CLK0 directly to CLKFB.
I'll find some docs about what this feedback is all about. But a wire
connecting CLK0 to CLKFB will do the trick?
be 1, 2, 4, 8, 16, 32, not 1 - 6.
It's late and I stopped thinking. That wasn't a typo.
On 5 Mar 2008, at 00:34, André Pouliot wrote:
Actually to use the ClkFx output with a frequency input below 18MHz
there shouldn't be any feedback present on the dcm.
For the documentation it's
Viktor Pracht wrote:
Timothy Normand Miller wrote:
We're not doing physical floor-planning here. We're doing high-level
Verilog modules. PR isn't involved. Or do you mean PR in terms of
how the Verilog modules are placed and routed visually in the IDE?
I mean the latter. The
Timothy Normand Miller wrote:
On 3/3/08, André Pouliot [EMAIL PROTECTED] wrote:
Why not do the connection between 2 modules be represented as a single
wire? That wire when selected open a windows with a list of the
connection already made and the other connection possible?
This all
The license for the HDL is under dual license GPLv2 and a license to
Transversal technology. If someone want to make is own board or re-use
the code he is free to do so for non commercial purpose. If someone want
to use the HDL code for any commercials activity they must talk with
Transversal.
John Griessen wrote:
Timothy Normand Miller wrote:
On 2/25/08, John Griessen [EMAIL PROTECTED] wrote:
For Traversal to earn revenue, we need unlimited rights to the
schematics and other copyrightable materials. But at the same time,
we also release our stuff under GPL. Look up how
multiplier in an asic
design. Maybe this could a design optimisation, the day you need to
find some free slice, to remove this stage for few unit.
2008/2/5, André Pouliot [EMAIL PROTECTED]:
Well it would add a fifth stage to the multiplier. That added stage
would take something like 10
There was some change made to the file in the repository. Because of
those change now the Spartan 3 part of the design can pass synthesis. It
will also solve some of the problem encountered by those trying to
simulate that part.
Here is the Changelog:
of this inf*zero=zero feature ?
// Open Graphics float25 multiplier tb generator
// Written by André Pouliot
//Created : 2008/02/03
/*
DUAL LICENSING
(0) This Work is defined to be this document or source code, parts of
this document or source code, or derivative works of this document or
source
Timothy Normand Miller wrote:
On 1/28/08, Terry Hancock [EMAIL PROTECTED] wrote:
Dieter wrote:
And i'm always astonished when i talk with VLSI/FPGA guys, that
they can cope with the brokenness of their tools which are by far
worse than gcc, especially considering what Synplicity and
The problem with the current version of the webpack is that it dosn't
support the spartan3 4000 present on the board, it support up to the
spartan3-1500
Terry Hancock wrote:
Regarding jb's remark about zero-cost Linux versions of Xilinx software,
can anyone field this comment?
James Richard Tyrer wrote:
André Pouliot wrote:
If we do the same with a fixed pipeline and we suppose we do the same
100 operations but unrolled and we run at 100MHZ. We have the same
requirement for the multiplier 20 stage of 4 multiplier per
stage(RGBA) so that's 80 multiplier
Timothy Normand Miller wrote:
Anyone use SVN tools for Windows? (It's not for me.)
I'm testing out RapidSVN, but it doesn't ask for authentication. In
that case you can't check stuff in, right? Any idea how to get it to
ask for a name and password?
For windows I'm using tortoise SVN
James Richard Tyrer wrote:
Kenneth Ostby wrote:
Actually when it comes hardware there is surprisingly little matrix
matrix multiplication in the 3D world.
With a 3-word SIMD you need to:
clear the accumulator
load P in a register
perform 3 MAC vector instructions
If you
Timothy Normand Miller wrote:
On 7/25/07, André Pouliot [EMAIL PROTECTED] wrote:
Hello,
Here is the first version for the float25 multiplier. The float are
based on the IEEE-754 specification but with a reduce mantissa to fit
the hardware on the spartan3. It's still doesn't have a test
.
The multiplier produce correct result with normalised value, denormalised value
are also calculed correctly but the output is not well handled. If the Exponent
go under zero the value is rounded to zero. If the exponent have a value of 255
or more the result is rounded to infinite.
Author : André
Petter Urkedal wrote:
I'd like to tie up a loose end on the CPU. We also need to work out the
communication with the periphery, but this is about the instruction set:
Currently the instruction format can only fit 8 operators, which
currently are and, or, xor, asl, add, rsub (y - x),
mult, and
Metastability still exist today.
Metastability period of opportunity do diminish because of the
technology is better, but it also augment because the operating
frequency augment.
It's not that prevalent in system where one clock domain is used because
to prevent it you just have to design
Peter TB Brett wrote:
On Tuesday 20 February 2007 10:52:46 Dieter wrote:
24Gb torrents that are stated to be dumps of HD-DVDs and
BlueRay discs...
Peter's AMD64 3200+ can't decode mpeg4 in real time. (bitrate?)
Even Attila decode it in software Kinali admits that a
AMD64 3700+ isn't
For the pci bus analyzer why try to get all the signal to show as a
waveform?
The card could just decode the stream of data on the pci bus and forward
that to the user on the form of address + data in an ascii file. For
some people it's a lot simpler if we provide that with some setting to
Why not keep it simple? We need only 2 level for defining how much the
design is open:
Open Document Hardware : where all the documentation to use and control
the hardware(chip or card) is available without a NDA.
Open Design Hardware : The same as Open Document Hardware but with an
added
Attila Kinali a écrit :
On Sun, 29 Oct 2006 11:30:24 -0400
Timothy Miller [EMAIL PROTECTED] wrote:
According to Howard, using async resets is the appropriate thing to do
for an FPGA. They come for free with the available circuitry and
they are supposed to behave correctly regardless of
[EMAIL PROTECTED] wrote:
I'm a nerd, not a geek, and I've got two of them. There are also situations like graphic arts, where you can get a little more image sharpness out of a monitor like the FW-900 if you use the BNC inputs instead of the VGA inputs. Grandma might have already blown
James Richard Tyrer wrote:
[EMAIL PROTECTED] wrote:
And, monitors without DDC are not oddball DDC is a recent innovation,
and a good chunk of the installed base doesn't have it.
The term odd-ball entered the discussion before DDC was mentioned. It
does not refer to monitors without DDC
James Richard Tyrer wrote:
[EMAIL PROTECTED] wrote:
And, monitors without DDC are not oddball DDC is a recent innovation,
and a good chunk of the installed base doesn't have it.
The term odd-ball entered the discussion before DDC was mentioned. It
does not refer to monitors without DDC
Timothy Miller wrote:
I'm making an assumption here that I haven't verified, but it makes
sense.
Internally, every LUT (the basic FPGA logic block) has a register
connected to its output. So if you want to register the output of a
LUT, the register is free, and the wire delay is
Timothy Miller wrote:
After doing some basic testing and debugging, I decided to start
taking a crack at optimizing the memory controller for speed.
Here's the longest combinatorial path right now:
Slack: -5.272ns (requirement - (data path - clock
path skew + uncertainty))
josephhenryblack wrote:
André Pouliot wrote:
josephhenryblack wrote:
André Pouliot wrote:
Also if there is multiple person who work on the code we better use
some
guideline on signal denomination and file name convention. Also the
structure of directory used. It's some boring
josephhenryblack wrote:
André Pouliot wrote:
Also if there is multiple person who work on the code we better use some
guideline on signal denomination and file name convention. Also the
structure of directory used. It's some boring consideration to do right
now but if we don't in a few
Timothy Miller wrote:
On 5/27/06, josephhenryblack [EMAIL PROTECTED] wrote:
two questions for now..
1. For the modules, what code will you accept - verilog or/and vhdl? ( I
can do basic vhdl, but willing to learn.)
Especially in this case, we're doing only one module, and I've already
Timothy Miller wrote:
On 5/27/06, André Pouliot [EMAIL PROTECTED] wrote:
Some synthetizer accept both language in the same design. But it must be
by doing call to the others block. For example you have the spi prom
interface in vhdl you instanciate it in a verilog design, the contrary
[EMAIL PROTECTED] wrote:
Just like with Niagara, we have lots of opportunities to avoid control
and data hazzards, so we don't need to account for them. (We may want
to have some locks in place, but we can afford to just stall.) For
each pixel, even the effective memory read latency
Lourens Veen wrote:
On Monday 03 April 2006 23:17, I wrote:
There are still other issues, like software and file formats to use,
but they are really part of the next stage I think. If you have any
ideas on those please save them for later, or if you really can't
wait, send them
Rene Herman wrote:
André Pouliot wrote:
Sorry to tell you but using 16 bit 44,1KHz sampling most person can
tell the difference you are already at twice the nyquist frequency
for what the ear can listen.
No, the Nyquist frequency is the highest frequency that can be fully
reconstructed
James Richard Tyrer wrote:
Still concerned about the business plan.
Have we considered using FPGAs with a direct path to ASICs?
For example:
http://www.altera.com/products/devices/hardcopy/hrd-index.html
If that would work, then after we had working C or VHDL code, we
would start by
J.O. Aho wrote:
On Tue, 28 Feb 2006, Attila Kinali wrote:
On Tue, 28 Feb 2006 21:47:33 +0100 (CET)
J.O. Aho [EMAIL PROTECTED] wrote:
What about trying to get magazines to write about the project?
Not sure how to catch their interest for the project, but maybe just
write
to some linux
After looking trough it some more, do at least 3 thing. First the
capacitor C10 lose it shouldn't even be there you already have a lowpass
filter made by R5 and C12, also the capacitor C12 feed automaticly
brutal current change into the chip and add more current sensing
capability from beyond the
I was trying to stay out of that debate but life isn't fair. So here my
two cents worths. Keep the RTL put it in an escrow when it will be
finish, so at a later date or when a certain amount of money will be
made it's released. Allow acces (via a secure CVS, subversion ,
whatever)to key developper
Andy Goth wrote:
On Sun, Apr 17, 2005 at 11:31:04PM +0200, Lourens Veen wrote:
How about geometric solids? Cube, Pyramid, Cylinder, Sphere, Prism,
Torus, Tetrahedron...It gives a feel of mathematical and engineering
precision and it makes for nice clean cover art.
Or the Barth Decic.
Daniel Phillips wrote:
On Sunday 10 April 2005 20:44, Timothy Miller wrote:
What you get, when you buy the prototype board, is the same logic as
what you get from the consumer board, except that it's slower and
more expensive. Mind you, there'll probably be plenty of hobbyist
things you can
Daniel Phillips wrote:
On Tuesday 05 April 2005 16:52, Timothy Miller wrote:
Um... I'm really hesitant to do that. We did a parts cost estimate,
but I can't remember the number off hand, although I think it was
over $300. Note that this board would include a good number of
debug features,
What we could do is pick a name for the chip right now. Then when it
come to name the card your going to be selling, we could stick with the
same name or change it. And yes I do have also a soft spot for
harbinger as name. :)
A the same time I have a question for Timothy. Would it be possible
The main problem is one of this chip market is embedded system, not only
x86. And some architecture, like in embedded, sometime doesn't support
DMA, they do support PIO and basic interfacing mode, but DMA is alien.
To be able to use DMA you need hardware and software supporting it and
you
Try to make it as fast as you can in the limit caused by the design. If
you optimise now for speed, when going to asic you will be able to clock
it faster without the need to do a major redesign. If the card clock is
150MHz for all the design I'll be happy since it's in a FPGA. I do wish
it could
On Wed, 2005-02-02 at 14:15, Timothy Miller wrote:
Another note: Our other hardware engineer who is looking at this said
that he fully intended, using ADV parts, that the DVI would be separate.
This puts us in the following position:
(1) Standard video will be something like the ADV7312
On Wed, 2005-02-02 at 21:40, Timothy Miller wrote:
On Wed, 02 Feb 2005 21:04:29 -0500, André Pouliot
To me it seem a possible options but I do see one or 2 potential
problem. One of them is the card estate that you work on. We already
have a FPGA, a serial eprom, eeprom for the card
---BeginMessage---
On Sat, 2005-01-29 at 12:06, Timothy Miller wrote:
On Sat, 29 Jan 2005 08:34:40 +0100, Pieter Hulshoff [EMAIL PROTECTED] wrote:
On Saturday 29 January 2005 04:17, Timothy Miller wrote:
On Fri, 28 Jan 2005 19:01:35 -0500, André Pouliot
[EMAIL PROTECTED] wrote
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