I can't test the code anytime soon, but it looks OK to me so I
think you should commit it if you've run tests on it.
I would like the same padding logic added to flash erase_address
to restore that functionality.
Qualified by an pad option to round up/down to nearest sector boundary,
if you
This config is only lightly tested, and doesn't work well yet;
but it's a start.
* Notably missing is PLL configuration, since each DaVinci
does that just a bit differently; and thus DDR2 setup.
* The SRST workaround needed for the goof in the CPLD's VHDL
depends on at least the
On Sunday 27 December 2009, Øyvind Harboe wrote:
I can't test the code anytime soon, but it looks OK to me so I
think you should commit it if you've run tests on it.
My thoughts exactly. Done.
I would like the same padding logic added to flash erase_address
to restore that functionality.
On Monday 21 December 2009, Yegor Yefremov wrote:
On Fri, Dec 18, 2009 at 3:58 PM, Charles Vaughn cvau...@gmail.com wrote:
What revision is your board? The title is a bit out of sync with the issue,
as in June it appears TI multiplexed SWO and JTAG. My board rev is LMWLV-C.
My board rev:
Yegor,
On Monday 21 December 2009, Yegor Yefremov wrote:
My board rev: LMWLV-B
Could you forward the USB IDs and device string of your
board? I notice that tcl/interface/luminary-lm3s811.cfg
doesn't include the USB IDs, so it's at least partially
broken. Also its device string doesn't match
Qualified by an pad option to round up/down to nearest sector boundary,
if you prefer.
I'll think about that. Any such dangerous erase extra stuff
should certainly not be a default behavior, when someone has gone
through the effort to specify exactly the address range they want
to erase!
