Few fixes for RISC-V APLIC discovered during Linux AIA patch reviews.
These patches can also be found in the apatel_aplic_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (2):
hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC
MSI-mode
hw/intc/riscv_aplic
lue = (incoming wire value) XOR (source is inverted)"
Update the riscv_aplic_read_input_word() implementation to match the above.
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 17 +++--
1 fil
d RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index e98e258deb..775bb96164 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw
On Thu, Feb 29, 2024 at 8:42 PM Andrew Jones wrote:
>
> On Thu, Feb 29, 2024 at 07:07:43PM +0530, Himanshu Chauhan wrote:
> > All the CPUs may or may not implement the debug triggers (sdtrig)
> > extension. The presence of it should be dynamically detectable.
> > This patch exports the debug
On Mon, Feb 5, 2024 at 9:36 AM Alistair Francis wrote:
>
> On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones wrote:
> >
> > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote:
> > > > > From memory the "debug" property is for the original debug spec:
> > > > >
On Wed, Jan 17, 2024 at 7:54 PM Himanshu Chauhan
wrote:
>
> The debug trigger (sdtrig) capability is controlled using the debug property.
> The sdtrig is an ISA extension and should be treated so. The sdtrig extension
> may or may not be implemented in a system. Therefore, it must raise an
fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
> > > memmap[VIRT_DRAM].size,
> > > machine);
> > > +} else {
> > > +fdt_load_addr =
>
On Tue, Aug 1, 2023 at 4:16 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 7/30/23 22:53, Fei Wu wrote:
> > riscv virt platform's memory started at 0x8000 and
> > straddled the 4GiB boundary. Curiously enough, this choice
> > of a memory layout will prevent from launching a VM with
> > a bit
Hi Bin,
On Wed, Jul 19, 2023 at 9:15 PM Bin Meng wrote:
>
> On Wed, Jul 19, 2023 at 11:22 PM Anup Patel wrote:
> >
> > On Wed, Jul 19, 2023 at 3:23 PM Alistair Francis
> > wrote:
> > >
> > > On Wed, Jul 19, 2023 at 3:39 PM Anup Patel wrote:
>
On Wed, Jul 19, 2023 at 3:23 PM Alistair Francis wrote:
>
> On Wed, Jul 19, 2023 at 3:39 PM Anup Patel wrote:
> >
> > On Wed, Jul 19, 2023 at 7:03 AM Alistair Francis
> > wrote:
> > >
> > > On Sat, Jul 15, 2023 at 7:14 PM Atish Patra wrote:
>
t; > On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup
On Fri, Jul 14, 2023 at 3:50 PM Conor Dooley wrote:
>
> On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote:
>
> > &
On Fri, Jul 14, 2023 at 3:43 AM Conor Dooley wrote:
>
> +CC OpenSBI Mailing list
>
> I've not yet had the chance to bisect this, so adding the OpenSBI folks
> to CC in case they might have an idea for what to try.
>
> And a question for you below Daniel.
>
> On Wed, Jul 12, 2023 at 11:14:21PM
On Mon, Jun 26, 2023 at 4:57 PM Philippe Mathieu-Daudé
wrote:
>
> Hi,
>
> I'm working on a tree-wide accelerator refactor and want
> to run various configs to be sure I didn't broke anything.
>
> QEMU theoretically supports running a riscv32 guest using
> KVM on a riscv64 host, however the
d `mmsiaddrcfgh`.
>
> Signed-off-by: Tommy Wu
> Reviewed-by: Frank Chang
Looks good to me.
Reviewed-by: Anup Patel
> ---
> hw/intc/riscv_aplic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.
On Fri, May 26, 2023 at 5:41 PM Sunil V L wrote:
>
> This series improves the pflash usage in RISC-V virt machine with solutions to
> below issues.
>
> 1) Currently the first pflash is reserved for ROM/M-mode firmware code. But
> S-mode
> payload firmware like EDK2 need both pflash devices to
te.
>
> Signed-off-by: Ivan Klokov
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/intc/riscv_aplic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index cfd007e629..71591
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
>
> Because the starting address of ram is not necessarily 0,
> the remaining free space in ram is
> ram_size - (start - ram_base) instead of ram_size-start.
>
> Signed-off-by: Hang Xu
What happens in-case a platform has multiple RAM banks ?
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cp
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/time_helper.c | 24
1 file
as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_rva.c.in
riscv-to-apply.next branch of Alistair
Changes since v1:
- Added Alistair's Reviewed-by tags to appropriate patches
- Added detailed comment block in PATCH4
Anup Patel (4):
target/riscv: Update VS timer whenever htimedelta changes
target/riscv: Don't clear mask in riscv_cpu_update_mip
Hi Alistair,
On Tue, Jan 3, 2023 at 9:43 PM Anup Patel wrote:
>
> Hi Alistair,
>
> On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis
> wrote:
> >
> > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote:
> > >
> > > On Thu, Dec 15, 2
Hi Alistair,
On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote:
>
> On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote:
> >
> > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis
> > wrote:
> > >
> > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel
&
On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote:
>
> On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote:
> >
> > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote:
>
On Thu, Dec 22, 2022 at 6:27 PM Bin Meng wrote:
>
> On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 12/22/22 07:24, Bin Meng wrote:
> > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza
> > > wrote:
> > >> This test is used to do a quick sanity check
On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis wrote:
>
> On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote:
> >
> > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis
> > wrote:
> > >
> > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel
> > &g
On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote:
>
> On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote:
> >
> > The htimedelta[h] CSR has impact on the VS timer comparison so we
> > should call riscv_timer_write_timecmp() whenever htimedelta changes.
> >
&g
Hi Alistair,
On Tue, Nov 8, 2022 at 6:27 PM Anup Patel wrote:
>
> This series mainly includes fixes discovered while developing nested
> virtualization running on QEMU.
>
> These patches can also be found in the riscv_nested_fixes_v2 branch at:
> https://github.com/avpatel/qe
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/time_helper.c | 24
1 file
as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_rva.c.in
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cp
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed,
detailed comment block in PATCH4
Anup Patel (5):
target/riscv: Typo fix in sstc() predicate
target/riscv: Update VS timer whenever htimedelta changes
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
target/riscv: No need to re-start QEMU timer when timecmp
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/
On Wed, Nov 2, 2022 at 5:40 AM Alistair Francis wrote:
>
> On Mon, Oct 31, 2022 at 1:49 PM Anup Patel wrote:
> >
> > On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis
> > wrote:
> > >
> > > On Fri, Oct 28, 2022 at 2:53 AM Anup Patel
> > > w
On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis wrote:
>
> On Fri, Oct 28, 2022 at 2:53 AM Anup Patel wrote:
> >
> > The time CSR will wrap-around immediately after reaching UINT64_MAX
> > so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
> >
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 16
1 file changed, 16
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel
---
target/riscv/time_helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 2 --
ta
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_rva.c.in
This series mainly includes fixes discovered while developing nested
virtualization running on QEMU.
These patches can also be found in the riscv_nested_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (5):
target/riscv: Typo fix in sstc() predicate
target/riscv: Update VS
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
Changes since v2
On Fri, Aug 19, 2022 at 8:40 PM Richard Henderson
wrote:
>
> On 8/19/22 00:31, Anup Patel wrote:
> > static int aia_hmode(CPURISCVState *env, int csrno)
> > {
> > -if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > +CPUState *cs = env_cpu(env);
> &g
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
Changes since v1
On Fri, Aug 19, 2022 at 10:24 AM Weiwei Li wrote:
>
>
> 在 2022/8/19 上午11:09, Anup Patel 写道:
> > The arch review of AIA spec is completed and we now have official
> > extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
> > AIA CSRs).
> >
> &g
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
hw/intc
On Thu, Aug 4, 2022 at 5:59 PM Weiwei Li wrote:
>
>
> 在 2022/8/4 上午11:38, Anup Patel 写道:
> > On Wed, Aug 3, 2022 at 6:16 PM Weiwei Li wrote:
> >> Normally, riscv_csrrw_check is called when executing Zicsr instructions.
> >> And we can only do access control
On Wed, Aug 3, 2022 at 6:16 PM Weiwei Li wrote:
>
> Normally, riscv_csrrw_check is called when executing Zicsr instructions.
> And we can only do access control for existed CSRs. So the priority of
> CSR related check, from highest to lowest, should be as follows:
> 1) check whether Zicsr is
On Wed, Jul 27, 2022 at 9:24 AM Richard Henderson
wrote:
>
> On 7/26/22 20:25, Anup Patel wrote:
> > We should call decode_save_opc() for every decoded instruction
> > because generating transformed instruction upon guest page faults
> > expects opcode to be available.
in hypervisor slow and
also breaks nested virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_privileged.c.inc | 4
target/riscv/insn_trans/trans_rvh.c.inc| 2 --
target/riscv/
t have better suggestions on this ?
Regards,
Anup
>
> Regards,
> Jim Shu
>
> On Mon, Jul 18, 2022 at 12:02 PM Anup Patel wrote:
>>
>> +Atish
>>
>> On Mon, Jul 18, 2022 at 9:23 AM Jim Shu wrote:
>> >
>> > RISC-V priv spec v1.12 permits 2
+Atish
On Mon, Jul 18, 2022 at 9:23 AM Jim Shu wrote:
>
> RISC-V priv spec v1.12 permits 2 PTE-update schemes of A/D-bit
> (Access/Dirty bit): HW update or SW update. RISC-V profile defines the
> extension name 'Ssptwad' for HW update to PTE A/D bits.
>
On Mon, Jul 4, 2022 at 2:59 AM Stafford Horne wrote:
>
> Add an endianness property to allow configuring the RTC as either
> native, little or big endian.
>
> Cc: Laurent Vivier
> Signed-off-by: Stafford Horne
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anu
On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v9 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC
riv spec version is not staisfied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (2):
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
target/riscv: Force disable extensions if priv spec version does not
match
target/riscv/cpu.c
rings to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
On Wed, Jun 29, 2022 at 9:27 AM Bin Meng wrote:
>
> Hi Rahul,
>
> On Wed, Jun 29, 2022 at 10:07 AM Rahul Pathak
> wrote:
> >
> > Hi Alistair
> >
> > My fix patch needs to be dropped since Anup took care of this issue
> > in his yesterdays series update in this patch -
> > [PATCH v8 4/4]
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
riv spec version is not staisfied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (4):
Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11
or higher"
target/riscv: Set minumum priv spec version for mcountinhibit
target/riscv
rings to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because
commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements
proper mcountinhibit CSR emulation.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 3 ---
target/riscv/csr.c | 2 --
2 files changed, 5 deletions
On Mon, Jun 27, 2022 at 10:25 PM dramforever wrote:
>
> On 6/27/22 09:00, Alistair Francis wrote:
> > On Sat, Jun 11, 2022 at 6:06 PM Anup Patel wrote:
> >> We should write transformed instruction encoding of the trapped
> >> instruction in [m|h]tinst CSR at
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because
commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements
proper mcountinhibit CSR emulation.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 3 ---
target/riscv/csr.c | 2 --
2 files changed, 5 deletions
rings to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
rite_gva is true only for HLV/HSV
instructions
- Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes"
patches in this series for easy review
- Re-worked PATCH7 to force disable extensions if required
priv spec version is not staisfied
- Added new PATCH8 to fix "aia=
On Tue, Jun 28, 2022 at 4:47 AM Alistair Francis wrote:
>
> On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote:
> >
> > We should disable extensions in riscv_cpu_realize() if minimum required
> > priv spec version is not satisfied. This also ensures that machines with
>
On Tue, Jun 28, 2022 at 4:48 AM Alistair Francis wrote:
>
> On Thu, Jun 9, 2022 at 1:31 PM Anup Patel wrote:
> >
> > We should write transformed instruction encoding of the trapped
> > instruction in [m|h]tinst CSR at time of taking trap as defined
> > by the R
On Thu, Jun 16, 2022 at 8:08 AM Alistair Francis wrote:
>
> On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra wrote:
> >
> > On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis
> > wrote:
> > >
> > > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
> > > >
> > > > On Thu, Jun 2, 2022 at 12:02
for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.
We update the IMSIC CSR emulation as-per above to match the latest AIA
draft specification.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 24 +--
target
(not mandatory) priority assignments.
We update the default priority table and hviprio mapping as-per above.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 2 +-
target/riscv/cpu_helper.c | 134 ++
2 files changed, 66 insertions(+), 70
and these can be
found at:
riscv_aia_update_v1 branch of https://github.com/avpatel/opensbi.git
riscv_aia_v1 branch of https://github.com/avpatel/linux.git
Anup Patel (2):
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
target/riscv: Update default priority table for local
ATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (4):
target/riscv: Don't force update priv spec version to latest
target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or
higher
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
target/risc
t latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel
Reviewed-by
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which is always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the
CSR ops.")
Signed-off-by:
rings to the device
tree")
Signed-off-by: Anup Patel
---
target/riscv/cpu.c | 144 +++--
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8db0f0bd49..a17bc98662 100644
--- a/target/riscv/cpu.c
++
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 214
On Fri, Jun 10, 2022 at 5:20 PM dramforever wrote:
>
> >
> >> In addition, the various V-extension vector load/store instructions do not
> >> have
> >> defined transformations, so they should show up in [m|h]tinst as all zeros.
> > Okay, I will update.
> Just a clarification/suggestion: It might
On Fri, Jun 10, 2022 at 3:00 PM dramforever wrote:
>
> Hi Anup Patel,
>
> I think there are some misunderstandings of the privileged spec with regards
> to
> [m|h]tinst handling. Here are some possible issues I've found:
>
> > +
On Thu, Jun 9, 2022 at 7:28 PM Richard Henderson
wrote:
>
> On 6/8/22 20:16, Anup Patel wrote:
> > On Wed, Jun 8, 2022 at 10:23 PM Richard Henderson
> > wrote:
> >>
> >> On 6/8/22 09:14, Anup Patel wrote:
> >>> +struct isa_ext_data isa_edata
rings to the device
tree")
Signed-off-by: Anup Patel
---
target/riscv/cpu.c | 57 ++
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9f9c27a3f5..e7eb65d708 100644
--- a/target/riscv/cpu.c
++
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 231
es in this series for easy review
- Re-worked PATCH7 to force disable extensions if required
priv spec version is not staisfied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (4):
target/riscv: Don't force update priv spec version to latest
target/riscv
t latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel
Reviewed-by
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which is always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the
CSR ops.")
Signed-off-by:
On Wed, Jun 8, 2022 at 10:23 PM Richard Henderson
wrote:
>
> On 6/8/22 09:14, Anup Patel wrote:
> > +struct isa_ext_data isa_edata_arr[] = {
>
> static const?
Using const is fine but we can't use "static const" because
the "struct isa_ext_data" has a
rings to the
device tree")
Signed-off-by: Anup Patel
---
target/riscv/cpu.c | 57 ++
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9f9c27a3f5..953ba2e445 100644
--- a/target/riscv/cpu.c
++
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 231
ied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (4):
target/riscv: Don't force update priv spec version to latest
target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or
higher
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrup
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel
t latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel
Reviewed-by
On Tue, Jun 7, 2022 at 8:31 AM Anup Patel wrote:
>
> On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote:
> >
> > On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, May 26, 2022 at 8:12 PM Anup Patel
> > >
On Mon, Jun 6, 2022 at 7:25 AM Alistair Francis wrote:
>
> On Thu, May 26, 2022 at 8:09 PM Anup Patel wrote:
> >
> > We should disable extensions in riscv_cpu_realize() if minimum required
> > priv spec version is not satisfied. This also ensures that machines with
>
On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote:
>
> On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis wrote:
> >
> > On Thu, May 26, 2022 at 8:12 PM Anup Patel wrote:
> > >
> > > We should write transformed instruction encoding of the trapped
> &g
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