e are "check-tcg" ones. The aging
> >> fedora-criss-cross image works well enough for developers but can't be
> >> used in CI as we need supported build platforms to build QEMU.
> >>
> >> Does this mean the writing is on the wall for this architecture?
> >
On Wed, Aug 23, 2023 at 4:56 PM Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
>
Reviewed-by: Edgar E. Iglesias
> ---
> target/cris/translate.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/targ
of the CFU_APB, CFU_FDRO and CFU_SFR are introduced and
> also models of the CFRAME controller and CFRAME broadcast controller.
>
> The series thereafter ends with connecting the models to Xilinx Versal
> machine.
>
I just had a quick look and the series LGTM!
Acked-by: Edgar E. Iglesias
&g
defined when enabling MTTCG.
Reviewed-by: Edgar E. Iglesias
There might be MicroBlaze systems that allow reordering of load vs store
streams but it doesn't seem to be documented and I'm not 100% certain so
this change LGTM!
Thanks,
Edgar
>
> Cc: Alistair Francis
> Cc: Edgar E.
hange all of these helpers to return
booleans...
Anyway, this fix looks good to me:
Reviewed-by: Edgar E. Iglesias
> +{
> +return !!(s->regs[R_DMASR] & DMASR_HALTED);
> +}
> +
> static void stream_reset(struct Stream *s)
> {
> s->regs[R_DMASR] = DMASR_HALTED
et indicates this bit is active on reset.
>
> See page 25, SPI Control Register section:
>
> https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
>
>
Yes, MTI should be set when the device comes out of reset.
https://gitlab.com/qemu-project/qemu/-/issues/1493
> Signed-off-by: Peter Maydell
>
Reviewed-by: Edgar E. Iglesias
> ---
> hw/char/cadence_uart.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
On Tue, Feb 21, 2023 at 7:28 AM Philippe Mathieu-Daudé
wrote:
> Hi Edgar,
>
> The Xilinx Virtex ML507 model uses 2 different interrupt controllers:
> - Universal Interrupt Controller
> - Xilinx OPB Interrupt Controller
> Both are connected to the same CPU IRQ line, IRQ#3 (PPC40x_INPUT_CINT):
>
>
e" command within gdb.
> >
> > (I built gdb from source, to try and debug why this still wasn't
> > working, only to find that it did. :-P)
> >
> > Alex, any way to modify our gdb test to fail gracefully here?
> >
> > Regardless, having proper xml for all
On Mon, Jan 09, 2023 at 01:59:33PM +0800, Qiang Liu wrote:
> This patch checks if the s->tx_fifo is full.
+ CC: Fred
Reviewed-by: Edgar E. Iglesias
>
> Fixes: 58ac482a66de ("introduce xlnx-dp")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1424
> Repo
be a definition
> DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
>^
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/timer/xilinx_timer.c | 27 +--
> 1 file changed, 13 insertions(+),
t; a definition
> DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
Reviewed-by: Edgar E. Iglesias
>^
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/intc/xilinx_intc.c | 28 +---
> 1 file changed, 13 insertions(+), 15 de
On Fri, Dec 30, 2022 at 08:24:19AM -0800, Richard Henderson wrote:
> Mirroring the upstream gdb xml files, the two stack boundary
> registers are separated out.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Richard Henderson
> ---
>
> I did this thinking I would b
On Thu, Dec 22, 2022 at 10:55:48PM +0100, Philippe Mathieu-Daudé wrote:
> ARM CPUs fetch instructions in little-endian.
>
> smpboot[] encoded instructions are written in little-endian.
>
> We call tswap32() on the array. tswap32 function swap a 32-bit
> value if the target endianness doesn't
to
> > break the loop.
> >
> > Signed-off-by: Markus Armbruster
> > Reviewed-by: Philippe Mathieu-Daudé
> > Reviewed-by: Alistair Francis
> > Reviewed-by: Stefano Garzarella
Reviewed-by: Edgar E. Iglesias
>
> Acked-by: Jason Wang
>
> Thanks
>
&
On Fri, Dec 16, 2022 at 03:57:06PM +0100, Bernhard Beschow wrote:
> Signed-off-by: Bernhard Beschow
Reviewed-by: Edgar E. Iglesias
> ---
> hw/ppc/virtex_ml507.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virt
On Tue, Dec 13, 2022 at 05:23:06PM +, Peter Maydell wrote:
> On Tue, 13 Dec 2022 at 16:53, Cédric Le Goater wrote:
> >
> > On 12/13/22 17:27, Richard Henderson wrote:
> > > On 12/13/22 10:21, Peter Maydell wrote:
> > >> It does seem odd, though. We have a value in host endianness
> > >> (the
On Tue, Dec 13, 2022 at 03:22:54PM +, Peter Maydell wrote:
> On Tue, 13 Dec 2022 at 14:23, Edgar E. Iglesias
> wrote:
> >
> > On Tue, Dec 13, 2022 at 02:18:42PM +, Peter Maydell wrote:
> > > On Tue, 13 Dec 2022 at 14:14, Edgar E. Iglesias
> > > wrote:
On Tue, Dec 13, 2022 at 02:18:42PM +, Peter Maydell wrote:
> On Tue, 13 Dec 2022 at 14:14, Edgar E. Iglesias
> wrote:
> >
> > On Tue, Dec 13, 2022 at 01:53:15PM +, Peter Maydell wrote:
> > > On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé
> > >
On Tue, Dec 13, 2022 at 09:17:40AM -0500, Stefan Hajnoczi wrote:
> On Tue, 13 Dec 2022 at 09:08, Philippe Mathieu-Daudé
> wrote:
> >
> > On 12/12/22 00:41, Philippe Mathieu-Daudé wrote:
> > > Hi,
> > >
> > > In the last years we had few discussions on "simplifying" QEMU (system
> > > emulation /
On Tue, Dec 13, 2022 at 01:53:15PM +, Peter Maydell wrote:
> On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé
> wrote:
> >
> > This partly revert commit d48751ed4f ("xilinx-ethlite:
> > Simplify byteswapping to/from brams") which states the
> > packet data is stored in big-endian.
> >
>
On Thu, Nov 24, 2022 at 11:50:07AM +, Peter Maydell wrote:
> Convert the cris CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/c
On Thu, Nov 24, 2022 at 11:50:12AM +, Peter Maydell wrote:
> Convert the microblaze CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/mi
any devices later.
Looks good to me!
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Alex Bennée
> ---
> target/microblaze/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
>
number
> > generation function. This FDT node is part of the DT specification.
> >
> > Reviewed-by: Edgar E. Iglesias
> > Signed-off-by: Jason A. Donenfeld
> > ---
> > hw/microblaze/boot.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > di
From: "Edgar E. Iglesias"
The following changes since commit 2906f933dd1de6d94c54881cc16ea7390a6ba300:
Merge tag 'pull-request-2022-09-20' of https://gitlab.com/thuth/qemu into
staging (2022-09-20 16:24:07 -0400)
are available in the Git repository at:
g...@github.com:edgarig
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This FDT node is part of the DT specification.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Jason A.
On Wed, Aug 31, 2022 at 03:35:19PM +0100, Alex Bennée wrote:
> Hi,
>
> Given our slowly growing range of TCG emulations and the evident
> interest in keeping up with modern processor architectures is it worth
> having an emulation focused BoF at the up-coming KVM Forum?
Hi Alex,
Yes, I'd be
On Thu, Jul 21, 2022, 6:44 PM Jason A. Donenfeld wrote:
> Hey Edgar,
>
> On Wed, Jul 20, 2022 at 9:13 AM Edgar E. Iglesias
> wrote:
> >
> >
> > On Tue, Jul 19, 2022 at 2:23 PM Jason A. Donenfeld
> wrote:
> >>
> >> If the FDT con
-by: Edgar E. Iglesias
>
> Cc: Edgar E. Iglesias
> Signed-off-by: Jason A. Donenfeld
> ---
> hw/microblaze/boot.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
> index 8b92a9801a..25ad54754e 100644
> --- a/
On Tue, May 3, 2022 at 7:12 PM Edgar E. Iglesias
wrote:
> On Tue, May 3, 2022 at 5:06 PM Frank Chang wrote:
>
>> On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias <
>> edgar.igles...@gmail.com> wrote:
>>
>>> On Tue, May 3, 2022 at 3:16 AM Frank Chang
>&
On Tue, May 3, 2022 at 5:06 PM Frank Chang wrote:
> On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias
> wrote:
>
>> On Tue, May 3, 2022 at 3:16 AM Frank Chang
>> wrote:
>>
>>> On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias <
>>> edgar.igles...
as been noticed that the irq mapping is wrong. So use the value from the
> linux device tree and the ultrascale+ reference manual.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Frederic Konrad
> ---
> hw/arm/xlnx-zynqmp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions
87-zynq-ultrascale-registers.html.
>
> Let's fix that and use macros when creating the mmio region.
Reviewed-by: Edgar E. Iglesias
>
> Fixes: 58ac482a66d ("introduce xlnx-dp")
> Signed-off-by: Frederic Konrad
> ---
> hw/display/xlnx_dp.c | 17 +
On Tue, May 03, 2022 at 04:25:43PM +0100, frederic.kon...@xilinx.com wrote:
> From: Sai Pavan Boddu
>
> Add a periodic timer which raises vblank at a frequency of 30Hz.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Sai Pavan Boddu
> Signed-off-by: Edgar E. I
On Tue, May 3, 2022 at 3:16 AM Frank Chang wrote:
> On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias
> wrote:
>
>> On Thu, Apr 28, 2022 at 5:43 PM wrote:
>>
>>> From: Frank Chang
>>>
>>> Add Xilinx AXI CDMA model, which follows
>>&
On Thu, Apr 28, 2022 at 5:43 PM wrote:
> From: Frank Chang
>
> Add Xilinx AXI CDMA model, which follows
> AXI Central Direct Memory Access v4.1 spec:
> https://docs.xilinx.com/v/u/en-US/pg034-axi-cdma
>
> Supports both Simple DMA and Scatter Gather modes.
>
Hi Frank,
Thanks for modeling this!
is-device,tpmdev=tpm0
>
> The TPM device can be seen in the memory tree and the generated device
> tree.
Hi Alistair!
You've got a typo in the subject of patch 4/6 "generating".
On the series:
Reviewed-by: Edgar E. Iglesias
Cheers,
Edgar
>
> Resolves: https://gitla
On Thu, Mar 31, 2022 at 01:53:12PM +0200, Damien Hedde wrote:
> Now we have renamed all calls to these old functions, we
> can delete the temporary inline we've defined.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
>
On Thu, Mar 31, 2022 at 01:53:11PM +0200, Damien Hedde wrote:
> All callsite are updated to the new function name
> "machine_class_allow_dynamic_device"
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
On Thu, Mar 31, 2022 at 01:53:10PM +0200, Damien Hedde wrote:
> Instead of checking if the device is a sysbus device, just check
> the newly added flag in device class.
>
> Signed-off-by: Damien Hedde
Reviewed-by: Edgar E. Iglesias
> ---
>
> v2: update the flag name
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> include/hw/boards.h | 50 +++--
> hw/core/machine.c | 10 -
> 2 files changed, 35 insertions(+), 25 deletions(-)
>
t;
Looks good to me!
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Damien Hedde
> ---
>
> v2:
> + change the flag name and put it just below user_creatable
> ---
> include/hw/qdev-core.h | 9 +
> hw/core/qdev.c | 1 +
> hw/core/sysbus.c | 1 +
>
From: "Edgar E. Iglesias"
This adds the Versal Cortex-R5s in the Real-Time Processing Unit
(RPU) subsystem.
A model of the Clock/Reset Low-power domain (CRL) is also added
allowing runtime release of the Cortex-R5s. The RPU subsystem
is largely missing but has enough to run simple bar
From: "Edgar E. Iglesias"
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
subsystem.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c| 6 +++---
hw/arm/xlnx-versal.c | 36
include/hw/arm/xlnx-ver
From: "Edgar E. Iglesias"
Add a model of the Xilinx Versal CRL.
Signed-off-by: Edgar E. Iglesias
---
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-crl.c | 421 ++
include/hw/misc/xlnx-versal-crl.h | 235 +
3 fil
From: "Edgar E. Iglesias"
Connect the CRL (Clock Reset LPD) to the Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 54 ++--
include/hw/arm/xlnx-versal.h | 4 +++
2 files changed, 56 insertions(+), 2 deletions(-)
diff
From: "Edgar E. Iglesias"
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 9 -
include/hw/arm/xlnx-versal.h | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xln
From: "Edgar E. Iglesias"
Connect the 4 TTC timers on the ZynqMP.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4
hw/arm/xlnx-zynqmp.c | 22 ++
2 files changed, 26 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/
From: "Edgar E. Iglesias"
Break out header file to allow embedding of the the TTC.
Signed-off-by: Edgar E. Iglesias
---
include/hw/timer/cadence_ttc.h | 54 ++
hw/timer/cadence_ttc.c | 32 ++--
2 files changed, 56 inserti
From: "Edgar E. Iglesias"
This adds the 4 TTC timers in the Xilinx ZynqMP.
This is for after the 7.0.0 release.
Cheers,
Edgar
Edgar E. Iglesias (2):
timer: cadence_ttc: Break out header file to allow embedding
hw/arm/xlnx-zynqmp: Connect 4 TTC timers
include/hw/arm/xlnx-zynqm
On Thu, Mar 17, 2022 at 8:15 PM Peter Maydell
wrote:
> On Wed, 16 Mar 2022 at 16:46, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > This adds the necessary modeling to support some of our firmware
> > tests at EL3 imp
From: "Edgar E. Iglesias"
Connect the ZynqMP APU Control device.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c
From: "Edgar E. Iglesias"
Connect the ZynqMP CRF - Clock Reset FPD device.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-crf.h | 211
hw
From: "Edgar E. Iglesias"
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu.h| 3 ++-
target/arm/cpu.c| 12 +++-
target/arm/hel
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP APU Control.
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +
hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +
hw/misc/m
From: "Edgar E. Iglesias"
Add an unimplemented SERDES (Serializer/Deserializer) area.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 5 +
2 files
From: "Edgar E. Iglesias"
This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.
Cheers,
Edgar
ChangeLog:
v2 -> v3:
* Make RVBAR_ELx register re
class struct, and the initialization of xcdc->read in the class init
> function wrote off the end of the memory. Add the missing line.
>
> Found by running 'check-qtest-aarch64' with a clang
> address-sanitizer build, which complains:
Reviewed-by: Edgar E. Iglesias
On Fri, Feb 18, 2022 at 01:37:51PM +, Peter Maydell wrote:
> On Thu, 3 Feb 2022 at 14:01, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add a model of the Xilinx ZynqMP CRF. At the moment this
> > is mostly a stub mode
On Mon, Feb 7, 2022 at 5:24 PM Alexander Graf wrote:
>
> On 07.02.22 17:06, Philippe Mathieu-Daudé wrote:
> > On 7/2/22 16:59, Alexander Graf wrote:
> >>
> >> On 07.02.22 16:52, Edgar E. Iglesias wrote:
> >
> >>> Both Versal and ZynqMP requir
On Mon, Feb 7, 2022 at 4:33 PM Alexander Graf wrote:
>
> On 07.02.22 16:22, Peter Maydell wrote:
> > On Mon, 7 Feb 2022 at 14:21, Alexander Graf wrote:
> >>
> >> On 27.01.22 16:46, Peter Maydell wrote:
> >>> Change the Xilinx ZynqMP-based board xlnx-zcu102 to use the new
> >>> boot.c
From: "Edgar E. Iglesias"
Connect the ZynqMP APU Control device.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c | 25 +++--
2 files c
From: "Edgar E. Iglesias"
Connect the ZynqMP CRF - Clock Reset FPD device.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16
2 files c
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP APU Control.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 95 +
hw/misc/xlnx-zynqmp-apu-ctrl.c | 254 +
hw/misc/meson.build| 1
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-crf.h | 213
hw/misc/xlnx-zynqmp-crf.c
From: "Edgar E. Iglesias"
This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.
I've only tested this on top of Peter's recent PSCI emulation fixe
From: "Edgar E. Iglesias"
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/
From: "Edgar E. Iglesias"
Add an unimplemented SERDES (Serializer/Deserializer) area.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 5 +
2 files
On Mon, Jan 31, 2022 at 06:27:09PM +0100, Edgar E. Iglesias wrote:
> On Mon, Jan 31, 2022 at 03:35:57PM +, Francisco Iglesias wrote:
> > Hi Edgar,
> >
> > A couple of minor comments below, looks good to me otherwise!
> >
> > On Mon, Jan 31, 2022 at 12:12:03
On Mon, Jan 31, 2022 at 03:35:57PM +, Francisco Iglesias wrote:
> Hi Edgar,
>
> A couple of minor comments below, looks good to me otherwise!
>
> On Mon, Jan 31, 2022 at 12:12:03AM +0100, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
>
On Mon, Jan 31, 2022 at 03:32:25PM +, Peter Maydell wrote:
> On Sun, 30 Jan 2022 at 23:12, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add unimplemented SERDES area.
>
> What's a SERDES ? A brief description might b
On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote:
> On 31/1/22 00:12, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add a model of the Xilinx ZynqMP APU Control.
> >
> > Signed-off-by: Edgar E. Iglesias
> >
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-crf.h | 209 +++
hw/misc/xlnx-zynqmp-crf.c | 270 +
From: "Edgar E. Iglesias"
Connect the ZynqMP APU Control device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c | 25 +++--
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/include/h
From: "Edgar E. Iglesias"
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/
From: "Edgar E. Iglesias"
Connect the ZynqMP CRF - Clock Reset FPD device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16
2 files changed, 18 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/
From: "Edgar E. Iglesias"
Add unimplemented SERDES area.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xln
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP APU Control.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +
hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +
hw/misc/meson.build| 1
From: "Edgar E. Iglesias"
This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.
I've only tested this on top of Peter's recent PSCI emulation fixe
all.
>
> I have tested this with make check/check-acceptance and also with some
> test images I have locally (including highbank and midway), but I
> don't have test images for most of these boards, and in particular I
> don't really have anything that exercises "run guest EL3 code" f
From: "Edgar E. Iglesias"
This should be applied on top of Peter Maydell's
"arm: Fix handling of unrecognized functions in PSCI emulation"
patch series.
This fixes an issue reported by Peter Maydell. We should
always call arm_load_kernel() regardless of kernel_filename being
From: "Edgar E. Iglesias"
Always call arm_load_kernel() regardless of kernel_filename being
set. This is needed because arm_load_kernel() sets up reset for
the CPUs.
Fixes: 6f16da53ff (hw/arm: versal: Add a virtual Xilinx Versal board)
Reported-by: Peter Maydell
Signed-off-b
On Thu, Jan 27, 2022 at 2:10 PM Peter Maydell
wrote:
> On Fri, 2 Nov 2018 at 17:24, Peter Maydell
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add a virtual Xilinx Versal board.
> >
> > This board is based on the Xilinx Versal SoC. Th
On Thu, Jan 27, 2022 at 6:14 PM Peter Maydell
wrote:
> Ping for code review? This is a nice short easy one :-)
>
Looks good comparing with the Pseudocode. I tried reading the chapters
about these exceptions but couldn't find a clear description :-)
Reviewed-by: Edgar E. Iglesias
>
On Tue, Dec 14, 2021 at 3:49 PM Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Tue, Dec 14, 2021 at 12:37:43PM +0100, Markus Armbruster wrote:
> >> Mark Burton writes:
> >>
> >> > I realise it’s very short notice, but what about having a discussion
> today at 15:00 ?
> >>
> >>
On Tue, Nov 23, 2021 at 10:34:25AM +, Francisco Iglesias wrote:
> Connect the OSPI flash memory controller model (including the source and
> destination DMA).
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/arm/xlnx-ver
On Tue, Nov 23, 2021 at 10:34:21AM +, Francisco Iglesias wrote:
> Include ptimer.h and stream.h in the header for being able to build and
> reuse the DMA model (the first usage of StreamSink, StreamCanPushNotifyFn
> and ptimer_state is in the header).
Reviewed-by: Edgar E.
On Tue, Nov 23, 2021 at 10:34:28AM +, Francisco Iglesias wrote:
> List myself as maintainer for the Xilinx Versal OSPI controller.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(
On Tue, Nov 23, 2021 at 10:34:27AM +, Francisco Iglesias wrote:
> Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
> controller.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal-virt.c | 23 +++
On Tue, Nov 23, 2021 at 10:34:19AM +, Francisco Iglesias wrote:
> Add a model of Versal's PMC SLCR (system-level control registers).
Acked-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> Signed-off-by: Edgar E. Iglesias
> ---
> h
On Wed, Nov 17, 2021 at 02:18:41PM +, Francisco Iglesias wrote:
> Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
> controller.
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal-virt.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff
ospi.h"
> +#include "hw/dma/xlnx_csu_dma.h"
> #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
>
> #define TYPE_XLNX_VERSAL "xlnx-versal"
> @@ -80,6 +82,12 @@ struct Versal {
> struct {
> SDHCIState sd[XLNX_VERSAL_NR_SDS];
> XlnxVersalPmcIouSlcr slcr;
> +
> +XlnxVersalOspi ospi;
> +XlnxCSUDMA ospi_dma_src;
> +XlnxCSUDMA ospi_dma_dst;
> +MemoryRegion lospi_mr;
> +qemu_or_irq ospi_irq;
I wonder if we should do something like?
struct {
XlnxVersalOspi ospi;
XlnxCSUDMA dma_src;
XlnxCSUDMA dma_dst;
MemoryRegion linear_mr;
qemu_or_irq irq;
} ospi;
But either way is OK with me:
Reviewed-by: Edgar E. Iglesias
On Wed, Nov 17, 2021 at 02:18:40PM +, Francisco Iglesias wrote:
> Add support for Micron Xccela flash mt35xu01g.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --g
On Wed, Nov 17, 2021 at 02:18:34PM +, Francisco Iglesias wrote:
> Connect Versal's PMC SLCR (system-level control registers) model.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal.c | 18 ++
> i
On Wed, Nov 17, 2021 at 02:18:38PM +, Francisco Iglesias wrote:
> Add a model of Xilinx Versal's OSPI flash memory controller.
Thanks Francisco,
If you haven't already in this series, I think you should also add yourself
in MAINTAINERS for this model.
Reviewed-by: Edgar E. Igles
On Wed, Nov 17, 2021 at 02:18:37PM +, Francisco Iglesias wrote:
> Implement the DMA control interface for allowing control of DMA operations
> from inside models that contain instances of (and reuse) the Xilinx CSU
> DMA.
Reviewed-by: Edgar E. Iglesias
>
> Signed-of
t; signaling.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/dma/dma-ctrl.c | 31
> hw/dma/meson.build| 1 +
> include/hw/dma/dma-ctrl.h | 74
> +++
&
On Wed, Nov 17, 2021 at 02:18:33PM +, Francisco Iglesias wrote:
> Add a model of Versal's PMC SLCR (system-level control registers).
>
> Signed-off-by: Francisco Iglesias
> Signed-off-by: Edgar E. Iglesias
> ---
> hw/misc/meson.build|5 +-
>
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