[PATCH v3 0/4] Check clock connection between STM32L4x5 RCC and peripherals

ests : consolidating `get_clock_freq_hz()` in a header and making appropriate changes in stm32l4x5q_*-test.c Signed-off-by: Inès Varhol Inès Varhol (4): hw/misc: Create STM32L4x5 SYSCFG clock hw/char: Use v2 VMStateDescription for STM32L4x5 USART hw/clock: Expose 'qtest-clock-period' QOM

[PATCH v3 4/4] tests/qtest: Check STM32L4x5 clock connections

For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5.h | 43 + tests/qtest/stm32l4x5_gpio-test.c | 23 +++ tests

[PATCH v3 1/4] hw/misc: Create STM32L4x5 SYSCFG clock

This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: Inès Varhol --- include/hw/misc/stm32l4x5_syscfg.h | 1 + hw/arm/stm32l4x5_soc.c | 2 ++ hw/misc/stm32l4x5_syscfg.c | 19 +-- 3

[PATCH v3 3/4] hw/clock: Expose 'qtest-clock-period' QOM property for QTests

Expose the clock period via the QOM 'qtest-clock-period' property so it can be used in QTests. This property is only accessible in QTests (not via HMP). Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Inès Varhol --- docs/devel/clocks.rst | 3 +++ hw/core/clock.c | 16

[PATCH v3 2/4] hw/char: Use v2 VMStateDescription for STM32L4x5 USART

`vmstate_stm32l4x5_usart_base` namely uses `VMSTATE_CLOCK` so version needs to be 2. Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 02f666308c

[PATCH v2 3/3] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI

-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 24 +++- 1 file changed, 11 insertions(+), 13 deletions

[PATCH v2 0/3] Connect STM32L4x5 USART devices to the EXTI

the handling of configurable line interrupts in the EXTI. Changes from v1 (2nd commit): - add STM32L4x5 EXTI status fields `irq_levels` to track configurable irq levels and do edge detection - use `qemu_set_irq` instead of qemu_irq_raise/lower Signed-off-by: Inès Varhol Inès Varhol (3): hw/misc

[PATCH v2 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants

constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell --- include/hw/misc/stm32l4x5_exti.h | 4 ++-- hw/misc/stm32l4x5_exti.c | 6 ++ 2 files changed, 4 insertions(+), 6

[PATCH v2 2/3] hw/misc: In STM32L4x5 EXTI, handle direct and configurable interrupts

interrupts (interrupts without configurable edge). The implementation of configurable interrupts (interrupts supporting edge selection) was incorrectly expecting alternating input levels : this commits adds a new status field `irq_levels` to actually detect edges. Signed-off-by: Inès Varhol ---

[PATCH 0/3] Connect STM32L4x5 USART devices to the EXTI

STM32L4x5 EXTI was handling only configurable interrupts (such as those coming from STM32L4x5 SYSCFG which was the only device connected to the EXTI). This patch adds support for direct line interrupts and connects the existing STM32L4x5 USART devices to the EXTI. Signed-off-by: Inès Varhol

[PATCH 3/3] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI

-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: Inès Varhol --- hw/arm/stm32l4x5_soc.c | 24 +++- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm

[PATCH 2/3] hw/misc: In STM32L4x5 EXTI, handle direct line interrupts

interrupts (interrupts without configurable edge), as well as a comment that will be useful to connect other devices to the EXTI. Signed-off-by: Inès Varhol --- hw/misc/stm32l4x5_exti.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/misc/stm32l4x5_exti.c

[PATCH 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants

constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: Inès Varhol --- include/hw/misc/stm32l4x5_exti.h | 4 ++-- hw/misc/stm32l4x5_exti.c | 6 ++ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git

[PATCH 3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency

This QOM property will be used to check the clock frequency from QTests. Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index fc5dcac0c4

[PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections

For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5.h | 40 + tests/qtest/stm32l4x5_gpio-test.c | 23

[PATCH 0/4] Check clock connection between STM32L4x5 RCC and peripherals

tm32l4x5q_*-test.c Signed-off-by: Inès Varhol Inès Varhol (4): hw/misc: Create STM32L4x5 SYSCFG clock hw/gpio: Handle clock migration in STM32L4x5 gpios hw/char: Add QOM property for STM32L4x5 USART clock frequency tests/qtest: Check STM32L4x5 clock connections include/hw/misc/stm32l4x5

[PATCH 2/4] hw/gpio: Handle clock migration in STM32L4x5 gpios

STM32L4x5 GPIO wasn't migrating its clock. Signed-off-by: Inès Varhol --- hw/gpio/stm32l4x5_gpio.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c index 71bf5fddb2..30d8d6cba4 100644 --- a/hw/gpio/stm32l4x5_gpio.c

[PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock

This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. A read-only QOM property allowing to read the clock frequency is added (it will be used in a QTest). Signed-off-by: Inès Varhol --- Hello, Several people noticed that replicating

Re: [PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock

- Le 7 Mai 24, à 11:50, peter maydell peter.mayd...@linaro.org a écrit : > On Sun, 5 May 2024 at 15:06, Inès Varhol wrote: >> >> Signed-off-by: Inès Varhol > > In general you should try to avoid commits with no commit message. > Sometimes there really isn't any

Re: [PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections

- Le 6 Mai 24, à 6:16, Thomas Huth th...@redhat.com a écrit : > On 05/05/2024 16.05, Inès Varhol wrote: >> For USART, GPIO and SYSCFG devices, check that clock frequency before >> and after enabling the peripheral clock in RCC is correct. >> >> Signed-off-by: I

[PATCH] hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 02f666308c..fc5dcac0c4 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char

[PATCH 3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency

Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index fc5dcac0c4..ee7727481c 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -26,6 +26,7

[PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock

Signed-off-by: Inès Varhol --- include/hw/misc/stm32l4x5_syscfg.h | 1 + hw/arm/stm32l4x5_soc.c | 2 ++ hw/misc/stm32l4x5_syscfg.c | 26 ++ 3 files changed, 29 insertions(+) diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc

[PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections

For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol --- Hello, Should these tests be regrouped in stm32l4x5_rcc-test.c ? Best regards, Inès Varhol tests/qtest/stm32l4x5_gpio-test.c | 39

[PATCH 2/4] hw/gpio: Handle clock migration in STM32L4x5 gpios

Signed-off-by: Inès Varhol --- hw/gpio/stm32l4x5_gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c index 71bf5fddb2..14e6618d30 100644 --- a/hw/gpio/stm32l4x5_gpio.c +++ b/hw/gpio/stm32l4x5_gpio.c @@ -20,6 +20,7 @@ #include "

[PATCH 0/4] Check clock connection between STM32L4x5 RCC and peripherals

the expected results. Signed-off-by: Inès Varhol Inès Varhol (4): hw/misc: Create STM32L4x5 SYSCFG clock hw/gpio: Handle clock migration in STM32L4x5 gpios hw/char: Add QOM property for STM32L4x5 USART clock frequency tests/qtest: Check STM32L4x5 clock connections include/hw/misc

[PATCH v6 1/5] hw/display : Add device DM163

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 59 + hw/display/dm163.c | 349 + hw/display/Kconfig

[PATCH v6 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/stm32l4x5_soc.c | 6 -- tests/qtest/stm32l4x5_gpio-test.c | 13 - tests/qtest/stm32l4x5_syscfg-test.c | 17 ++--- 3 files changed, 22 insertions(+), 14 deletions(-) diff

[PATCH v6 5/5] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/dm163-test.c | 194 +++ tests/qtest/meson.build | 2 + 2 files changed, 196 insertions(+) create mode 100644 tests/qtes

[PATCH v6 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 46 - 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index

[PATCH v6 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw

[PATCH v6 0/5] Add device DM163 (led driver, matrix colors shield & display)

sts accordingly) - restricting DM163 test to ARM & DM163 availability - using `object_class_by_name()` to check for DM163 presence at run-time - exporting SYSCFG inputs to the SoC (and adapting tests accordingly) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé

[PATCH] hw/misc : Correct 5 spaces indents in stm32l4x5_exti

Signed-off-by: Inès Varhol --- hw/misc/stm32l4x5_exti.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 9fd859160d..5c55ee4268 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -59,22

[PATCH v5 5/5] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/dm163-test.c | 194 +++ tests/qtest/meson.build | 2 + 2 files changed, 196 insertions(+) create mode 100644 tests/qtes

[PATCH v5 1/5] hw/display : Add device DM163

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 59 + hw/display/dm163.c | 334 + hw/display/Kconfig | 3 + hw/display/meson.build

[PATCH v5 0/5] Add device DM163 (led driver, matrix colors shield & display)

163 test to ARM & DM163 availability - using `object_class_by_name()` to check for DM163 presence at run-time - exporting SYSCFG inputs to the SoC (and adapting tests accordingly) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (5): hw/display : Add device DM163 hw/arm

[PATCH v5 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/stm32l4x5_soc.c | 6 -- tests/qtest/stm32l4x5_gpio-test.c | 13 - tests/qtest/stm32l4x5_syscfg-test.c | 17 ++--- 3 files changed, 22 insertions(+), 14 deletions(-) diff

[PATCH v5 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 46 - 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index

[PATCH v5 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw

[PATCH v2] tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`

The messages for assertions using hexadecimal numbers will be easier to understand with `g_assert_cmphex`. Cases changed : "cmpuint.*0x", "cmpuint.*<<" Signed-off-by: Inès Varhol --- tests/qtest/aspeed_fsi-test.c | 20 ++-- tests/qtest/cmsdk-apb-dualtimer-te

Re: [PATCH] tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`

- Le 14 Avr 24, à 18:19, Philippe Mathieu-Daudé phi...@linaro.org a écrit : > Hi Inès, Hello Philippe ! > > On 14/4/24 15:24, Inès Varhol wrote: >> The messages for STM32L4x5 tests will be easier to understand with >> `g_assert_cmphex` since the comparisions were

[PATCH] tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`

The messages for STM32L4x5 tests will be easier to understand with `g_assert_cmphex` since the comparisions were made with hexadecimal numbers. Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_exti-test.c | 138 ++-- tests/qtest/stm32l4x5_syscfg-test.c | 74

[PATCH v4 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Minier Signed-off-by: Inès Varhol --- hw/arm/stm32l4x5_soc.c | 6 -- tests/qtest/stm32l4x5_gpio-test.c | 12 +++- tests/qtest/stm32l4x5_syscfg-test.c | 16 +--- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm

[PATCH v4 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 2b570b3e09

[PATCH v4 0/5] Add device DM163 (led driver, matrix colors shield & display)

; DM163 availability - using `object_class_by_name()` to check for DM163 presence at run-time - exporting SYSCFG inputs to the SoC (and adapting tests accordingly) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (5): hw/display : Add device DM163 hw/arm : Pass STM32L4x5 SYSCF

[PATCH v4 5/5] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/dm163-test.c | 192 +++ tests/qtest/meson.build | 5 + 2 files changed, 197 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/test

[PATCH v4 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 44 + 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa43fc..2b570b3e09 100644 --- a/hw/arm

[PATCH v4 1/5] hw/display : Add device DM163

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 58 + hw/display/dm163.c | 333 + hw/display/Kconfig | 3 + hw/display/meson.build

Re: [PATCH v6 0/3] Add device STM32L4x5 GPIO

Le 5 Mar 24, à 17:10, peter maydell peter.mayd...@linaro.org a écrit : > On Sat, 24 Feb 2024 at 10:54, Inès Varhol > wrote: >> >> This patch adds a new device STM32L4x5 GPIO device and is part >> of a series implementing the STM32L4x5 with a few peripherals. > &g

[PATCH v7 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- include/hw/arm/stm32l4x5_soc.h | 2 + include/hw/gpio/stm32l4x5_gpio.h | 1 + include/hw/misc/stm32l4x5_syscfg.h | 3 +- hw/arm/stm32l4x5_soc.c | 71

[PATCH v7 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_gpio-test.c | 551 ++ tests/qtest/meson.build

[PATCH v7 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +

[PATCH v7 0/3] Add device STM32L4x5 GPIO

-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest testcase MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/arm/stm32l4x5_soc.h | 2

[PATCH v3 1/5] hw/display : Add device DM163

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 57 ++ hw/display/dm163.c | 308 + hw/display/Kconfig | 3 + hw/display/meson.build

[PATCH v3 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 44 + 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa43fc..2b570b3e09 100644 --- a/hw/arm

[PATCH v3 5/5] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/dm163-test.c | 192 +++ tests/qtest/meson.build | 5 + 2 files changed, 197 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/test

[PATCH v3 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Minier Signed-off-by: Inès Varhol --- Hello, If SYSCFG inputs are exposed, should GPIOs be part of the board rather than the SoC? Best regards, Ines hw/arm/stm32l4x5_soc.c | 6 -- tests/qtest/stm32l4x5_gpio-test.c | 12 +++- tests/qtest/stm32l4x5_syscfg-test.c | 16

[PATCH v3 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 2b570b3e09

[PATCH v3 0/5] Add device DM163 (led driver, matrix colors shield & display)

Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (5): hw/display : Add device DM163 hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC hw/arm : Create Bl475eMachineState hw/arm : Connect DM163 to B-L475E-IOT01A tests/qtest : Add testcase for DM163 docs/system/arm/b-l475e-iot

[PATCH v2 5/5] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/dm163-test.c | 192 +++ tests/qtest/meson.build | 5 + 2 files changed, 197 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/test

[PATCH v2 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Minier Signed-off-by: Inès Varhol --- Hello, If SYSCFG inputs are exposed, should GPIOs be part of the board rather than the SoC? Best regards, Ines hw/arm/stm32l4x5_soc.c | 6 -- tests/qtest/stm32l4x5_gpio-test.c | 12 +++- tests/qtest/stm32l4x5_syscfg-test.c | 16

[PATCH v2 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 2b570b3e09

[PATCH v2 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/b-l475e-iot01a.c | 44 + 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa43fc..2b570b3e09 100644 --- a/hw/arm

[PATCH v2 1/5] hw/display : Add device DM163

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 57 ++ hw/display/dm163.c | 308 + hw/display/Kconfig | 3 + hw/display/meson.build

[PATCH v2 0/5] Add device DM163 (led driver, matrix colors shield & display)

un-time - exporting SYSCFG inputs to the SoC (and adapting tests accordingly) Thank you for your review Philippe :) Based-on: 220240224105417.195674-1-ines.var...@telecom-paris.fr ([PATCH v6 0/3] Add device STM32L4x5 GPIO) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (5

[PATCH v6 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/gpio/stm32l

[PATCH v6 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- include/hw/arm/stm32l4x5_soc.h | 2 + include/hw/gpio/stm32l4x5_gpio.h | 1 + include/hw/misc/stm32l4x5_syscfg.h | 3 +- hw/arm/stm32l4x5_soc.c | 71

[PATCH v6 0/3] Add device STM32L4x5 GPIO

`get_gpio_pins_to_disconnect()`, correct `stm32l4x5_gpio_init()` and initialize the clock, add a realize function - update MAINAINERS Based-on: 20240219200908.49551-1-arnaud.min...@telecom-paris.fr ([PATCH v5 0/8] Add device STM32L4x5 RCC) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès

[PATCH v6 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_gpio-test.c | 586 ++ tests/qtest/meson.build

[PATCH v5 0/3] Add device STM32L4x5 GPIO

-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest testcase MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2

[PATCH v5 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- include/hw/arm/stm32l4x5_soc.h | 2 + hw/arm/stm32l4x5_soc.c | 68 +++--- hw/arm/Kconfig | 3 +- 3 files changed, 58 insertions(+), 15 deletions

[PATCH v5 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/gpio/stm32l

[PATCH v5 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_gpio-test.c | 586 ++ tests/qtest/meson.build

[PATCH v2 1/2] hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs

Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI") Signed-off-by: Inès Varhol --- include/hw/arm/stm32l4x5_soc.h | 4 ++ hw/arm/stm32l4x5_soc.c | 80 +- 2 files changed, 74 insertions(+), 10 deletions(-) diff --git a/incl

[PATCH v2 0/2] hw/arm: Fix STM32L4x5 EXTI to CPU irq fan-in connections

: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI") Signed-off-by: Inès Varhol Inès Varhol (2): hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs tests/qtest: Check that EXTI fan-in irqs are correctly connected include/hw/arm/stm32l4x5_soc.h| 4

[PATCH v2 2/2] tests/qtest: Check that EXTI fan-in irqs are correctly connected

This commit adds a QTest that verifies each input line of a specific EXTI OR gate can influence the output line. Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell --- Hello, I expected this test to fail after switching the two patch commits, but it didn't. I'm mentionning it in case

[PATCH 1/2] hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs

Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI") Signed-off-by: Inès Varhol --- hw/arm/stm32l4x5_soc.c | 69 -- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index

[PATCH 2/2] tests/qtest: Check that EXTI fan-in irqs are correctly connected

This commit adds a QTest that verifies each input line of a specific EXTI OR gate can influence the output line. Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_exti-test.c | 97 +++ 1 file changed, 97 insertions(+) diff --git a/tests/qtest/stm32l4x5_exti

[PATCH 0/2] hw/arm: Fix STM32L4x5 EXTI to CPU irq fan-in connections

even before the fix : when any fan-in input line is raised, the output is raised too. Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI") Signed-off-by: Inès Varhol Inès Varhol (2): hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs tests/qtest: Check tha

Re: [PATCH v8 2/3] hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC

Hi, > De: Philippe > Envoyé: mercredi 7 février 2024 23:02 CET >  > Hi Inès, >  > (this is now commit 52671f69f7). >  > On 9/1/24 17:06, Inès Varhol wrote: > > Tested-by: Philippe Mathieu-Daudé > > Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 0/3] Add device DM163 (led driver, matrix colors shield & display)

Hello, > De: "Philippe Mathieu-Daudé" > Envoyé: Lundi 5 Février 2024 15:03:59 > > Hi Inès, > > On 26/1/24 20:31, Inès Varhol wrote: > > This device implements the IM120417002 colors shield v1.1 for Arduino > > (which relies on the DM163 8x3-channel led

Re: [PATCH 2/3] hw/arm : Connect DM163 to STM32L4x5

Hello ! > De: "Philippe Mathieu-Daudé" > Envoyé: Lundi 5 Février 2024 14:46:58 > > Hi Inès, > > On 26/1/24 20:31, Inès Varhol wrote: > > Signed-off-by: Arnaud Minier > > Signed-off-by: Inès Varhol > > --- > > hw/arm/Kconfig

[PATCH v4 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- include/hw/arm/stm32l4x5_soc.h | 2 + hw/arm/stm32l4x5_soc.c | 78 -- hw/arm/Kconfig | 3 +- 3 files changed, 68 insertions(+), 15 deletions(-) diff --git a/include/hw/arm

[PATCH v4 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/gpio/stm32l4x5_gpio.h | 70 + hw/gpio/stm32l

[PATCH v4 0/3] Add device STM32L4x5 GPIO

function - update MAINAINERS Based-on: 20240130160656.113112-1-arnaud.min...@telecom-paris.fr ([PATCH v4 0/8] Add device STM32L4x5 RCC) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

[PATCH v4 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/stm32l4x5_gpio-test.c | 586 ++ tests/qtest/meson.build

[PATCH 1/3] hw/display : Add device DM163

Signed-off-by: Inès Varhol --- hw/display/Kconfig | 3 + hw/display/dm163.c | 307 + hw/display/meson.build | 1 + hw/display/trace-events| 13 ++ include/hw/display/dm163.h | 57 +++ 5 files changed, 381 insertions(+) create

[PATCH 3/3] tests/qtest : Add testcase for DM163

device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/dm163-test.c | 192 +++ tests/qtest/meson.build | 1 + 2 files changed, 193 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/test

[PATCH 0/3] Add device DM163 (led driver, matrix colors shield & display)

4x5 GPIO) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/display : Add device DM163 hw/arm : Connect DM163 to STM32L4x5 tests/qtest : Add testcase for DM163 hw/arm/Kconfig | 1 + hw/arm/stm32l4x5_soc.c | 55 +- hw/display/Kcon

[PATCH 2/3] hw/arm : Connect DM163 to STM32L4x5

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 1 + hw/arm/stm32l4x5_soc.c | 55 +- include/hw/arm/stm32l4x5_soc.h | 3 ++ 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw

[PATCH v3 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 78 -- include/hw/arm/stm32l4x5_soc.h | 2 + 3 files changed, 68 insertions(+), 15 deletions(-) diff --git a/hw/arm/Kconfig b/hw

[PATCH v3 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/gpio/Kconfig| 3 + hw/gpio/m

[PATCH v3 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_gpio-test.c | 586

[PATCH v3 0/3] Add device STM32L4x5 GPIO

Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest testcase MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/arm/Kconfig

[PATCH v2 1/3] hw/gpio: Implement STM32L4x5 GPIO

ns instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- MAINTAINERS| 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/gpio/Kconfig| 3 + hw/gpio/m

[PATCH v2 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 79 -- include/hw/arm/stm32l4x5_soc.h | 2 + 3 files changed, 69 insertions(+), 15 deletions(-) diff --git a/hw/arm/Kconfig b/hw

[PATCH v2 0/3] Add device STM32L4x5 GPIO

`get_gpio_pins_to_disconnect()`, correct `stm32l4x5_gpio_init()` and initialize the clock, add a realize function - update MAINAINERS Based-on: 20240118091107.87831-1-arnaud.min...@telecom-paris.fr ([PATCH v2 0/7] Add device STM32L4x5 RCC) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès

[PATCH v2 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_gpio-test.c | 520 ++ 2 files changed, 522 insertions(+), 1 deletion(-) create mode 100644 tests

[PATCH 0/3] Add device STM32L4x5 GPIO

-on: 20240118091107.87831-1-arnaud.min...@telecom-paris.fr ([PATCH v2 0/7] Add device STM32L4x5 RCC) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest

[PATCH 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

the desired result in ODR. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_gpio-test.c | 526 ++ 2 files changed, 528 insertions(+), 1 deletion(-) create mode 100644 tests

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