On 20/6/23 01:36, Joel Stanley wrote:
The phb error macros add a newline for you, so remove the second one to
avoid double whitespace.
Signed-off-by: Joel Stanley
---
hw/pci-host/pnv_phb4.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Philippe
On 19/6/23 16:02, Richard Henderson wrote:
One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all. This leads to
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
for Apple M1 cpus.
We already have a check for ARMv8-A never
On 9/6/23 04:23, Richard Henderson wrote:
This method uses one uint32_t * 256 table instead of 4,
which means its data cache overhead is less.
Signed-off-by: Richard Henderson
---
crypto/aes.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> Use #ifdef, #ifndef for brevity and add comments to #endif that are
> more than a few lines apart for clarity.
These will collide with the SOFTMMU ifdef changes that Philippe is
working on I think? They seem okay but maybe wait until
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> After previous changes the hypercall handling in 7xx and 74xx
> exception handlers can be folded into one if statement to simpilfy
> this code.
Simplify and add unlikely?
I like to avoid slipping in improvements with cleanups. Arguably
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> Some helpers only have a CPUState local to call cpu_interrupt_exittb()
> but we can use env_cpu for that and remove the local.
>
> Signed-off-by: BALATON Zoltan
I have less issue with this one.
Acked-by: Nicholas Piggin
> ---
>
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> Use the env_cpu function to get the CPUState for cpu_abort. These are
> only needed in case of fatal errors so this allows to avoid casting
> and storing CPUState in a local variable wnen not needed.
>
Eh, this is still replacing less
On 19/6/23 19:14, Alex Bennée wrote:
Lets try and keep the overview of the sub-system digestible by
splitting the core API stuff into a separate file. As QOM and QDEV
work together we should also try and enumerate the qdev_ functions.
Currently this is a little broken as kerneldoc doesn't
On 19/6/23 19:14, Alex Bennée wrote:
Mention that QOM-ified devices already have support for registering
the description.
Signed-off-by: Alex Bennée
---
include/migration/vmstate.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> From: Nicholas Piggin
>
> Unlike sc, for scv a facility unavailable interrupt must be generated
> if FSCR[SCV]=0 so we can't raise the exception with nip set to next
> instruction but we can move advancing nip if the FSCR check passes
On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back
On Sun Jun 18, 2023 at 7:53 PM AEST, Daniel Henrique Barboza wrote:
> Nick,
>
> Do you plan to send a new version of this patch with a spapr_nested.h
> header included? Otherwise I'll pick this one as is.
Hey Daniel,
I'll send another series shortly with the header split out.
Thanks,
Nick
From: Foxes Hung
Signed-off-by: Foxes Hung
---
semihosting/syscalls.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c
index 68899ebb1c..1a5d39da01 100644
--- a/semihosting/syscalls.c
+++ b/semihosting/syscalls.c
@@ -281,6 +281,9 @@ static
On Tue Jun 20, 2023 at 3:14 AM AEST, Peter Maydell wrote:
> On Mon, 19 Jun 2023 at 18:03, Richard Henderson
> wrote:
> >
> > On 6/19/23 17:55, Peter Maydell wrote:
> > > On Mon, 19 Jun 2023 at 16:49, Richard Henderson
> > > wrote:
> > >>
> > >> On 6/5/23 08:27, Nicholas Piggin wrote:
> > >>> On
From: Foxes Hung
Signed-off-by: Foxes Hung
---
gdbstub/syscalls.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdbstub/syscalls.c b/gdbstub/syscalls.c
index 02e3a8f74c..4c6b5f728b 100644
--- a/gdbstub/syscalls.c
+++ b/gdbstub/syscalls.c
@@ -126,7 +126,7 @@ void
>-Original Message-
>From: Avihai Horon
>Sent: Monday, June 19, 2023 7:14 PM
...
>> a/hw/vfio/migration.c b/hw/vfio/migration.c index
>> 6b58dddb8859..bc51aa765cb8 100644
>> --- a/hw/vfio/migration.c
>> +++ b/hw/vfio/migration.c
>> @@ -632,42 +632,41 @@ int64_t
From: Huasen Zhang
Hello,
On Sat, 17 Jun 2023 11:42:06 +0200 Marc-André Lureau <
marcandre.lur...@redhat.com> wrote:
Hi
> On Fri, Jun 16, 2023 at 7:41 AM Zhang Huasen
> wrote:
>
> > From: Huasen Zhang
> >
> > Hello,
> >
> > On Thu, 15 Jun 2023 12:57:55 +0200 Marc-André Lureau <
> >
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, and require the explicit use of cache
management instructions as well as an instruction barrier to make
code updates
From: John Högberg
https://gitlab.com/qemu-project/qemu/-/issues/1034
Signed-off-by: John Högberg
---
tests/tcg/aarch64/Makefile.target | 3 +-
tests/tcg/aarch64/icivau.c| 169 ++
2 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644
The test cases have been changed in v3 to fix some issues pointed out in
code review. The main change is that the tests no longer naively copy C
code around, opting instead to have hard-coded binary payloads. Given
the small amount of code I found that the workarounds for position-
independence
On Thu, 8 Jun 2023, BALATON Zoltan wrote:
On Thu, 8 Jun 2023, Michael S. Tsirkin wrote:
On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote:
On 07/06/2023 21:01, BALATON Zoltan wrote:
On pegasos2 which has ACPI as part of VT8231 south bridge the board
firmware writes PM control
The phb error macros add a newline for you, so remove the second one to
avoid double whitespace.
Signed-off-by: Joel Stanley
---
hw/pci-host/pnv_phb4.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index
This patch adds support for the emulation of different density lines
(low, medium, and high). A new class property stm32f100-soc.density=
has been introduced to allow users to state the desired configuration.
That property is recognized by a new machine, stm32f1-generic. The SOC
is configured
"frankwmiller frankwmiller.net" writes:
> Greetings,
>
> I've been contemplating using QEMU for faster-than-real-time execution of
> SPARC executables on an X86-64 machine.
> It appears from the base architecture of QEMU that this is not possible if
> QEMU is using JIT of the SPARC to
Hi Alistair,
On Wed, Apr 20, 2022 at 03:52:48PM +1000, Alistair Francis wrote:
> From: Alistair Francis
>
> Imply the TPM sysbus devices. This allows users to add TPM devices to
> the RISC-V virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2
Greetings,
I've been contemplating using QEMU for faster-than-real-time execution of SPARC
executables on an X86-64 machine. It appears from the base architecture of
QEMU that this is not possible if QEMU is using JIT of the SPARC to x86-84
since the resulting x86-64 will run on the
> On 19 Jun 2023, at 16.02, Richard Henderson
> wrote:
>
> One cannot test for feature aa32_simd_r32 without first
> testing if AArch32 mode is supported at all. This leads to
>
> qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
>
> for Apple M1 cpus.
>
> We
Richard Henderson writes:
> On 4/19/23 17:12, Alex Bennée wrote:
>> The lack of SVE memory instrumentation has been an omission in plugin
>> handling since it was introduced. Fortunately we can utilise the
>> probe_* functions to force all all memory access to follow the slow
>> path. We do
On Mon, Jun 19, 2023 at 09:29:26PM +0530, Ani Sinha wrote:
> When a device is plugged into a PCIE root port, it can only be plugged into
> slot
> 0. Hotplugging a device into a slot other than slot 0 is invalid and should be
> prevented. This change ensures that we throw an error if the user
Anton Kochkov writes:
> Add crossplatform Meson file to build TCG plugins since
> the Makefile makes wrong assumptions about it being used only
> on Linux. Tested on Linux and macOS.
I think you should go the whole hog and remove the existing makefile
machinery. Otherwise it will be confusing
On Wed, Jun 14, 2023 at 10:56:22PM +, Alexander Graf wrote:
> Apple has its own virtio-blk PCI device ID where it deviates from the
> official virtio-pci spec slightly: It puts a new "apple type"
> field at a static offset in config space and introduces a new discard
> command.
>
> This patch
On 6/19/23 16:02, Richard Henderson wrote:
One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all. This leads to
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
for Apple M1 cpus.
The orangepi5 board I use didn't have
Richard Henderson writes:
> On 6/12/23 04:50, Richard Henderson wrote:
>> On 6/11/23 02:14, Alex Bennée wrote:
>>>
>>> Richard Henderson writes:
>>>
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn.
Hi Like and zhenyu,
Thank you very much! That will be very helpful.
In order to help the review, I will rebase the patchset on top of the most
recent QEMU.
Thank you very much!
Dongli Zhang
On 6/19/23 01:52, Like Xu wrote:
> I think we've been stuck here too long. Sorry Dongli.
>
> +zhenyu,
Hi,
At the recent QEMU maintainers summit we lamented the fact it was hard
to push forward with our modernising plans as legacy approaches still
get introduced into the code. A lot of knowledge about the "modern"
way of doing things is locked up in senior developers heads. Lets make
a push to
Using QOM correctly is increasingly important to maintaining a modern
code base. However the current documentation skips some important
concepts before launching into a simple example. Lets:
- at least mention properties
- mention TYPE_OBJECT and TYPE_DEVICE
- talk about why we have
On Mon, 19 Jun 2023 at 18:03, Richard Henderson
wrote:
>
> On 6/19/23 17:55, Peter Maydell wrote:
> > On Mon, 19 Jun 2023 at 16:49, Richard Henderson
> > wrote:
> >>
> >> On 6/5/23 08:27, Nicholas Piggin wrote:
> >>> On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote:
>
Fix up the kerneldoc markup and start documenting the various fields
in QDEV related structures. Unfortunately this is not enough include
the documentation because kerneldoc currently chokes on some of our
macros such as:
/**
* @gpios: list of named GPIOs the device provides.
*/
Lets try and keep the overview of the sub-system digestible by
splitting the core API stuff into a separate file. As QOM and QDEV
work together we should also try and enumerate the qdev_ functions.
Currently this is a little broken as kerneldoc doesn't understand our
macros.
Signed-off-by: Alex
Mention that QOM-ified devices already have support for registering
the description.
Signed-off-by: Alex Bennée
---
include/migration/vmstate.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index
Give an overview of the most useful bits of the devel documentation to
read depending on what the developer wants to do.
Signed-off-by: Alex Bennée
---
docs/devel/index-process.rst | 2 ++
docs/devel/index-tcg.rst | 2 ++
docs/devel/index.rst | 24 ++--
From: Shashi Mallela
Create ITS as part of SBSA platform GIC initialization.
GIC ITS information is in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
Signed-off-by: Shashi Mallela
Co-authored-by: Marcin Juszkiewicz
In 2021 Shashi Mallela sent v8 of GIC ITS patchset [1]. At that time it
was decided to do platform versioning first.
1.
https://lore.kernel.org/qemu-devel/20210812165341.40784-8-shashi.mall...@linaro.org/
Now we are going through our list of changes for SBSA Reference Platform
and GIC ITS is
On 6/19/23 18:56, Daniel P. Berrangé wrote:
On Thu, Jun 08, 2023 at 07:23:29PM -0700, Richard Henderson wrote:
Start adding infrastructure for accelerating guest AES.
Begin with a SubBytes + ShiftRows + AddRoundKey primitive.
Signed-off-by: Richard Henderson
---
On 6/19/23 17:55, Peter Maydell wrote:
On Mon, 19 Jun 2023 at 16:49, Richard Henderson
wrote:
On 6/5/23 08:27, Nicholas Piggin wrote:
On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote:
Differently-sized larx/stcx. pairs can succeed if the starting address
matches. Add a size check
On 6/19/23 18:07, Philippe Mathieu-Daudé wrote:
We already have a check for ARMv8-A never setting vfp-d32 true,
... gah! "false".
r~
-20230616' of https://gitlab.com/gaosong/qemu into
staging (2023-06-16 12:30:16 +0200)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230619
for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb:
hw/misc
On Thu, Jun 08, 2023 at 07:23:29PM -0700, Richard Henderson wrote:
> Start adding infrastructure for accelerating guest AES.
> Begin with a SubBytes + ShiftRows + AddRoundKey primitive.
>
> Signed-off-by: Richard Henderson
> ---
> host/include/generic/host/aes-round.h | 16 ++
>
On Thu, Jun 08, 2023 at 07:23:27PM -0700, Richard Henderson wrote:
> We do not currently have a table in crypto/ for just MixColumns.
> Move both tables for consistency.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> include/crypto/aes.h | 6 ++
>
On 19/6/23 16:02, Richard Henderson wrote:
One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all. This leads to
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
for Apple M1 cpus.
We already have a check for ARMv8-A never
No need to have the v8m_stackcheck() helper in the generic
op_helper.c, move it with the rest of the M-profile helpers.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/m_helper.c | 16
target/arm/tcg/op_helper.c | 16
2 files changed, 16
Instead of including helper-m.h.inc via helper.h which is
included by all TCG files, restrict it to the few files
that require it.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 2 --
target/arm/tcg/m_helper.c | 4
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 7d57a71b67..13d59d8417 100644
---
helper.h is used by all units, but not all require the
M-profile definitions. Move them to a new header; the next
commit will remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 17 ++---
target/arm/tcg/helper-m.h.inc | 23
When a device is plugged into a PCIE root port, it can only be plugged into slot
0. Hotplugging a device into a slot other than slot 0 is invalid and should be
prevented. This change ensures that we throw an error if the user tries to plug
a device into a pcie root port on any slot other than slot
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented as the Coding Style:
If you do use template header
[...]
Sorry for the late reply!
Still trying to make up my mind what the right way forward with this is.
This usage is still problematic I suspect (well, and a layer violation
regarding the machine). The machine hotplug handler is supposed to call the
pre_plug/plug/unplug hooks as response
Instead of including helper-a64.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 4
target/arm/tcg/helper-a64.c| 4
target/arm/tcg/sve_helper.c| 5
Instead of including helper-gvec.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/translate-a64.c | 4
target/arm/tcg/translate-gvec.c | 6
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/debug_helper.c | 6 +-
target/arm/helper.c | 6 +-
target/arm/tcg/helper-a64.c | 5 -
target/arm/tcg/hflags.c | 5 -
target/arm/tcg/m_helper.c | 5 -
Instead of including helper-sme.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sme_helper.c| 5 -
target/arm/tcg/translate-a64.c | 4
Instead of including helper-mve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 2 --
target/arm/tcg/mve_helper.c| 5 -
target/arm/tcg/translate-mve.c | 6
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented as the Coding Style:
If you do use template header
helper.h is used by all units, but not all require the generic
vector definitions. Move them to a new header; the next commit
will remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 380 +--
helper.h is used by all units, but not all require the crypto
definitions. Move them to a new header; the next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 37 ++
helper.h is used by all units, but not all require the
SVE2 definitions. We already have helper-sve.h.inc for
SVE* definitions, move them there. The next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/helper.h
We want to extract gvec helpers to a new translate-gvec.c
file. Some helpers will still be accessed out of it, from
the current translate.c. Expose their prototype.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 5 +
target/arm/tcg/translate.c | 8
2 files
Extract 1600 lines from the big enough translate.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-gvec.c | 1644 +++
target/arm/tcg/translate.c | 1630 --
target/arm/tcg/meson.build |1 +
3 files changed,
helper.h is used by all units, but not all require the crypto
definitions. Move them to a new header, which we only include
where necessary, removing the need for "exec/helper-proto.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/helper-a64.h.inc | 16
helper.h is used by all units, but not all require the crypto
definitions. Move them to a new header, which we only include
where necessary, removing the need for "exec/helper-proto.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/helper-a64.h.inc | 12
Instead of including helper-crypto.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 2 --
target/arm/tcg/crypto_helper.c | 7 ++-
target/arm/tcg/translate-a64.c
Instead of including helper-sve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sve_helper.c| 4
target/arm/tcg/translate-sme.c | 4
On Mon, 19 Jun 2023 at 16:49, Richard Henderson
wrote:
>
> On 6/5/23 08:27, Nicholas Piggin wrote:
> > On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote:
> >> Differently-sized larx/stcx. pairs can succeed if the starting address
> >> matches. Add a size check to require stcx. exactly
Instead of including helper-neon.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/neon_helper.c| 5 -
target/arm/tcg/translate-a64.c | 4
helper.h is used by all units, but not all require the NEON
definitions. Move them to a new header; the next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/helper.h | 207
On 6/5/23 08:27, Nicholas Piggin wrote:
On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote:
Differently-sized larx/stcx. pairs can succeed if the starting address
matches. Add a size check to require stcx. exactly match the larx that
established the reservation.
Hmm, question:
Instead of including helper-vfp.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/mve_helper.c | 4
target/arm/tcg/sve_helper.c |
Move various NEON helpers to the well named neon_helper.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/helper-a64.c | 80 --
target/arm/tcg/neon_helper.c | 106 +++
target/arm/tcg/op_helper.c | 22
3 files
helper.h is used by all units, but not all require the
VFP definitions. Move them (along with definitions in
helper-a64.h.inc) to a new header; the next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 167
Instead of including helper-iwmmxt.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/iwmmxt_helper.c| 5 -
Keep the VFP helpers in the same file, guarding them with #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/helper-a64.c | 87 --
target/arm/vfp_helper.c | 93 -
2 files changed, 92 insertions(+), 88
Extract 1300 lines from the big enough translate.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-iwmmxt.c | 1325 +
target/arm/tcg/translate.c| 1312
target/arm/tcg/meson.build
In order to restrict lookup_cp_reg() and set_rmode() helpers
to VFP translation, un-inline gen_lookup_cp_reg and gen_set /
gen_restore_rmode.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 22 +++---
target/arm/tcg/translate-vfp.c | 21
Expose a few methods and variables before extracting iwmmxt
code from translate.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate.h | 6 ++
target/arm/tcg/translate.c | 8
2 files changed, 10 insertions(+), 4 deletions(-)
diff
In order to be able to move the iwmmxt-related code,
fix its style to avoid:
ERROR: braces {} are necessary for all arms of this statement
ERROR: space prohibited before that '++' (ctx:WxB)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate.c
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented as the Coding Style:
If you do use template header
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/helper.h| 96 +--
target/arm/tcg/helper-iwmmxt.h.inc | 103 +
2 files changed, 104 insertions(+), 95 deletions(-)
create mode 100644
CONFIG_TCG is always defined within target/arm/tcg/.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/tcg/cpu32.c| 4 +---
target/arm/tcg/m_helper.c | 6 --
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/arm/tcg/cpu32.c
Since v2:
- Addressed rth's review comments (unnecessary helper-gen)
- Added R-b
- Extracted crypto, pauth, mte, gvec
Possible follow-up:
- merge gvec/vfp
- rename neon -> advsimd
- rename historical op_helper -> misc_helper
Since v1:
- Addressed rth's review comments (unnecessary helper-gen)
-
On Thu, Jun 08, 2023 at 07:23:28PM -0700, Richard Henderson wrote:
> These symbols will avoid the indirection through memory
> when fully unrolling some new primitives.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> crypto/aes.c | 50
On 5/11/23 13:02, Richard Henderson wrote:
On 5/11/23 09:40, Mark Cave-Ayland wrote:
Obviously nothing notionally against this patch, however if you could give me a few days
to run my OpenBIOS SPARC32/SPARC64 boot tests against git master with this patch applied
to double-check there are no
On 6/12/23 04:50, Richard Henderson wrote:
On 6/11/23 02:14, Alex Bennée wrote:
Richard Henderson writes:
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn.
During the tests/tcg/multiarch/memory test, this logging is
> On Jun 19, 2023, at 18:28, Peter Maydell wrote:
>
> On Wed, 7 Jun 2023 at 08:25, Chen Baozi wrote:
>>
>>
>>> On Jun 7, 2023, at 10:33, Yuquan Wang wrote:
>>>
>>> The current sbsa-ref cannot use EHCI controller which is only
>>> able to do 32-bit DMA, since sbsa-ref doesn't have RAM
Stefan Hajnoczi 于2023年6月19日周一 22:42写道：
>
> On Mon, Jun 19, 2023 at 06:32:52PM +0800, Sam Li wrote:
> > Stefan Hajnoczi 于2023年6月19日周一 18:10写道：
> > > On Mon, Jun 05, 2023 at 06:41:06PM +0800, Sam Li wrote:
> > > > diff --git a/block/qcow2.h b/block/qcow2.h
> > > > index 4f67eb912a..fe18dc4d97
On Mon, Jun 19, 2023 at 08:34:04AM -0400, Shaoqin Huang wrote:
> Simply fix the #vcpus_count to @vcpus_count in CPUArchId comments. Whlie
> at it, reorder the parameters in comments to match the sequence of
> parameters which defined in the CPUArchId.
>
> Reviewed-by: Igor Mammedov
>
On Mon, Jun 19, 2023 at 08:16:27PM +0900, Jeuk Kim wrote:
> On Fri, Jun 19, 2023, Stefan Hajnoczi wrote:
> >On Fri, Jun 16, 2023 at 03:58:27PM +0900, Jeuk Kim wrote:
> >> This commit adds support for ufs logical unit.
> >> The LU handles processing for the SCSI command,
> >> unit descriptor query
On 6/19/23 12:37, Philippe Mathieu-Daudé wrote:
On 9/6/23 04:23, Richard Henderson wrote:
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.
This is rather confusing.
Signed-off-by: Richard Henderson
---
On 6/19/23 16:23, Richard Henderson wrote:
v1:
https://lore.kernel.org/qemu-devel/20210316220735.2048137-1-richard.hender...@linaro.org/
v2:
https://lore.kernel.org/qemu-devel/20230306015710.1868853-1-richard.hender...@linaro.org/
Changes for v3:
* Update for tcg-built-once.
* Require
On Mon, Jun 19, 2023 at 06:32:52PM +0800, Sam Li wrote:
> Stefan Hajnoczi 于2023年6月19日周一 18:10写道：
> > On Mon, Jun 05, 2023 at 06:41:06PM +0800, Sam Li wrote:
> > > diff --git a/block/qcow2.h b/block/qcow2.h
> > > index 4f67eb912a..fe18dc4d97 100644
> > > --- a/block/qcow2.h
> > > +++
On Mon, Jun 05, 2023 at 06:41:08PM +0800, Sam Li wrote:
> The zoned format feature can be tested by:
> $ tests/qemu-iotests/check zoned-qcow2
>
> Signed-off-by: Sam Li
> ---
> tests/qemu-iotests/tests/zoned-qcow2 | 110 +++
> tests/qemu-iotests/tests/zoned-qcow2.out |
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