Hi All,
This patch adds support for Samsung Flex-OneNAND devices.
Flex-OneNAND combines SLC and MLC technologies into a single
device. SLC area provides increased reliability and speed, suitable
for storing code and data, such as bootloader, kernel
and root file system. MLC area provides high
Hello.
I have a few questions on arm926 initialization code, located in
${U_BOOT}/cpu/arm926ejs/start.S:
1) what is the point of deliberately setting up SVC mode, as it's
already in this mode right upon the reset?
2) I can't quite understand what 'CONFIG_USE_IRQ' is used for. It is
defined on
hi every one.
i am working in a project that use the u-boot as boot loader, i do have two
kernel images in the board i am using and i need the u-boot to try loading the
first image, but in case of failure, i want the u-boot to go to the address of
the second image. how can i do that?.
thanks
Hello Wolfgang,
I get these messages also, and I did not considered that to be a
problem, because everything works...
Oh, but this *is* a problem. It is not the normal output of that
command.
Yeah, I agree, it was a problem, but this is what I meant: During
debugging it was not related to
Hi Wolfgang,
On Sunday 21 September 2008, Wolfgang Denk wrote:
AMCC wants to ship the new 600MHz boards. This version at least works
compared to the current version which turns those boards into bricks,
since it doesn't bootup into the U-Boot prompt. So it definitely is an
improvement.
Hi,
I have a few questions on arm926 initialization code, located in
${U_BOOT}/cpu/arm926ejs/start.S:
1) what is the point of deliberately setting up SVC mode, as it's
already in this mode right upon the reset?
What if the target board has a custom bootmonitor you use U-Boot as
secondary
Stefan Roese sr at denx.de writes:
On Friday 19 September 2008, Michael Lawnick wrote:
BTW: Which NOR FLASH driver are you using? The common CFI driver? It has
no real connection to the MTD layer which is needed for the UBI port from
Kyungmin. Did you think about this?
We are
I seem to be getting into a habit of (partially) answering my own
questions, but I figure these self answered questions may help
someone in the future...
Firstly, the i386 port definitely does not relocate - Two sources of
proof -1) /cpu/i386/start.S is where bss and data get initialised in
RAM
Hello Stelian,
As promised, here is the first patch to test.
I looked at your logging output, and noticed that the device you mailed me the
logging from contained an interrupt endpoint (3 endpoints).
My USB sticks do not have such an endpoint, so that was the only difference
in the lsusb
On Mon, 2008-09-22 at 14:59 +0200, Stefan Roese wrote:
This commit:
78d78236896d62bb8ca7302af38d8f1493eb2651
ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.
Hi all,
I've changed upm table for some tests with my NAND flash.
In the normal table we have:
Offset Transaction
-- ---
0 read data
8 write command
16write address
24write data
...
But now this offsets changed, write command and write
Added the ability for C code to invalidate the i/d-cache's and
to flush the d-cache. This allows us to more efficient change mappings
from cache-able to cache-inhibited.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
cpu/mpc85xx/start.S | 49
Changing the flash from cacheable to cache-inhibited was taking a significant
amount of time due to the fact that we were iterating over the full 256M of
flash. Instead we can just flush the L1 d-cache and invalidate the i-cache.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Dear Anatolij Gustschin,
In message [EMAIL PROTECTED] you wrote:
Commit be0bd8234b9777ecd63c4c686f72af070d886517
changed SPD EEPROM address to 0x51 and DDR SDRAM
detection stopped working. Change this address
back to 0x50.
Signed-off-by: Anatolij Gustschin [EMAIL PROTECTED]
---
Dear Anatolij Gustschin,
In message [EMAIL PROTECTED] you wrote:
Running mtest command on socrates without specifying
an address range crashes the board. This patch changes
default mtest address range to prevent this behavior.
Signed-off-by: Anatolij Gustschin [EMAIL PROTECTED]
---
Dear Laurent Pinchart,
In message [EMAIL PROTECTED] you wrote:
Signed-off-by: Laurent Pinchart [EMAIL PROTECTED]
---
include/spartan3.h |9 -
1 files changed, 0 insertions(+), 9 deletions(-)
Applied (after fixing a whitespace problem that cause the first hunk
to fail). Thanks.
Dear Laurent Pinchart,
In message [EMAIL PROTECTED] you wrote:
A few Spartan-3 definitions erroneously use Spartan-3E size constants. This
patch fixes them.
Signed-off-by: Laurent Pinchart [EMAIL PROTECTED]
---
include/spartan3.h |6 +++---
1 files changed, 3 insertions(+), 3
Dear Stefan, Kim, Andy, Jon Kumar,
in message [EMAIL PROTECTED]
Nobuhiro Iwamatsu wrote:
I did a simple check.
Only powerpc and i386 and sh seem to use PCI.
If powerpc does not have a problem, would you commit it?
Do I have your go (or at least no veto) to apply this patch?
Best
Dear Gary Jennejohn,
In message [EMAIL PROTECTED] you wrote:
Without this change DPRAM can be exhausted when CFG_ALLOC_DPRAM is
defined, which eventually leads to a machine check. This change
assures that DPRAM is allocated only once in that case.
Signed-off-by: Gary Jennejohn [EMAIL
Dear Graeme Russ,
In message [EMAIL PROTECTED] you wrote:
Several minor corrections to allow clean builds of new i386 and sc520
based boards based on 2008.10
Soory, but some parts of this cannot work:
--- a/examples/82559_eeprom.c
+++ b/examples/82559_eeprom.c
@@ -19,7 +19,6 @@
*/
Dear Graeme Russ,
In message [EMAIL PROTECTED] you wrote:
This patch eliminates an apparent conflict in the definition of
show_boot_progress (defined in both assembler and in C) which
the linker was not picking up but was causing a reset.
Why do we need two implementations of the same
On Mon, Sep 22, 2008 at 3:11 PM, Wolfgang Denk [EMAIL PROTECTED] wrote:
Dear Stefan, Kim, Andy, Jon Kumar,
in message [EMAIL PROTECTED]
Nobuhiro Iwamatsu wrote:
I did a simple check.
Only powerpc and i386 and sh seem to use PCI.
If powerpc does not have a problem, would you commit it?
Dear Bartek,
In message [EMAIL PROTECTED] you wrote:
Are seconds an appropriate scale factor for the timeout?
...
The patch didn't introduce changes in this regard -- TFTP timeouts were
defined in seconds originally. The patch makes the timeout behavior
configurable, instead of being
Le lundi 22 septembre 2008 à 14:42 +0200, Remy Bohmer a écrit :
pièce jointe document texte brut (increase-usb-control-timeout.patch)
Hello Stelian,
As promised, here is the first patch to test.
Unfortunately it doesn't seem to make much difference, see the log
below. I've enabled USB_DEBUG
Dear Kumar Gala,
In message [EMAIL PROTECTED] you wrote:
+ /* start */
+ if (argv[1][0] == 's') {
I think just matching on the first letter is to restrictive; we'll end
up with artificical command names that nobody can remember.
I'm happy to move to using strncmp, but I agree
Dear Kumar Gala,
In message [EMAIL PROTECTED] you wrote:
+ if (!images.valid) {
+ printf(Need to call %s start first\n, argv[0]);
+ return 1;
+ }
We should probably set up a small state machine.
A small state machine for what?
Well, we have states - here you
Dear Remy Bohmer,
In message [EMAIL PROTECTED] you wrote:
Add all missing types to dev_print() in part.c
Signed-off-by: Remy Bohmer [EMAIL PROTECTED]
---
disk/part.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX
Dear nile smile,
In message [EMAIL PROTECTED] you wrote:
i am working in a project that use the u-boot as boot loader, i do have two
kernel images in the board i am using and i need the u-boot to try loading
the first image, but in case of failure, i want the u-boot to go to the
address
Dear Stefan Roese,
In message [EMAIL PROTECTED] you wrote:
Depending on the configuration jumper SATA SELECT, U-Boot disabled
either one PCIe node or the SATA node in the device tree blob. This
patch removes the unnecessary and even confusing warning, when the node
is not found at all.
On Thu, 11 Sep 2008 21:35:36 +0400
Anton Vorontsov [EMAIL PROTECTED] wrote:
The spd_dram code shifts the base address, then masks 20 bits, but
forgets to shift the base address back. Fix this by just masking the
base address correctly.
Found this bug while trying to relocate a DDR memory at
On Sep 22, 2008, at 4:09 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message CF82B92D-9821-495A-
[EMAIL PROTECTED] you wrote:
+ if (!images.valid) {
+ printf(Need to call %s start first\n, argv[0]);
+ return 1;
+ }
We should probably set up a small state machine.
Dear Kumar,
in message [EMAIL PROTECTED] you wrote:
Well, we have states - here you code that a certain operation is not
allowed unless something else has been done before. SImilar
dependencies may follow - after uncompressing and loading the kernel
image it might for
On Mon, Sep 22, 2008 at 3:33 PM, Andrew Dyer [EMAIL PROTECTED] wrote:
On Mon, Sep 22, 2008 at 3:11 PM, Wolfgang Denk [EMAIL PROTECTED] wrote:
Dear Stefan, Kim, Andy, Jon Kumar,
in message [EMAIL PROTECTED]
Nobuhiro Iwamatsu wrote:
I did a simple check.
Only powerpc and i386 and sh seem
-Original Message-
From: Jens Gehrlein [mailto:[EMAIL PROTECTED]
Sent: Friday, September 19, 2008 6:05 PM
To: Jin Zhengxiong-R64188; Wood Scott-B07421
Cc: u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
Hi Jason,
-Original
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
include/configs/MPC8536DS.h |2 ++
include/configs/MPC8540ADS.h |2 ++
include/configs/MPC8541CDS.h |2 ++
include/configs/MPC8544DS.h |2 ++
include/configs/MPC8548CDS.h |2 ++
include/configs/MPC8555CDS.h |2 ++
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