Hi,
I have problem in accessing registers of I2C .
I am calling my application from u-boot.
In my application i can access registers of I2C1 but can't access registers
of I2C2.
Is there any thing done in u-boot for initializing I2Ci ; i=1,2,3 for
accessing registers?
--
View this message in
On 07/03/2013 20:19, Stephen Warren wrote:
On 03/07/2013 10:24 AM, Stefano Babic wrote:
On 26/02/2013 23:28, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and
Dear Simon Glass,
In message 1362715633-20556-8-git-send-email-...@chromium.org you wrote:
We are introducing a new unified board setup and we want this to
be the default. So we need to opt all architectures out first.
...
+- CONFIG_SYS_LEGACY_BOARD
+ This option should not be defined by
Hi Andreas,
On 3/8/2013 15:32, Andreas Bießmann wrote:
[snip]
+void at91_periph_clk_enable(int id)
+{
+struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
The write protect is meant to be right here?
I am sorry, I don't get the right means.
Well, this seems to be the first SoC
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for
u-boot should be 8 character tabs! So this issue should be amended.
2. Add a NOTE for the ENV parameters of the Slave.
Signed-off-by: Liu Gang
Change the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER to
CONFIG_SRIO_PCIE_BOOT_MASTER, remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by:
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the
Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc2000ull
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb000
#define
T4 can support the feature of Boot from SRIO/PCIE, and the macro
CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from
fre 2013-03-08 klockan 10:46 +1300 skrev Charles Manning:
I have had to deal with this a bit so I'll give my 2c.
Under the GPL2, the company only has to provide source, or make an
offer to do so, to customers buying the product containing the GPL
code.
If you go the written offer path then
Hi Friends,
I have successfully run u-boot our my custom board but I can't run kernel.
Problem is that I have saved uImage.bin at NOR location 0x80 and load into
DRAM:0x4100. Here u-boot can get kernel info and print into UART consol but
after loading uncompressed image from 0x4100
On 08/03/13 09:56, Ramesh K Khokhani wrote:
Hi Friends,
I have successfully run u-boot our my custom board but I can't run kernel.
Problem is that I have saved uImage.bin at NOR location 0x80 and load
into DRAM:0x4100. Here u-boot can get kernel info and print into UART
consol but
Hi Simon,
Hi Akshay,
On Thu, Mar 7, 2013 at 6:09 AM, Akshay Saraswat aksha...@samsung.com wrote:
This patch adds fdt nodes for peripherals which require
pin muxing and configuration. Device tree bindings for pinctrl
are kept same as required for Linux. Existing pinmux code
modified to
Dear Wolfgang Denk,
On Friday, March 8, 2013 6:25:19 AM, Wolfgang Denk wrote:
Dear Marek Vasut,
In message 201303080429.00780.ma...@denx.de you wrote:
+ # ... and from configs defined from other configs
+ s/=\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)/=$(\1)/;
Should we
Hi simon,
+ Albert, Tom who might know about this
Hi Akshay,
On Wed, Mar 6, 2013 at 7:36 AM, Akshay Saraswat aksha...@samsung.com wrote:
Hi Simon,
Hi Akshay,
On Tue, Mar 5, 2013 at 2:53 AM, Akshay Saraswat aksha...@samsung.com wrote:
This patch subtracts a part of clock init from spl
and
Hi Marek,
On Friday, March 8, 2013 4:29:00 AM, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Benoît Thébaudeau,
In message
1362596377-5827-15-git-send-email-benoit.thebaud...@advansee.com
you wrote:
+ # ... and from configs defined from other configs
+
2013/3/5 Tom Rini tr...@ti.com:
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On 03/05/2013 01:34 PM, Jagan Teki wrote:
Okay.. what I understand is - Currently, all the flash supported
commands are provided to user as choice. what what i suppose to
implement. He needs to choose the best
Dear Rajeshwari,
On 23/01/13 15:30, Rajeshwari Shinde wrote:
This patch set adds driver for Gigabyte device GD25LQ and GD25Q64B
required for Snow board and enables same in config file.
Based on following patches submitted by Simon Glass:
sf: Add spi_flash_alloc() to create a new SPI flash
On 15/02/13 14:46, Rajeshwari Shinde wrote:
Driver for MAX98095 is added and support for same is incorporated in
sound driver and Snow Board.
This patchset is based on top of
EXYNOS5: SNOW: Add initial dts and config file
Changes in V2:
- Corrected multi-line comment style
Changes
On Thu, Mar 7, 2013 at 6:28 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
Introduce 'mx28evk_nand' target for saving environment variables into NAND.
The mx28evk board does not come with a NAND flash populated from the
factory. It comes with an empty slot (U23), which allows the
Dear Wolfgang Denk,
Dear Marek Vasut,
In message 201303080429.00780.ma...@denx.de you wrote:
+ # ... and from configs defined from other configs
+ s/=\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)/=$(\1)/;
Should we not remove the lower case letters here? Such are not
Dear Benoît Thébaudeau,
Hi Marek,
On Friday, March 8, 2013 4:29:00 AM, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Benoît Thébaudeau,
In message
1362596377-5827-15-git-send-email-benoit.thebaud...@advansee.com
you wrote:
+ # ... and from configs defined from
Dear Marek,
In message 201303081508.49239.ma...@denx.de you wrote:
Should we not remove the lower case letters here? Such are not
supposed to be used in macro names.
btw. CONFIG_[[:alnum:]_]\+ is shorter ;-)
...and has the same issue of including the unwanted lower case
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On 03/08/2013 09:28 AM, Wolfgang Denk wrote:
Dear Marek,
In message 201303081508.49239.ma...@denx.de you wrote:
Should we not remove the lower case letters here? Such are
not supposed to be used in macro names.
btw. CONFIG_[[:alnum:]_]\+
From: Fabio Estevam fabio.este...@freescale.com
When loading a Freescale 2.6.35 on a mx28evk the following issue is seen:
sgtl5000_hw_read: read reg error : Reg 0x00
Device with ID register 0 is not a SGTL5000
Disabling CONFIG_CMD_I2C makes the sgtl5000 probe to succeed.
Mainline kernel does
On Fri, Mar 8, 2013 at 11:40 AM, Tom Rini tr...@ti.com wrote:
I think the giant list from Benoit got lost. It's a HUGE thing to
change. I think we should just accept that config variables are mixed
case, or at least not block this patch on a very large unrelated fixup.
Agreed. Benoit's
On Thu, Mar 07, 2013 at 09:25:44AM -0500, Tom Rini wrote:
When working on RAW partitions, it's possible that the whole area
is larger than DDR. So what we need to do is make sure that the length
we are given is aligned with the LBA block size, then pass that length
in as our count of LBA
Dear Tom Rini,
In message 5139f87a.7000...@ti.com you wrote:
What about the CONFIG_8xx_* variables then ? :)
Argh... well, actually these should be fixed.
I think the giant list from Benoit got lost. It's a HUGE thing to
change. I think we should just accept that config variables
Hi Tom,
When working on RAW partitions, it's possible that the whole area
is larger than DDR. So what we need to do is make sure that the
length we are given is aligned with the LBA block size, then pass
that length in as our count of LBA blocks to operate on. In doing
this, we no longer
This patch adds the fast booting LWMON5 derivat lcd4_lwmon5.
Its a stripped down version of the full blown lwmon5 support,
without ECC, USB, POST and some other stuff. It used the newly
introduced SPL infrastrucure for SPL from NOR flash booting
on the PPC4xx.
By setting the environment variable
Hi Mike,
Sorry, I am partly off-topic.
but since cross compiling and uboot images are still close to uboot,
i'll stay here.
Am 05.03.2013 21:30, schrieb Michael Cashwell:
On Mar 5, 2013, at 2:25 PM, JPT j-...@gmx.net wrote:
*** Next step, booting from disk
...
this works, but the kernel
On Mon, Mar 4, 2013 at 4:39 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 03/04/2013 04:26 PM, Tom Warren wrote:
Thierry,
On Mon, Mar 4, 2013 at 3:41 PM, Thierry Reding
thierry.red...@avionic-design.de wrote:
On Mon, Mar 04, 2013 at 01:46:48PM -0700, Tom Warren wrote:
[...]
I kinda
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On 03/08/2013 11:36 AM, Tom Warren wrote:
On Mon, Mar 4, 2013 at 4:39 PM, Stephen Warren
swar...@wwwdotorg.org wrote:
On 03/04/2013 04:26 PM, Tom Warren wrote:
Thierry,
On Mon, Mar 4, 2013 at 3:41 PM, Thierry Reding
Tom
On Fri, Mar 8, 2013 at 9:44 AM, Tom Rini tr...@ti.com wrote:
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On 03/08/2013 11:36 AM, Tom Warren wrote:
On Mon, Mar 4, 2013 at 4:39 PM, Stephen Warren
swar...@wwwdotorg.org wrote:
On 03/04/2013 04:26 PM, Tom Warren wrote:
Thierry,
On Mon,
On Thu, Feb 28, 2013 at 06:03:47PM -0700, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Various code that is conditional upon HAVE_BLOCK_DEVICE is required by
code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if
CONFIG_CMD_PART is enabled.
Signed-off-by:
On Thu, Feb 28, 2013 at 06:03:46PM -0700, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
This set of ifdefs is used in a number of places. Move its definition
somewhere common so it doesn't have to be repeated.
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Tom
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On 03/08/2013 11:48 AM, Tom Warren wrote:
On Fri, Mar 8, 2013 at 9:44 AM, Tom Rini tr...@ti.com wrote:
On 03/08/2013 11:36 AM, Tom Warren wrote:
On Mon, Mar 4, 2013 at 4:39 PM, Stephen Warren
swar...@wwwdotorg.org wrote:
On 03/04/2013 04:26 PM,
On Fri, Mar 8, 2013 at 9:57 AM, Tom Rini tr...@ti.com wrote:
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On 03/08/2013 11:48 AM, Tom Warren wrote:
On Fri, Mar 8, 2013 at 9:44 AM, Tom Rini tr...@ti.com wrote:
On 03/08/2013 11:36 AM, Tom Warren wrote:
On Mon, Mar 4, 2013 at 4:39 PM, Stephen
Thierry,
On Fri, Mar 8, 2013 at 9:58 AM, Tom Warren twarren.nvi...@gmail.com wrote:
On Fri, Mar 8, 2013 at 9:57 AM, Tom Rini tr...@ti.com wrote:
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On 03/08/2013 11:48 AM, Tom Warren wrote:
On Fri, Mar 8, 2013 at 9:44 AM, Tom Rini tr...@ti.com
Add documentation for the current DFU config options. DFU is a standard
USB device class so more information is available from usb.org
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5:
- New patch to document existing DFU CONFIG options
Changes in v4: None
Changes in v3: None
Changes in
This series does a few things. I've updated Pantelis Antoniou's patch
that allows for transfering of files larger than 4MiB to still allow for
filesystem writes to work. I also document the existing DFU CONFIG
options, and then the new options this series adds. Then we update
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5:
- New patch to re-align defines in dfu.h
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/dfu.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/dfu.h b/include/dfu.h
index
From: Pantelis Antoniou pa...@antoniou-consulting.com
Previously we didn't support upload/download larger than available
memory. This is pretty bad when you have to update your root filesystem
for example.
This patch removes that limitation (and the crashes when you transfered
any file larger
The flag changed from WITH_INLINE_OOB to WITH_YAFFS_OOB by accident in
418396e.
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5: None
Changes in v4:
- Add patch to fix CONFIG_CMD_NAND_YAFFS
Changes in v3: None
Changes in v2: None
common/cmd_nand.c |2 +-
1 file changed, 1
From: Pantelis Antoniou pa...@antoniou-consulting.com
Support for NAND storage devices to work with the DFU framework.
Signed-off-by: Pantelis Antoniou pa...@antoniou-consulting.com
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5:
- Document CONFIG_DFU_NAND in README
Changes in v4: None
From: Pantelis Antoniou pa...@antoniou-consulting.com
drivers/usb/gadget/composite.c requires that this is defined early.
Signed-off-by: Pantelis Antoniou pa...@antoniou-consulting.com
Signed-off-by: Tom Rini tr...@ti.com
Acked-by: Tom Rini tr...@ti.com
---
Changes in v5: None
Changes in v4:
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add CONFIG_CMD_MTDPARTS and relevant information to am335x_evm
include/configs/am335x_evm.h |9 +
1 file changed, 9 insertions(+)
diff --git
From: Pantelis Antoniou pa...@antoniou-consulting.com
- Add CONFIG_DFU_NAND, CONFIG_DFU_MMC
- Set dfu_alt_info_nand, dfu_alt_info_emmc and dfu_alt_info_mmc to show
working examples for those cases.
- Increase CONFIG_SYS_MAXARGS due to hush parsing bugs that would
otherwise disallow 'setenv
From: Steve Kipisz s-kipi...@ti.com
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a
On Mon, Mar 04, 2013 at 04:01:52PM -0800, Simon Glass wrote:
Hi Tom,
Great to see the previous lot made it in. Here is the next x86 series.
The following changes since commit 2536850d7cd90bdb75bf3ff86838f913392b68db:
Prepare v2013.04-rc1 (2013-03-04 16:29:17 -0500)
are available in
Hi Adnan,
On Fri, Mar 8, 2013 at 3:11 AM, Adnan Ali adnan@codethink.co.uk wrote:
Hi
On 08/03/13 05:03, Simon Glass wrote:
+U-Boot et al
Hi,
On Thu, Mar 7, 2013 at 2:35 AM, Adnan Ali adnan@codethink.co.uk
wrote:
Introduces btrfs file-system to read file
from
MPC8xx based systems throw this warning:
cpu.c:81:2: warning: dereferencing type-punned pointer will break
strict-aliasing rules [-Wstrict-aliasing]
Fix it.
Signed-off-by: Wolfgang Denk w...@denx.de
Cc: Andy Fleming aflem...@gmail.com
---
arch/powerpc/cpu/mpc8xx/cpu.c| 4 +++-
The mtest command is of little practical use (if any), and
experience has shown that a large number of board configurations
define useless or even dangerous start and end addresses. If not even
the board maintainers are able to figure out which memory range can be
reliably tested, how can we
On Fri, Mar 08, 2013 at 08:08:24PM +0100, Wolfgang Denk wrote:
The mtest command is of little practical use (if any), and
experience has shown that a large number of board configurations
define useless or even dangerous start and end addresses. If not even
the board maintainers are able to
On Thu, Dec 20, 2012 at 11:51:05AM -, Scott Wood wrote:
SPL doesn't write to the environment. These list entries prevent the
functions from being garbage-collected, even though nothing will look at
the list. This caused several SPL builds (e.g. P2020RDB-PC_NAND) to
break due to size
On 03/08/2013 02:27:48 PM, Tom Rini wrote:
On Thu, Dec 20, 2012 at 11:51:05AM -, Scott Wood wrote:
SPL doesn't write to the environment. These list entries prevent
the
functions from being garbage-collected, even though nothing will
look at
the list. This caused several SPL builds
Dear Ira,
In message 20130308194131.ge23...@ovro.caltech.edu you wrote:
I noticed a couple of small typos, and thought I'd point them out.
Thanks a lot, highly appreciated!
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235
The mtest command is of little practical use (if any), and
experience has shown that a large number of board configurations
define useless or even dangerous start and end addresses. If not even
the board maintainers are able to figure out which memory range can be
reliably tested, how can we
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On 03/08/2013 03:34 PM, Scott Wood wrote:
On 03/08/2013 02:27:48 PM, Tom Rini wrote:
On Thu, Dec 20, 2012 at 11:51:05AM -, Scott Wood wrote:
SPL doesn't write to the environment. These list entries
prevent the functions from being
Dear Scott,
In message 1357696756-31079-1-git-send-email-scottw...@freescale.com you
wrote:
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be
Hi,
In message 1362768757-11425-1-git-send-email...@denx.de you wrote:
MPC8xx based systems throw this warning:
cpu.c:81:2: warning: dereferencing type-punned pointer will break
strict-aliasing rules [-Wstrict-aliasing]
Fix it.
I withdraw this patch in favour of Scott's older and more
Hi Akshay,
On Fri, Mar 8, 2013 at 4:08 AM, Akshay Saraswat aksha...@samsung.comwrote:
Hi Simon,
Hi Akshay,
On Thu, Mar 7, 2013 at 6:09 AM, Akshay Saraswat aksha...@samsung.com
wrote:
This patch adds fdt nodes for peripherals which require
pin muxing and configuration. Device tree
Hi Eric,
On Wed, Jan 30, 2013 at 4:10 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
This patch adds support for the Nitrogen6X board(s) from
Boundary Devices. The boards are based on the i.MX6x
processor family with two major variants:
i.MX6Quad/6Dual
Thanks for the review Fabio,
On 03/08/2013 03:49 PM, Fabio Estevam wrote:
Hi Eric,
On Wed, Jan 30, 2013 at 4:10 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
This patch adds support for the Nitrogen6X board(s) from
Boundary Devices. The boards are based on the i.MX6x
processor family
Hi Wolfgang,
On Fri, Mar 8, 2013 at 12:31 AM, Wolfgang Denk w...@denx.de wrote:
Dear Simon Glass,
In message 1362715633-20556-8-git-send-email-...@chromium.org you wrote:
We are introducing a new unified board setup and we want this to
be the default. So we need to opt all architectures
We are introducing a new unified board setup. Add a check to make sure that
board config files do not define CONFIG_SYS_GENERIC_BOARD unless their
architecture defines __HAVE_ARCH_GENERIC_BOARD
__HAVE_ARCH_GENERIC_BOARD will currently not be the default setting, but
we can switch this later when
This enables generic board support so that ARM boards can define
CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v8:
- Define __HAVE_ARCH_GENERIC_BOARD in ARM's config.mk
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes
This enables generic board support so that ppc boards can define
CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v8:
- Define __HAVE_ARCH_GENERIC_BOARD in PPC's config.mk
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes
This enables generic board support so that x86 boards can define
CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Avoid setting up gd on x86 as it is already done
Changes in v4: None
Changes in
Hi,
On Sat, Mar 2, 2013 at 12:29 AM, Jagan Teki jagannadh.t...@gmail.comwrote:
Hi All,
On Fri, Jan 11, 2013 at 7:46 AM, Simon Glass s...@chromium.org wrote:
Hi Jagannadha,
On Mon, Dec 31, 2012 at 3:13 AM, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
All these patches
On 03/08/2013 03:16:52 PM, Wolfgang Denk wrote:
Dear Scott,
In message
1357696756-31079-1-git-send-email-scottw...@freescale.com you wrote:
C99's strict aliasing rules are insane to use in low-level code
such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
On 03/08/2013 02:59:47 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 03/08/2013 03:34 PM, Scott Wood wrote:
On 03/08/2013 02:27:48 PM, Tom Rini wrote:
On Thu, Dec 20, 2012 at 11:51:05AM -, Scott Wood wrote:
SPL doesn't write to the environment. These list entries
On 03/08/2013 11:37:23 AM, Tom Rini wrote:
We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes
happen)
so that bad blocks can be accounted for. We also make them take an
loff_t limit on how much data can be read
On 03/08/2013 11:37:25 AM, Tom Rini wrote:
From: Pantelis Antoniou pa...@antoniou-consulting.com
Support for NAND storage devices to work with the DFU framework.
Signed-off-by: Pantelis Antoniou pa...@antoniou-consulting.com
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v5:
- Document
Hi,
We need your help on this question, we had the same problem, did you figure
out how the CRC was calculated to the device? This is very important.
Can you help me on this?
--
View this message in context:
Dear Matt,
In message 1345733053-5023-1-git-send-email-m...@genesi-usa.com you wrote:
This gives us a string like 20120822150855 which encodes the build time.
This allows automated version checking and flashing of U-Boot to be performed,
for example, in boot.scr files (or scripting in
Hi guys,
This patch set is floating already for _three_ months.
All comments were addressed, it introduces negative diff stat,
and provides two useful features (also for production automation).
Andy hasn't been responding for quite a while.
I think this patch set is good enough for merging.
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