On Mon, 27 Jan 2003, tsi wrote:
On Sat, 25 Jan 2003, hy0 wrote:
Anyway, back to this patch, why does it have to set MEM_CNTL to 0? If
you simply comment off OUTREG(RADEON_MEM_CNTL, 0) in PreInt10Save,
will the patch still work for your special cases?
It's interesting how these special
On Wed, 29 Jan 2003, Wayne Whitney wrote:
Anyway, back to this patch, why does it have to set MEM_CNTL to 0? If
you simply comment off OUTREG(RADEON_MEM_CNTL, 0) in PreInt10Save,
will the patch still work for your special cases?
It's interesting how these special cases out-number the
On Tue, 28 Jan 2003, hy0 wrote:
It's interesting how these special cases out-number the single more
common case of not having to re-POST the adapter...
I agree the re-POST bug could be quite common for secondary card, since BIOS
code itself may not be well designed/tested to run under such
On Sat, 25 Jan 2003, hy0 wrote:
Thanks for the explanations, now I can see what this is about.
However I still have some concerns about this code. Indeed,
Radeon chips do have 0x1c0 (misnamed MPP_TB_CONFIG) as SEPROM_CNTL
register. Modifying/restoring its SCK_PRESCALE field
On Fri, Jan 24, 2003 at 01:14:18AM -0800, hy0 wrote:
Thanks for the explanations, now I can see what this is about. However I
still have some concerns about this code.
Indeed, Radeon chips do have 0x1c0 (misnamed MPP_TB_CONFIG) as SEPROM_CNTL
register. Modifying/restoring its SCK_PRESCALE
On Fri, 24 Jan 2003, Cedric De Wilde wrote:
On Fri, Jan 24, 2003 at 01:14:18AM -0800, hy0 wrote:
Thanks for the explanations, now I can see what this is about. However I
still have some concerns about this code.
Indeed, Radeon chips do have 0x1c0 (misnamed MPP_TB_CONFIG) as SEPROM_CNTL
On Tue, Jan 21, 2003 at 09:26:36PM -0500, Brian J. Murrell wrote:
On Mon, Jan 20, 2003 at 11:15:17PM +0100, Michel Dänzer wrote:
No, but these warnings are special:
(WW) RADEON(0): Restoring MEM_CNTL (), setting to 29002901
(WW) RADEON(0): Restoring CONFIG_MEMSIZE (0200),
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