----- Original Message ----- From: "Marc Aurele La France" <[EMAIL PROTECTED]> To: "Cedric De Wilde" <[EMAIL PROTECTED]> Cc: "hy0" <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]> Sent: Friday, January 24, 2003 8:31 AM Subject: [XFree86] Re: Have you dropped radeon 7200 support?
> On Fri, 24 Jan 2003, Cedric De Wilde wrote: > > > On Fri, Jan 24, 2003 at 01:14:18AM -0800, hy0 wrote: > > > Thanks for the explanations, now I can see what this is about. However I > > > still have some concerns about this code. > > > Indeed, Radeon chips do have 0x1c0 (misnamed MPP_TB_CONFIG) as SEPROM_CNTL > > > register. Modifying/restoring its SCK_PRESCALE field is unlikely to be the > > > cause of this screen corruption problem. > > > In the current code path, even for a properly POSTed card, MEM_CNTL is set > > > to zero and then restored back. This step may cause some side effect to the > > > memory controller. Properly initializing MEM_CNTL/MEM_SIZE should take > > > several steps (I may miss something): 1. wait for memory control idle > > > (MC_STATUS). 2. configure each channel (MEM_CNTL). 3. reset memory > > > (MEM_SDRAM_MOD_REG). 4. check if each channel works correctly. Simply > > > setting MEM_CNTL to zero and then restoring it back may put memory > > > controller in some bad state. > > To me, this only means more registers need to be saved, and later restored > in a specific order. It should be possible to determine such a sequence > from the BIOS init code. It would be for Mach64 and Rage128 variants, I > know. But I don't happen to have a Radeon BIOS Kit at the moment. Asic initialization involves not only register writes with correct values, but also state waiting, delaying, resetting, etc. Yes, there are initialization tables in Radeon chips embedded in the BIOS images like in Mach64 and R128, but these tables only got standardized in the relative new versions of BIOS. This means using these tables will introduce compatibility problems with old chip/BIOS. While it's possible to resolve these compatibility problems, it will take a lot of work and tests, don't think it's an option for the upcoming v4.3. Anyway, back to this patch, why does it have to set MEM_CNTL to 0? If you simply comment off OUTREG(RADEON_MEM_CNTL, 0) in PreInt10Save, will the patch still work for your special cases? Hui > > > Since Cedric doesn't seem to have this problem > > > with old CVS code, maybe he can try to change the current CVS code from > > > #if 0/* !defined(__alpha__) */ > > > back to > > > #if !defined(__alpha__) > > > See if it can make any difference. At least we can rule out MEM_CNTL related > > > code being the cause. > > > Cool, it work, thanks. There was only a bug in the keyboard mapping but > > it's not related. > > That's fine for the purpose of nailing down the problem. But I don't see > this as a good solution. > > Marc. > > +----------------------------------+-----------------------------------+ > | Marc Aurele La France | work: 1-780-492-9310 | > | Computing and Network Services | fax: 1-780-492-1729 | > | 352 General Services Building | email: [EMAIL PROTECTED] | > | University of Alberta +-----------------------------------+ > | Edmonton, Alberta | | > | T6G 2H1 | Standard disclaimers apply | > | CANADA | | > +----------------------------------+-----------------------------------+ > XFree86 Core Team member. ATI driver and X server internals. > > _______________________________________________ > XFree86 mailing list > [EMAIL PROTECTED] > http://XFree86.Org/mailman/listinfo/xfree86 > _______________________________________________ XFree86 mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/xfree86
