On Mon, Sep 6, 2010 at 10:26 AM, ron minnich <rminn...@gmail.com> wrote: > On Mon, Sep 6, 2010 at 10:05 AM, erik quanstrom <quans...@quanstro.net> wrote: > >> i like the idea. unfortunately, iirc this problem hangs on specifications >> which we don't have. so perhaps it would be better to attack a problem >> were we're not just guessing. > > I've come to the conclusion that where hardware is concerned, I spend > a lot of time guessing ... docs or no .. > ron >
e.g. "If the processor has an L3 cache, then bit 15 of msr C001_102A (ClLinesToNbDis) must be set. This bit needs to eventually be cleared in order for the OS to use the L3 cache. But BIOS must not clear this bit until cacheable accesses to the flash chip are no longer needed. This situation applies only to family 10h processors that have L3 cache." yikes. ron
