From: Taimur Hassan <[email protected]> This version brings along following update: -Revert "Enable HUBP/OPTC/DPP power gating" -Revert "Unify fast update classification paths" -enable ODM 2:1 on single eDP based on pixel clock -Enable IPS on DCN42 -Add additional IPS entry/exit for PSR/Replay -Separate ABM functions into dedicated power_abm.c file -Fix always-true lower-bound assert -Refactor dc_link_aux_transfer_raw -only call pmfw if smu present flags true -Fix multiple compiler warnings -Fix CRC open failure during active rendering -Fix white screen on boot with OLED panel -Fix refresh rate round up case
Acked-by: Tom Chung <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: James Lin <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d87bf8f4f56e..d0b6fad65bc0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.381" +#define DC_VER "3.2.382" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0
