Move struct amdgpu_asic_funcs, polaris kickers, and ASICs macro from the monolithic amdgpu.h file into a new amdgpu_asic.h file.
This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 128 +----------------- drivers/gpu/drm/amd/amdgpu/amdgpu_asic.h | 160 +++++++++++++++++++++++ 2 files changed, 161 insertions(+), 127 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_asic.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d2b84c27a6e7..812bd0f6ff0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -119,6 +119,7 @@ #include "amdgpu_init_level.h" #include "amdgpu_uid.h" #include "amdgpu_video_codecs.h" +#include "amdgpu_asic.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" #endif @@ -415,61 +416,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); */ int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); -/* - * ASIC specific functions. - */ -struct amdgpu_asic_funcs { - bool (*read_disabled_bios)(struct amdgpu_device *adev); - bool (*read_bios_from_rom)(struct amdgpu_device *adev, - u8 *bios, u32 length_bytes); - int (*read_register)(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset, u32 *value); - void (*set_vga_state)(struct amdgpu_device *adev, bool state); - int (*reset)(struct amdgpu_device *adev); - enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); - /* get the reference clock */ - u32 (*get_xclk)(struct amdgpu_device *adev); - /* MM block clocks */ - int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); - int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); - /* static power management */ - int (*get_pcie_lanes)(struct amdgpu_device *adev); - void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); - /* get config memsize register */ - u32 (*get_config_memsize)(struct amdgpu_device *adev); - /* flush hdp write queue */ - void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); - /* invalidate hdp read cache */ - void (*invalidate_hdp)(struct amdgpu_device *adev, - struct amdgpu_ring *ring); - /* check if the asic needs a full reset of if soft reset will work */ - bool (*need_full_reset)(struct amdgpu_device *adev); - /* initialize doorbell layout for specific asic*/ - void (*init_doorbell_index)(struct amdgpu_device *adev); - /* PCIe bandwidth usage */ - void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, - uint64_t *count1); - /* do we need to reset the asic at init time (e.g., kexec) */ - bool (*need_reset_on_init)(struct amdgpu_device *adev); - /* PCIe replay counter */ - uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); - /* device supports BACO */ - int (*supports_baco)(struct amdgpu_device *adev); - /* pre asic_init quirks */ - void (*pre_asic_init)(struct amdgpu_device *adev); - /* enter/exit umd stable pstate */ - int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); - /* query video codecs */ - int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, - const struct amdgpu_video_codecs **codecs); - /* encode "> 32bits" smn addressing */ - u64 (*encode_ext_smn_addressing)(int ext_id); - - ssize_t (*get_reg_state)(struct amdgpu_device *adev, - enum amdgpu_reg_state reg_state, void *buf, - size_t max_size); -}; - /* * IOCTL. */ @@ -510,45 +456,6 @@ struct amd_powerplay { const struct amd_pm_funcs *pp_funcs; }; -/* polaris10 kickers */ -#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ - ((rid == 0xE3) || \ - (rid == 0xE4) || \ - (rid == 0xE5) || \ - (rid == 0xE7) || \ - (rid == 0xEF))) || \ - ((did == 0x6FDF) && \ - ((rid == 0xE7) || \ - (rid == 0xEF) || \ - (rid == 0xFF)))) - -#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ - ((rid == 0xE1) || \ - (rid == 0xF7))) - -/* polaris11 kickers */ -#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ - ((rid == 0xE0) || \ - (rid == 0xE5))) || \ - ((did == 0x67FF) && \ - ((rid == 0xCF) || \ - (rid == 0xEF) || \ - (rid == 0xFF)))) - -#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ - ((rid == 0xE2))) - -/* polaris12 kickers */ -#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ - ((rid == 0xC0) || \ - (rid == 0xC1) || \ - (rid == 0xC3) || \ - (rid == 0xC7))) || \ - ((did == 0x6981) && \ - ((rid == 0x00) || \ - (rid == 0x01) || \ - (rid == 0x10)))) - struct amdgpu_pcie_reset_ctx { bool in_link_reset; bool occurs_dpc; @@ -1082,39 +989,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #include "amdgpu_reset.h" -/* - * ASICs macro. - */ -#define amdgpu_asic_set_vga_state(adev, state) \ - ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) -#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) -#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) -#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) -#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) -#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) -#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) -#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) -#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) -#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) -#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) -#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) -#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) -#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) -#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) -#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) -#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) -#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) -#define amdgpu_asic_supports_baco(adev) \ - ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) -#define amdgpu_asic_pre_asic_init(adev) \ - { \ - if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ - (adev)->asic_funcs->pre_asic_init((adev)); \ - } -#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ - ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) -#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) - #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_asic.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_asic.h new file mode 100644 index 000000000000..413f9a98181f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_asic.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_ASIC_H__ +#define __AMDGPU_ASIC_H__ + +#include <linux/types.h> +#include "amdgpu_reg_state.h" + +struct amdgpu_ring; +struct amdgpu_video_codecs; +struct amdgpu_device; +enum amd_reset_method; + +/* + * ASIC specific functions. + */ +struct amdgpu_asic_funcs { + bool (*read_disabled_bios)(struct amdgpu_device *adev); + bool (*read_bios_from_rom)(struct amdgpu_device *adev, + u8 *bios, u32 length_bytes); + int (*read_register)(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset, u32 *value); + void (*set_vga_state)(struct amdgpu_device *adev, bool state); + int (*reset)(struct amdgpu_device *adev); + enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); + /* get the reference clock */ + u32 (*get_xclk)(struct amdgpu_device *adev); + /* MM block clocks */ + int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); + int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); + /* static power management */ + int (*get_pcie_lanes)(struct amdgpu_device *adev); + void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); + /* get config memsize register */ + u32 (*get_config_memsize)(struct amdgpu_device *adev); + /* flush hdp write queue */ + void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); + /* invalidate hdp read cache */ + void (*invalidate_hdp)(struct amdgpu_device *adev, + struct amdgpu_ring *ring); + /* check if the asic needs a full reset of if soft reset will work */ + bool (*need_full_reset)(struct amdgpu_device *adev); + /* initialize doorbell layout for specific asic*/ + void (*init_doorbell_index)(struct amdgpu_device *adev); + /* PCIe bandwidth usage */ + void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, + uint64_t *count1); + /* do we need to reset the asic at init time (e.g., kexec) */ + bool (*need_reset_on_init)(struct amdgpu_device *adev); + /* PCIe replay counter */ + uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); + /* device supports BACO */ + int (*supports_baco)(struct amdgpu_device *adev); + /* pre asic_init quirks */ + void (*pre_asic_init)(struct amdgpu_device *adev); + /* enter/exit umd stable pstate */ + int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); + /* query video codecs */ + int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs); + /* encode "> 32bits" smn addressing */ + u64 (*encode_ext_smn_addressing)(int ext_id); + + ssize_t (*get_reg_state)(struct amdgpu_device *adev, + enum amdgpu_reg_state reg_state, void *buf, + size_t max_size); +}; + +/* polaris10 kickers */ +#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ + ((rid == 0xE3) || \ + (rid == 0xE4) || \ + (rid == 0xE5) || \ + (rid == 0xE7) || \ + (rid == 0xEF))) || \ + ((did == 0x6FDF) && \ + ((rid == 0xE7) || \ + (rid == 0xEF) || \ + (rid == 0xFF)))) + +#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ + ((rid == 0xE1) || \ + (rid == 0xF7))) + +/* polaris11 kickers */ +#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ + ((rid == 0xE0) || \ + (rid == 0xE5))) || \ + ((did == 0x67FF) && \ + ((rid == 0xCF) || \ + (rid == 0xEF) || \ + (rid == 0xFF)))) + +#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ + ((rid == 0xE2))) + +/* polaris12 kickers */ +#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ + ((rid == 0xC0) || \ + (rid == 0xC1) || \ + (rid == 0xC3) || \ + (rid == 0xC7))) || \ + ((did == 0x6981) && \ + ((rid == 0x00) || \ + (rid == 0x01) || \ + (rid == 0x10)))) + +/* + * ASICs macro. + */ +#define amdgpu_asic_set_vga_state(adev, state) \ + ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) +#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) +#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) +#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) +#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) +#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) +#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) +#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) +#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) +#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) +#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) +#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) +#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) +#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) +#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) +#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) +#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) +#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) +#define amdgpu_asic_supports_baco(adev) \ + ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) +#define amdgpu_asic_pre_asic_init(adev) \ + { \ + if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ + (adev)->asic_funcs->pre_asic_init((adev)); \ + } +#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ + ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) +#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) +#endif -- 2.54.0
