Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the monolithic amdgpu.h into a new amdgpu_mqd.h file.
This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 47 +--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_mqd.h | 75 +++++++++++++++++++++++++ 2 files changed, 76 insertions(+), 46 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mqd.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8fb70731ea58..9473626ea96f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -114,6 +114,7 @@ #include "amdgpu_sa.h" #include "amdgpu_wb.h" #include "amdgpu_ip.h" +#include "amdgpu_mqd.h" #include "amdgpu_uid.h" #include "amdgpu_video_codecs.h" #if defined(CONFIG_DRM_AMD_ISP) @@ -611,44 +612,6 @@ struct amd_powerplay { (rid == 0x01) || \ (rid == 0x10)))) -enum amdgpu_mqd_update_flag { - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ -}; - -struct amdgpu_mqd_prop { - uint64_t mqd_gpu_addr; - uint64_t hqd_base_gpu_addr; - uint64_t rptr_gpu_addr; - uint64_t wptr_gpu_addr; - uint32_t queue_size; - bool use_doorbell; - uint32_t doorbell_index; - uint64_t eop_gpu_addr; - uint32_t hqd_pipe_priority; - uint32_t hqd_queue_priority; - uint32_t mqd_stride_size; - bool allow_tunneling; - bool hqd_active; - uint64_t shadow_addr; - uint64_t gds_bkup_addr; - uint64_t csa_addr; - uint64_t fence_address; - bool tmz_queue; - bool kernel_queue; - uint32_t *cu_mask; - uint32_t cu_mask_count; - uint32_t cu_flags; - bool is_user_cu_masked; -}; - -struct amdgpu_mqd { - unsigned mqd_size; - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, - struct amdgpu_mqd_prop *p); -}; - struct amdgpu_pcie_reset_ctx { bool in_link_reset; bool occurs_dpc; @@ -1035,14 +998,6 @@ struct amdgpu_device { struct amdgpu_kfd_dev kfd; }; -/* - * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) - * as fence address and writes a 32 bit fence value to this address. - * Driver needs to allocate at least 4 DWs extra memory in addition to - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. - */ -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) - static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mqd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mqd.h new file mode 100644 index 000000000000..3806ade5fa71 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mqd.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_MQD_H__ +#define __AMDGPU_MQD_H__ + +#include <linux/types.h> + +struct amdgpu_device; + +enum amdgpu_mqd_update_flag { + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ +}; + +struct amdgpu_mqd_prop { + uint64_t mqd_gpu_addr; + uint64_t hqd_base_gpu_addr; + uint64_t rptr_gpu_addr; + uint64_t wptr_gpu_addr; + uint32_t queue_size; + bool use_doorbell; + uint32_t doorbell_index; + uint64_t eop_gpu_addr; + uint32_t hqd_pipe_priority; + uint32_t hqd_queue_priority; + uint32_t mqd_stride_size; + bool allow_tunneling; + bool hqd_active; + uint64_t shadow_addr; + uint64_t gds_bkup_addr; + uint64_t csa_addr; + uint64_t fence_address; + bool tmz_queue; + bool kernel_queue; + uint32_t *cu_mask; + uint32_t cu_mask_count; + uint32_t cu_flags; + bool is_user_cu_masked; +}; + +struct amdgpu_mqd { + unsigned mqd_size; + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, + struct amdgpu_mqd_prop *p); +}; + +/* + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) + * as fence address and writes a 32 bit fence value to this address. + * Driver needs to allocate at least 4 DWs extra memory in addition to + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) +#endif -- 2.54.0
