From: YiPeng Chai <[email protected]> Add ras ip configuration for A + A.
Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/aca.c | 1 + drivers/gpu/drm/amd/ras/core/aca.h | 2 +- drivers/gpu/drm/amd/ras/core/core.c | 3 +- drivers/gpu/drm/amd/ras/core/ras_gfx.c | 10 ++++- drivers/gpu/drm/amd/ras/core/ras_mp1.c | 11 ++--- drivers/gpu/drm/amd/ras/core/ras_nbio.c | 9 ++-- drivers/gpu/drm/amd/ras/core/ras_umc.c | 1 + .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 41 +++++++++++++++---- 8 files changed, 54 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/core/aca.c b/drivers/gpu/drm/amd/ras/core/aca.c index e6110e02c38e9..898742e578347 100644 --- a/drivers/gpu/drm/amd/ras/core/aca.c +++ b/drivers/gpu/drm/amd/ras/core/aca.c @@ -665,6 +665,7 @@ int ras_aca_hw_init(struct ras_core_context *ras_core) aca_blk->blk_info = ip_func->block_info[i]; } + ras_aca->ip_func = ip_func; ras_aca->ue_updated_mark = 0; return 0; diff --git a/drivers/gpu/drm/amd/ras/core/aca.h b/drivers/gpu/drm/amd/ras/core/aca.h index f42f408f4acfe..d81a9d0ccc6d2 100644 --- a/drivers/gpu/drm/amd/ras/core/aca.h +++ b/drivers/gpu/drm/amd/ras/core/aca.h @@ -28,7 +28,7 @@ #define MAX_SOCKET_NUM_PER_NODE 8 #define MAX_AID_NUM_PER_SOCKET 4 -#define MAX_XCD_NUM_PER_AID 2 +#define MAX_XCD_NUM_PER_AID 4 #define MAX_ACA_RAS_BLOCK 20 #define ACA_ERROR__UE_MASK (0x1 << RAS_ERR_TYPE__UE) diff --git a/drivers/gpu/drm/amd/ras/core/core.c b/drivers/gpu/drm/amd/ras/core/core.c index 9d0453ba21c15..aad95bf3fa180 100644 --- a/drivers/gpu/drm/amd/ras/core/core.c +++ b/drivers/gpu/drm/amd/ras/core/core.c @@ -526,8 +526,7 @@ uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core) ras_core->ras_nbio.ip_func->get_memory_partition_mode) return ras_core->ras_nbio.ip_func->get_memory_partition_mode(ras_core); - RAS_DEV_ERR(ras_core->dev, "Failed to get gpu memory nps mode!\n"); - return 0; + return UMC_MEMORY_PARTITION_MODE_UNKNOWN; } int ras_core_update_ecc_info(struct ras_core_context *ras_core) diff --git a/drivers/gpu/drm/amd/ras/core/ras_gfx.c b/drivers/gpu/drm/amd/ras/core/ras_gfx.c index 2efe18cbbe5b5..e553f1364d6c6 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_gfx.c +++ b/drivers/gpu/drm/amd/ras/core/ras_gfx.c @@ -35,6 +35,9 @@ static const struct ras_gfx_ip_func *ras_gfx_get_ip_funcs( case IP_VERSION(9, 4, 4): case IP_VERSION(9, 5, 0): return &gfx_ras_func_v9_0; + case IP_VERSION(12, 1, 0): + /* TBD */ + break; default: RAS_DEV_ERR(ras_core->dev, "GFX ip version(0x%x) is not supported!\n", ip_version); @@ -49,8 +52,11 @@ int ras_gfx_get_ta_subblock(struct ras_core_context *ras_core, { struct ras_gfx *gfx = &ras_core->ras_gfx; - return gfx->ip_func->get_ta_subblock(ras_core, + if (gfx->ip_func && gfx->ip_func->get_ta_subblock) + return gfx->ip_func->get_ta_subblock(ras_core, error_type, subblock, ta_subblock); + + return -RAS_CORE_NOT_SUPPORTED; } int ras_gfx_hw_init(struct ras_core_context *ras_core) @@ -61,7 +67,7 @@ int ras_gfx_hw_init(struct ras_core_context *ras_core) gfx->ip_func = ras_gfx_get_ip_funcs(ras_core, gfx->gfx_ip_version); - return gfx->ip_func ? RAS_CORE_OK : -EINVAL; + return 0; } int ras_gfx_hw_fini(struct ras_core_context *ras_core) diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.c b/drivers/gpu/drm/amd/ras/core/ras_mp1.c index 97ae049fea496..12c9e20098c43 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_mp1.c +++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.c @@ -34,6 +34,9 @@ static const struct ras_mp1_ip_func *ras_mp1_get_ip_funcs( case IP_VERSION(13, 0, 14): case IP_VERSION(13, 0, 12): return &mp1_ras_func_v13_0; + case IP_VERSION(15, 0, 8): + //TBD for dGPU + break; default: RAS_DEV_ERR(ras_core->dev, "MP1 ip version(0x%x) is not supported!\n", ip_version); @@ -82,11 +85,9 @@ int ras_mp1_hw_init(struct ras_core_context *ras_core) int ret = 0; mp1->mp1_ip_version = ras_core->config->mp1_ip_version; - mp1->sys_func = ras_core->config->mp1_cfg.mp1_sys_fn; - if (!mp1->sys_func) { - RAS_DEV_ERR(ras_core->dev, "RAS mp1 sys function not configured!\n"); - return -EINVAL; - } + + if (ras_core->config->mp1_cfg.mp1_sys_fn) + mp1->sys_func = ras_core->config->mp1_cfg.mp1_sys_fn; mp1->ip_func = ras_mp1_get_ip_funcs(ras_core, mp1->mp1_ip_version); if (!mp1->ip_func) diff --git a/drivers/gpu/drm/amd/ras/core/ras_nbio.c b/drivers/gpu/drm/amd/ras/core/ras_nbio.c index bfddd104d5486..ca543b2f36791 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_nbio.c +++ b/drivers/gpu/drm/amd/ras/core/ras_nbio.c @@ -33,6 +33,9 @@ static const struct ras_nbio_ip_func *ras_nbio_get_ip_funcs( case IP_VERSION(7, 9, 0): case IP_VERSION(7, 9, 1): return &ras_nbio_v7_9; + case IP_VERSION(6, 3, 2): + /* TBD for dGPU */ + break; default: RAS_DEV_ERR(ras_core->dev, "NBIO ip version(0x%x) is not supported!\n", ip_version); @@ -48,14 +51,8 @@ int ras_nbio_hw_init(struct ras_core_context *ras_core) nbio->nbio_ip_version = ras_core->config->nbio_ip_version; nbio->sys_func = ras_core->config->nbio_cfg.nbio_sys_fn; - if (!nbio->sys_func) { - RAS_DEV_ERR(ras_core->dev, "RAS nbio sys function not configured!\n"); - return -EINVAL; - } nbio->ip_func = ras_nbio_get_ip_funcs(ras_core, nbio->nbio_ip_version); - if (!nbio->ip_func) - return -EINVAL; if (nbio->sys_func) { if (nbio->sys_func->set_ras_controller_irq_state) diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.c b/drivers/gpu/drm/amd/ras/core/ras_umc.c index 95a98b411fc79..fcf65dc5f7146 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.c @@ -72,6 +72,7 @@ static const struct ras_umc_ip_func *ras_umc_get_ip_func( switch (ip_version) { case IP_VERSION(12, 0, 0): case IP_VERSION(12, 5, 0): + case IP_VERSION(15, 0, 0): return &ras_umc_func_v12_0; default: RAS_DEV_ERR(ras_core->dev, diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index e2d5f3d968895..1b23ffffc415c 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -34,9 +34,13 @@ #include "amdgpu_ras_nbio_v7_9.h" #include "amdgpu_ras_mce.h" -#define MAX_SOCKET_NUM_PER_NODE 8 -#define MAX_AID_NUM_PER_SOCKET 4 -#define MAX_XCD_NUM_PER_AID 2 +#define MAX_SOCKET_NUM_PER_NODE_GFX9 8 +#define MAX_AID_NUM_PER_SOCKET_GFX9 4 +#define MAX_XCD_NUM_PER_AID_GFX9 2 + +#define MAX_SOCKET_NUM_PER_NODE_GFX12 4 +#define MAX_AID_NUM_PER_SOCKET_GFX12 2 +#define MAX_XCD_NUM_PER_AID_GFX12 4 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ #define TYPICAL_ECC_BAD_PAGE_RATE (100ULL * SZ_1M) @@ -89,9 +93,22 @@ static int amdgpu_ras_mgr_init_aca_config(struct amdgpu_device *adev, { struct ras_aca_config *aca_cfg = &config->aca_cfg; - aca_cfg->socket_num_per_node = MAX_SOCKET_NUM_PER_NODE; - aca_cfg->aid_num_per_socket = MAX_AID_NUM_PER_SOCKET; - aca_cfg->xcd_num_per_aid = MAX_XCD_NUM_PER_AID; + switch (config->gfx_ip_version) { + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 5, 0): + aca_cfg->socket_num_per_node = MAX_SOCKET_NUM_PER_NODE_GFX9; + aca_cfg->aid_num_per_socket = MAX_AID_NUM_PER_SOCKET_GFX9; + aca_cfg->xcd_num_per_aid = MAX_XCD_NUM_PER_AID_GFX9; + break; + case IP_VERSION(12, 1, 0): + aca_cfg->socket_num_per_node = MAX_SOCKET_NUM_PER_NODE_GFX12; + aca_cfg->aid_num_per_socket = MAX_AID_NUM_PER_SOCKET_GFX12; + aca_cfg->xcd_num_per_aid = MAX_XCD_NUM_PER_AID_GFX12; + break; + default: + return -EINVAL; + } return 0; } @@ -194,6 +211,9 @@ static int amdgpu_ras_mgr_init_mp1_config(struct amdgpu_device *adev, case IP_VERSION(13, 0, 12): mp1_cfg->mp1_sys_fn = &amdgpu_ras_mp1_sys_func_v13_0; break; + case IP_VERSION(15, 0, 8): + //TBD for dGPU + break; default: RAS_DEV_ERR(adev, "The mp1(0x%x) ras config is not right!\n", @@ -216,6 +236,9 @@ static int amdgpu_ras_mgr_init_nbio_config(struct amdgpu_device *adev, case IP_VERSION(7, 9, 1): nbio_cfg->nbio_sys_fn = &amdgpu_ras_nbio_sys_func_v7_9; break; + case IP_VERSION(6, 3, 2): + //TBD for dGPU + break; default: RAS_DEV_ERR(adev, "The nbio(0x%x) ras config is not right!\n", @@ -300,9 +323,11 @@ static struct ras_core_context *amdgpu_ras_mgr_create_ras_core(struct amdgpu_dev init_config.mp1_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); init_config.gfx_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); init_config.nbio_ip_version = amdgpu_ip_version(adev, NBIO_HWIP, 0); - init_config.psp_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); + init_config.psp_ip_version = amdgpu_ip_version(adev, MP0_HWIP, 0); - if (init_config.umc_ip_version == IP_VERSION(12, 0, 0) || + if (init_config.gfx_ip_version == IP_VERSION(12, 1, 0)) + init_config.aca_ip_version = IP_VERSION(5, 0, 0); + else if (init_config.umc_ip_version == IP_VERSION(12, 0, 0) || init_config.umc_ip_version == IP_VERSION(12, 5, 0)) init_config.aca_ip_version = IP_VERSION(1, 0, 0); -- 2.55.0
