From: Xiang Liu <[email protected]> CPU machine-check and platform boot errors require standard processor and Platform Memory section definitions. The AMD crashdump format also uses a 64-byte common header followed by a common error information structure.
Add the required GUIDs, validity fields, processor structures, and AMD crashdump wire layout so rascore can generate each record type. Signed-off-by: Xiang Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/ras_cper.h | 99 +++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/core/ras_cper.h b/drivers/gpu/drm/amd/ras/core/ras_cper.h index f69f4e4de9ec9..58d2955ec08dc 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_cper.h +++ b/drivers/gpu/drm/amd/ras/core/ras_cper.h @@ -38,8 +38,10 @@ struct ras_cper_guid { (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }} #define CPER_HDR__REV_1 (0x100) +#define CPER_HDR__REV_AMD_CPU (0x101) #define CPER_SEC__MINOR_REV_1 (0x01) #define CPER_SEC__MAJOR_REV_22 (0x22) +#define CPER_SEC__REV_AMD_CPU (0x0100) #define CPER_OAM_MAX_COUNT (8) #define CPER_CTX_TYPE__CRASH (1) @@ -68,6 +70,43 @@ struct ras_cper_guid { #define PROC_ERR__SECTION_TYPE \ CPER_GUID__INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \ 0x24, 0x2B, 0x6E, 0x1D) +#define PROC_ERR__MS_CHECK_TYPE \ + CPER_GUID__INIT(0x48AB7F57, 0xDC34, 0x4F6C, 0xA7, 0xD3, 0xB0, 0xB5, \ + 0xB0, 0xA7, 0x43, 0x14) +#define PLATFORM_MEM__SECTION_TYPE \ + CPER_GUID__INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ + 0xED, 0x7C, 0x83, 0xB1) +#define PCIE_ERR__SECTION_TYPE \ + CPER_GUID__INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \ + 0xCB, 0x3C, 0x6F, 0x35) +#define SMN_ERR__SECTION_TYPE \ + CPER_GUID__INIT(0xA2860CC1, 0x8987, 0x4B7C, 0xB8, 0x6A, 0xD5, 0x08, \ + 0xB1, 0x76, 0xBA, 0x70) + +#define CPER_PROC_VALID_APIC_ID BIT_ULL(0) +#define CPER_PROC_ERR_INFO_COUNT(x) (((u64)(x) & 0x3f) << 2) +#define CPER_PROC_CONTEXT_COUNT(x) (((u64)(x) & 0x3f) << 8) +#define CPER_AMD_CONTEXT_COUNT(x) (((u64)(x) & 0x3f) << 8) +#define CPER_AMD_ERR_INFO_COUNT(x) (((u64)(x) & 0x3f) << 2) + +#define CPER_PROC_INFO_VALID_CHECK_INFO BIT_ULL(0) + +#define CPER_MS_CHECK_VALID_ERR_TYPE BIT_ULL(0) +#define CPER_MS_CHECK_VALID_PCC BIT_ULL(1) +#define CPER_MS_CHECK_VALID_UNCORRECTED BIT_ULL(2) +#define CPER_MS_CHECK_VALID_OVERFLOW BIT_ULL(5) +#define CPER_MS_CHECK_ERR_TYPE_INTERNAL (5ULL << 16) +#define CPER_MS_CHECK_PCC BIT_ULL(19) +#define CPER_MS_CHECK_UNCORRECTED BIT_ULL(20) +#define CPER_MS_CHECK_OVERFLOW BIT_ULL(23) + +#define CPER_MCA_STATUS_OVERFLOW BIT_ULL(62) +#define CPER_MCA_STATUS_UNCORRECTED BIT_ULL(61) +#define CPER_MCA_STATUS_PCC BIT_ULL(57) +#define CPER_MCA_STATUS_DEFERRED BIT_ULL(44) + +#define CPER_SMCA_MC0_STATUS_MSR (0xc0002001U) +#define CPER_SMCA_BANK_STRIDE (0x10U) enum ras_cper_type { RAS_CPER_TYPE_RUNTIME, @@ -238,10 +277,10 @@ struct cper_section_runtime { }; struct crashdump_hdr { - uint64_t reserved1; - uint64_t reserved2; + u64 valid_bits; + u32 pcie_device_id; + u32 pldm_bundle; char fw_id[48]; - uint64_t reserved3[8]; }; struct fatal_reg_info { @@ -267,16 +306,56 @@ struct crashdump_boot { uint64_t msg[CPER_OAM_MAX_COUNT]; }; +struct crashdump_error_info { + struct ras_cper_guid error_type; + u64 valid_bits; + u64 check_info; + u8 fru_part_number[16]; + u8 redfish_event_id[16]; +}; + struct cper_section_fatal { - struct crashdump_hdr hdr; - struct crashdump_fatal data; + struct crashdump_hdr hdr; + struct crashdump_error_info error_info; + struct crashdump_fatal data; }; struct cper_section_boot { - struct crashdump_hdr hdr; + struct crashdump_hdr hdr; + struct crashdump_error_info error_info; struct crashdump_boot data; }; +struct cper_processor_section { + u64 valid_bits; + u64 apic_id; + u8 cpuid[48]; +}; + +struct cper_processor_error_info { + struct ras_cper_guid error_type; + u64 valid_bits; + u64 check_info; + u64 target_id; + u64 requester_id; + u64 responder_id; + u64 instruction_pointer; +}; + +struct cper_processor_context { + u16 reg_ctx_type; + u16 reg_arr_size; + u32 msr_addr; + u64 mm_reg_addr; + u64 reg_dump[RAS_CPER_ACA_REG_COUNT]; +}; + +struct cper_section_processor { + struct cper_processor_section processor; + struct cper_processor_error_info error_info; + struct cper_processor_context context; +}; + struct ras_cper_fatal_record { struct cper_section_hdr hdr; struct cper_section_desc descriptor; @@ -288,6 +367,13 @@ struct ras_cper_boot_record { struct cper_section_desc descriptor; struct cper_section_boot boot; }; + +struct ras_cper_processor_record { + struct cper_section_hdr hdr; + struct cper_section_desc descriptor; + struct cper_section_processor processor; +}; + #pragma pack(pop) struct ras_core_context; @@ -334,6 +420,7 @@ struct ras_cper { #define RAS_BOOT_SEC_LEN (sizeof(struct cper_section_boot)) #define RAS_FATAL_SEC_LEN (sizeof(struct cper_section_fatal)) #define RAS_NONSTD_SEC_LEN (sizeof(struct cper_section_runtime)) +#define RAS_PROC_SEC_LEN (sizeof(struct cper_section_processor)) #define RAS_SEC_DESC_OFFSET(idx) (RAS_HDR_LEN + (RAS_SEC_DESC_LEN * idx)) -- 2.55.0
