From: Xiang Liu <[email protected]> Machine-check records may not carry the hardware-maintained UMC error count expected by the normal polling path. As a result, valid deferred, uncorrected, and corrected MCE status values can remain unclassified.
For MCE-originated banks, classify the error directly from the MCA status bits when normal UMC decoding does not produce an error count. Signed-off-by: Xiang Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c b/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c index e35f96c3ac350..fe3942f54afc5 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c @@ -174,6 +174,11 @@ static int aca_parse_umc_bank(struct ras_core_context *ras_core, ext_error_code = ACA_V5_REG_STATUS_ERRORCODEEXT(status); misc0_errcnt = ACA_V5_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); + if (bank->ecc_type == RAS_ERR_TYPE__MCE && + ACA_V5_REG_STATUS_DEFERRED(status)) { + err->de_count = 1; + return 0; + } if (aca_check_umc_de(ras_core, status)) err->de_count = misc0_errcnt ? misc0_errcnt : 1; @@ -182,6 +187,18 @@ static int aca_parse_umc_bank(struct ras_core_context *ras_core, else if (aca_check_umc_ce(ras_core, status)) err->ce_count = ext_error_code ? 1 : misc0_errcnt; + if (bank->ecc_type != RAS_ERR_TYPE__MCE || err->de_count || + err->ue_count || err->ce_count) + return 0; + + if (ACA_V5_REG_STATUS_DEFERRED(status)) + err->de_count = 1; + else if (ACA_V5_REG_STATUS_UC(status) || ACA_V5_REG_STATUS_PCC(status) || + ACA_V5_REG_STATUS_TCC(status)) + err->ue_count = 1; + else if (ACA_V5_REG_STATUS_CECC(status) || ACA_V5_REG_STATUS_UECC(status)) + err->ce_count = 1; + return 0; } -- 2.55.0
