From: Hawking Zhang <[email protected]> mmhub v4_2_0 used adev->aid_mask as the mid_mask when programming MMHUB instances. That assumption is not valid for products with more AIDs than MIDs.
Track discovered MMHUB instances in mmhub.inst_mask and use that mask for mmhub v4_2_0 programming paths. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 3 + drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 94 ++++++++----------- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 22 +++-- drivers/gpu/drm/amd/amdgpu/soc_v1_0.h | 1 + 5 files changed, 70 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 5488715938b02..66315ce79fdcc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1760,6 +1760,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) adev->sdma.sdma_mask = 0; adev->vcn.inst_mask = 0; adev->jpeg.inst_mask = 0; + adev->mmhub.inst_mask = 0; r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); if (r) return r; @@ -1825,6 +1826,16 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) } ip->revision &= ~0xc0; } + + if (le16_to_cpu(ip->hw_id) == MMHUB_HWID) { + if (inst < AMDGPU_MAX_MMHUB_INSTANCES) + adev->mmhub.inst_mask |= BIT(inst); + else + dev_err(adev->dev, "Too many MMHUB instances: %d vs %d\n", + inst + 1, + AMDGPU_MAX_MMHUB_INSTANCES); + } + if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || le16_to_cpu(ip->hw_id) == SDMA1_HWID || le16_to_cpu(ip->hw_id) == SDMA2_HWID || diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index c5120ba51e248..bc25a13180690 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -21,6 +21,8 @@ #ifndef __AMDGPU_MMHUB_H__ #define __AMDGPU_MMHUB_H__ +#define AMDGPU_MAX_MMHUB_INSTANCES 4 + struct amdgpu_mmhub_ras { struct amdgpu_ras_block_object ras_block; }; @@ -53,6 +55,7 @@ struct amdgpu_mmhub { const struct amdgpu_mmhub_funcs *funcs; struct amdgpu_mmhub_ras *ras; struct amdgpu_mmhub_client_ids client_ids; + uint32_t inst_mask; }; static inline void diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index 5a29d38220ca4..8e010296b3c29 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -137,12 +137,12 @@ static u64 mmhub_v4_2_0_get_mc_fb_offset(struct amdgpu_device *adev) static void mmhub_v4_2_0_mid_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base, - uint32_t mid_mask) + uint32_t inst_mask) { struct amdgpu_vmhub *hub; int i; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, @@ -160,16 +160,13 @@ static void mmhub_v4_2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) { - uint32_t mid_mask; - - mid_mask = adev->aid_mask; mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, vmid, page_table_base, - mid_mask); + adev->mmhub.inst_mask); } static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { uint64_t pt_base; int i; @@ -179,9 +176,9 @@ static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, else pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); - mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, 0, pt_base, mid_mask); + mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, 0, pt_base, inst_mask); - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { if (adev->gmc.pdb0_bo) { WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, @@ -215,7 +212,7 @@ static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, } static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { uint64_t value; uint32_t tmp; @@ -229,7 +226,7 @@ static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *ade if (amdgpu_sriov_vf(adev)) return; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { if (adev->gmc.pdb0_bo) { /* Disable agp and system aperture * when vmid0 page table is enabled */ @@ -328,12 +325,12 @@ static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *ade } static void mmhub_v4_2_0_mid_init_tlb_regs(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { uint32_t tmp; int i; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { /* Setup TLB control */ tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMMC_VM_MX_L1_TLB_CNTL); @@ -353,7 +350,7 @@ static void mmhub_v4_2_0_mid_init_tlb_regs(struct amdgpu_device *adev, } static void mmhub_v4_2_0_mid_init_cache_regs(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { uint32_t tmp; int i; @@ -364,7 +361,7 @@ static void mmhub_v4_2_0_mid_init_cache_regs(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) return; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { /* Setup L2 cache */ tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL); tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); @@ -416,12 +413,12 @@ static void mmhub_v4_2_0_mid_init_cache_regs(struct amdgpu_device *adev, } static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { uint32_t tmp; int i; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_CNTL); tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, @@ -439,7 +436,7 @@ static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev, } static void mmhub_v4_2_0_mid_disable_identity_aperture(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { int i; @@ -449,7 +446,7 @@ static void mmhub_v4_2_0_mid_disable_identity_aperture(struct amdgpu_device *ade if (amdgpu_sriov_vf(adev)) return; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 0xFFFFFFFF); @@ -474,13 +471,13 @@ static void mmhub_v4_2_0_mid_disable_identity_aperture(struct amdgpu_device *ade } static void mmhub_v4_2_0_mid_setup_vmid_config(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { struct amdgpu_vmhub *hub; uint32_t tmp; int i, j; - for_each_inst(j, mid_mask) { + for_each_inst(j, inst_mask) { hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; for (i = 0; i <= 14; i++) { tmp = RREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), @@ -530,12 +527,12 @@ static void mmhub_v4_2_0_mid_setup_vmid_config(struct amdgpu_device *adev, } static void mmhub_v4_2_0_mid_program_invalidation(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { struct amdgpu_vmhub *hub; unsigned int i, j; - for_each_inst(j, mid_mask) { + for_each_inst(j, inst_mask) { hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; for (i = 0; i < 18; ++i) { @@ -550,37 +547,34 @@ static void mmhub_v4_2_0_mid_program_invalidation(struct amdgpu_device *adev, } static int mmhub_v4_2_0_mid_gart_enable(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { /* GART Enable. */ - mmhub_v4_2_0_mid_init_gart_aperture_regs(adev, mid_mask); - mmhub_v4_2_0_mid_init_system_aperture_regs(adev, mid_mask); - mmhub_v4_2_0_mid_init_tlb_regs(adev, mid_mask); - mmhub_v4_2_0_mid_init_cache_regs(adev, mid_mask); + mmhub_v4_2_0_mid_init_gart_aperture_regs(adev, inst_mask); + mmhub_v4_2_0_mid_init_system_aperture_regs(adev, inst_mask); + mmhub_v4_2_0_mid_init_tlb_regs(adev, inst_mask); + mmhub_v4_2_0_mid_init_cache_regs(adev, inst_mask); - mmhub_v4_2_0_mid_enable_system_domain(adev, mid_mask); - mmhub_v4_2_0_mid_disable_identity_aperture(adev, mid_mask); - mmhub_v4_2_0_mid_setup_vmid_config(adev, mid_mask); - mmhub_v4_2_0_mid_program_invalidation(adev, mid_mask); + mmhub_v4_2_0_mid_enable_system_domain(adev, inst_mask); + mmhub_v4_2_0_mid_disable_identity_aperture(adev, inst_mask); + mmhub_v4_2_0_mid_setup_vmid_config(adev, inst_mask); + mmhub_v4_2_0_mid_program_invalidation(adev, inst_mask); return 0; } static int mmhub_v4_2_0_gart_enable(struct amdgpu_device *adev) { - uint32_t mid_mask; - - mid_mask = adev->aid_mask; - return mmhub_v4_2_0_mid_gart_enable(adev, mid_mask); + return mmhub_v4_2_0_mid_gart_enable(adev, adev->mmhub.inst_mask); } static void mmhub_v4_2_0_mid_gart_disable(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { struct amdgpu_vmhub *hub; u32 tmp; u32 i, j; - for_each_inst(j, mid_mask) { + for_each_inst(j, inst_mask) { hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; /* Disable all tables */ for (i = 0; i < 16; i++) @@ -608,15 +602,12 @@ static void mmhub_v4_2_0_mid_gart_disable(struct amdgpu_device *adev, static void mmhub_v4_2_0_gart_disable(struct amdgpu_device *adev) { - uint32_t mid_mask; - - mid_mask = adev->aid_mask; - mmhub_v4_2_0_mid_gart_disable(adev, mid_mask); + mmhub_v4_2_0_mid_gart_disable(adev, adev->mmhub.inst_mask); } static void mmhub_v4_2_0_mid_set_fault_enable_default(struct amdgpu_device *adev, - bool value, uint32_t mid_mask) + bool value, uint32_t inst_mask) { u32 tmp; int i; @@ -627,7 +618,7 @@ mmhub_v4_2_0_mid_set_fault_enable_default(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) return; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_PROTECTION_FAULT_CNTL_LO32); tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, @@ -673,10 +664,8 @@ static void mmhub_v4_2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { - uint32_t mid_mask; - - mid_mask = adev->aid_mask; - mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, mid_mask); + mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, + adev->mmhub.inst_mask); } static uint32_t mmhub_v4_2_0_get_invalidate_req(unsigned int vmid, @@ -743,12 +732,12 @@ static const struct amdgpu_vmhub_funcs mmhub_v4_2_0_vmhub_funcs = { }; static void mmhub_v4_2_0_mid_init(struct amdgpu_device *adev, - uint32_t mid_mask) + uint32_t inst_mask) { struct amdgpu_vmhub *hub; int i; - for_each_inst(i, mid_mask) { + for_each_inst(i, inst_mask) { hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; hub->ctx0_ptb_addr_lo32 = @@ -805,10 +794,7 @@ static void mmhub_v4_2_0_mid_init(struct amdgpu_device *adev, static void mmhub_v4_2_0_init(struct amdgpu_device *adev) { - uint32_t mid_mask; - - mid_mask = adev->aid_mask; - mmhub_v4_2_0_mid_init(adev, mid_mask); + mmhub_v4_2_0_mid_init(adev, adev->mmhub.inst_mask); amdgpu_mmhub_init_client_info(&adev->mmhub, mmhub_client_ids_v4_2_0, diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 8a1365ae9db6c..3c1ddbd1b93f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -823,19 +823,27 @@ static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) return ret; } -int soc_v1_0_init_soc_config(struct amdgpu_device *adev) +uint32_t soc_v1_0_get_aid_mask(uint16_t xcc_mask) { - int ret, i; int xcc_inst_per_aid = 4; - uint16_t xcc_mask, sdma_mask = 0; + uint32_t aid_mask = 0; + int i; - xcc_mask = adev->gfx.xcc_mask; - adev->aid_mask = 0; for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { - if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) - adev->aid_mask |= (1 << i); + if (xcc_mask & GENMASK(xcc_inst_per_aid - 1, 0)) + aid_mask |= BIT(i); } + return aid_mask; +} + +int soc_v1_0_init_soc_config(struct amdgpu_device *adev) +{ + int ret, i; + uint16_t sdma_mask = 0; + + adev->aid_mask = soc_v1_0_get_aid_mask(adev->gfx.xcc_mask); + adev->sdma.num_inst_per_xcc = 2; for_each_inst(i, adev->gfx.xcc_mask) sdma_mask |= diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h index 16c220fcc4e92..3cbc20eb16155 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h @@ -30,6 +30,7 @@ void soc_v1_0_grbm_select(struct amdgpu_device *adev, u32 queue, u32 vmid, int xcc_id); int soc_v1_0_init_soc_config(struct amdgpu_device *adev); +uint32_t soc_v1_0_get_aid_mask(uint16_t xcc_mask); bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg); bool soc_v1_0_mid1_reg_range(uint32_t reg); uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg); -- 2.55.0
