Describe the nbio v4_3 doorbell entry ctrl field layout and initialize the CP, IH, SDMA, RLC, and VCN port and register assignments.
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> --- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 77 ++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index a66e3073aed8..6d12324ce663 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -28,6 +28,81 @@ #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" #include <uapi/linux/kfd_ioctl.h> +static const struct amdgpu_nbio_doorbell_layout +nbio_v4_3_doorbell_layout = { + .ctrl = { + .enable = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_ENABLE), + .awid = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_AWID), + .fence_enable = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_FENCE_ENABLE), + .range_offset = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_RANGE_OFFSET), + .range_size = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_RANGE_SIZE), + .disable_64bit = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS), + .deduct_range_offset = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET), + .awaddr_31_28 = REG_FIELD_MASK( + S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE), + }, +}; + +static void nbio_v4_3_init_doorbell_entry_registers( + struct amdgpu_device *adev) +{ + struct amdgpu_nbio_doorbell_entries *entries; + u32 ctrl_base; + + memset(adev->nbio.doorbell_entries, 0, + sizeof(adev->nbio.doorbell_entries)); + adev->nbio.doorbell_layout = &nbio_v4_3_doorbell_layout; + + ctrl_base = SOC15_REG_OFFSET(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL); + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_CP]; + entries->num_entries = 1; + entries->entry[0].port = 0; + entries->entry[0].ctrl_reg = ctrl_base; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_IH]; + entries->num_entries = 1; + entries->entry[0].port = 1; + entries->entry[0].ctrl_reg = ctrl_base + 1; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA]; + entries->num_entries = 1; + entries->entry[0].port = 2; + entries->entry[0].ctrl_reg = ctrl_base + 2; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_RLC]; + entries->num_entries = 1; + entries->entry[0].port = 3; + entries->entry[0].ctrl_reg = ctrl_base + 3; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_VCN]; + entries->num_entries = 2; + entries->entry[0].port = 4; + entries->entry[0].ctrl_reg = ctrl_base + 4; + entries->entry[1].port = 5; + entries->entry[1].ctrl_reg = ctrl_base + 5; +} + static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev) { WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, @@ -337,6 +412,8 @@ const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = { static void nbio_v4_3_init_registers(struct amdgpu_device *adev) { + nbio_v4_3_init_doorbell_entry_registers(adev); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) { uint32_t data; -- 2.17.1
