Build and program doorbell entry control values through the common NBIO helpers while preserving the existing nbio v7_11_4 client routing and field values.
Signed-off-by: Hawking Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c | 307 +++++++++++++--------- 1 file changed, 184 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c index 8bae45c9ddfd..9e60613addc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c @@ -27,6 +27,89 @@ #include "nbif/nbif_4_10_0_sh_mask.h" #include <uapi/linux/kfd_ioctl.h> +static const struct amdgpu_nbio_doorbell_layout +nbio_v7_11_4_doorbell_layout = { + .ctrl = { + .enable = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_ENABLE), + .awid = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_AWID), + .fence_enable = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_FENCE_ENABLE), + .range_offset = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_RANGE_OFFSET), + .range_size = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_RANGE_SIZE), + .disable_64bit = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS), + .deduct_range_offset = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET), + .drop = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_DROP_EN), + .awaddr_31_28 = REG_FIELD_MASK( + GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, + S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE), + }, +}; + +static void nbio_v7_11_4_init_doorbell_entry_registers( + struct amdgpu_device *adev) +{ + struct amdgpu_nbio_doorbell_entries *entries; + u32 ctrl_base; + + memset(adev->nbio.doorbell_entries, 0, + sizeof(adev->nbio.doorbell_entries)); + adev->nbio.doorbell_layout = &nbio_v7_11_4_doorbell_layout; + + ctrl_base = SOC15_REG_OFFSET( + NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL); + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_CP]; + entries->num_entries = 1; + entries->entry[0].port = 0; + entries->entry[0].ctrl_reg = ctrl_base; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_IH]; + entries->num_entries = 1; + entries->entry[0].port = 1; + entries->entry[0].ctrl_reg = ctrl_base + 2; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA]; + entries->num_entries = 1; + entries->entry[0].port = 2; + entries->entry[0].ctrl_reg = ctrl_base + 4; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_RLC]; + entries->num_entries = 1; + entries->entry[0].port = 3; + entries->entry[0].ctrl_reg = ctrl_base + 6; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_VCN]; + entries->num_entries = 1; + entries->entry[0].port = 4; + entries->entry[0].ctrl_reg = ctrl_base + 8; + + entries = &adev->nbio.doorbell_entries[ + AMDGPU_NBIO_DOORBELL_CLIENT_VPE]; + entries->num_entries = 1; + entries->entry[0].port = 5; + entries->entry[0].ctrl_reg = ctrl_base + 10; +} + static void nbio_v7_11_4_remap_hdp_registers(struct amdgpu_device *adev) { WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, @@ -66,81 +149,62 @@ static void nbio_v7_11_4_sdma_doorbell_range(struct amdgpu_device *adev, int doorbell_index, int doorbell_size) { - if (instance == 0) { - u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); - - if (use_doorbell) { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_ENABLE, - 0x1); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_AWID, - 0xe); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_OFFSET, - doorbell_index); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_SIZE, - doorbell_size); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, - 0x3); - } else { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_SIZE, - 0); - } - - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, - doorbell_range); + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awid = 0xe, + .range_offset = doorbell_index, + .range_size = doorbell_size, + .awaddr_31_28 = 0x3, + }; + u32 ctrl; + + if (instance != 0) + return; + + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, + NULL, NULL); + return; } + + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL); } static void nbio_v7_11_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index, int instance) { - u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awid = 0x4, + .range_offset = doorbell_index, + .range_size = 8, + .awaddr_31_28 = 0x4, + }; + u32 ctrl; if (instance) return; - if (use_doorbell) { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_ENABLE, - 0x1); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_AWID, - 0x4); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_OFFSET, - doorbell_index); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_SIZE, - 8); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, - 0x4); - } else { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_SIZE, - 0); + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VCN, 0, + NULL, NULL); + return; } - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, - doorbell_range); + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VCN, 0, &ctrl, NULL); } static void nbio_v7_11_4_vpe_doorbell_range(struct amdgpu_device *adev, @@ -148,46 +212,54 @@ static void nbio_v7_11_4_vpe_doorbell_range(struct amdgpu_device *adev, int doorbell_index, int doorbell_size) { + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awid = 0xf, + .range_offset = doorbell_index, + .range_size = doorbell_size, + .awaddr_31_28 = 0xf, + }; + u32 ctrl; + if (instance) return; - u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); - - if (use_doorbell) { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_ENABLE, - 0x1); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_AWID, - 0xf); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_RANGE_OFFSET, - doorbell_index); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_RANGE_SIZE, - doorbell_size); - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, - 0xf); - } else { - doorbell_range = REG_SET_FIELD(doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, - S2A_DOORBELL_PORT5_RANGE_SIZE, - 0); + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, + NULL, NULL); + return; } - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, &ctrl, NULL); } static void nbio_v7_11_4_gc_doorbell_init(struct amdgpu_device *adev) { - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); + struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awaddr_31_28 = 0x3, + }; + u32 ctrl; + + fields.awid = 0x3; + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL); + + fields.awid = 0x6; + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL); } static void nbio_v7_11_4_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -223,38 +295,25 @@ nbio_v7_11_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, static void nbio_v7_11_4_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { - u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); - - if (use_doorbell) { - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_ENABLE, - 0x1); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_AWID, - 0x0); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_OFFSET, - doorbell_index); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_SIZE, - 2); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, - 0x0); - } else { - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_SIZE, - 0); + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .range_offset = doorbell_index, + .range_size = 2, + }; + u32 ctrl; + + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL); + return; } - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, - ih_doorbell_range); + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL); } static void nbio_v7_11_4_ih_control(struct amdgpu_device *adev) @@ -336,6 +395,8 @@ static void nbio_v7_11_4_init_registers(struct amdgpu_device *adev) { uint32_t data; + nbio_v7_11_4_init_doorbell_entry_registers(adev); + data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); -- 2.17.1
