Build and program the CP, RLC, IH, SDMA, and VCN doorbell entries through the common NBIO helpers while retaining the existing callback interface and v4_3 client routing values.
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> --- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 188 ++++++++++++------------- 1 file changed, 88 insertions(+), 100 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index 6d12324ce663..be98fee6fbf2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -140,87 +140,86 @@ static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan bool use_doorbell, int doorbell_index, int doorbell_size) { - if (instance == 0) { - u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); - - if (use_doorbell) { - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_ENABLE, - 0x1); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_AWID, - 0xe); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_OFFSET, - doorbell_index); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_SIZE, - doorbell_size); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, - 0x3); - } else - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_2_CTRL, - S2A_DOORBELL_PORT2_RANGE_SIZE, - 0); - - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awid = 0xe, + .range_offset = doorbell_index, + .range_size = doorbell_size, + .awaddr_31_28 = 0x3, + }; + u32 ctrl; + + if (instance != 0) + return; + + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, + NULL, NULL); + return; } + + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL); } static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index, int instance) { - u32 doorbell_range; + static const u8 vcn_component[] = { 0x4, 0x7 }; + struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .range_offset = doorbell_index, + .range_size = 8, + }; + u32 ctrl; - if (instance) - doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); - else - doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); - - if (use_doorbell) { - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_ENABLE, - 0x1); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_AWID, - instance ? 0x7 : 0x4); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_OFFSET, - doorbell_index); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_SIZE, - 8); - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, - instance ? 0x7 : 0x4); - } else - doorbell_range = REG_SET_FIELD(doorbell_range, - S2A_DOORBELL_ENTRY_4_CTRL, - S2A_DOORBELL_PORT4_RANGE_SIZE, - 0); - - if (instance) - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); - else - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); + if (WARN_ON_ONCE((unsigned int)instance >= + ARRAY_SIZE(vcn_component))) + return; + + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance, + NULL, NULL); + return; + } + + fields.awid = vcn_component[instance]; + fields.awaddr_31_28 = fields.awid; + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance, &ctrl, NULL); } static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev) { - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); + struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .awaddr_31_28 = 0x3, + }; + u32 ctrl; + + fields.awid = 0x3; + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL); + + fields.awid = 0x6; + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL); } static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -256,36 +255,25 @@ static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *ad static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { - u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); - - if (use_doorbell) { - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_ENABLE, - 0x1); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_AWID, - 0x0); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_OFFSET, - doorbell_index); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_SIZE, - 8); - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, - 0x0); - } else - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, - S2A_DOORBELL_ENTRY_1_CTRL, - S2A_DOORBELL_PORT1_RANGE_SIZE, - 0); - - WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); + const struct amdgpu_nbio_doorbell_fields fields = { + .enable = true, + .range_offset = doorbell_index, + .range_size = 8, + }; + u32 ctrl; + + if (!use_doorbell) { + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL); + return; + } + + if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry( + adev, &fields, &ctrl, NULL))) + return; + + amdgpu_nbio_program_doorbell_entry(adev, + AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL); } static void nbio_v4_3_ih_control(struct amdgpu_device *adev) -- 2.17.1
