From: Tom Chung <[email protected]> Add dcn35_dmub_hw_control_lock() and dcn35_dmub_hw_control_lock_fast(), a SW lock mechanism to prevent racing between driver and FW.
The helpers are not wired into dcn35_funcs/dcn351_funcs yet, so there is no functional change: DCN3.5/3.5.1/3.6 keep using the existing inbox1 lock path. Enabling them will come in a follow-up patch. Reviewed-by: Ray Wu <[email protected]> Signed-off-by: Tom Chung <[email protected]> Signed-off-by: Chenyu Chen <[email protected]> --- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 43 +++++++++++++++++++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 4 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 942d3f3d9f25..a0944d53860e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1822,3 +1822,46 @@ void dcn35_disable_link_output(struct dc_link *link, dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); } + +void dcn35_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock) +{ + /* use always for now */ + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + /* if not support inbox0 lock, would not use inbox0 lock mechanism */ + if (!dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support) + return; + + if (!dc_dmub_srv_is_cursor_offload_enabled(dc) && + !dmub_hw_lock_mgr_does_context_require_lock(dc, context)) + return; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); +} + +void dcn35_dmub_hw_control_lock_fast(union block_sequence_params *params) +{ + struct dc *dc = params->dmub_hw_control_lock_fast_params.dc; + bool lock = params->dmub_hw_control_lock_fast_params.lock; + + /* if not support inbox0 lock, would not use inbox0 lock mechanism */ + if (!dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support) + return; + + if (params->dmub_hw_control_lock_fast_params.is_required) { + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h index fce9acb5c2fc..392ccbcb343c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h @@ -27,6 +27,8 @@ #ifndef __DC_HWSS_DCN35_H__ #define __DC_HWSS_DCN35_H__ +#include "inc/core_types.h" +#include "dc.h" #include "hw_sequencer_private.h" struct dc; @@ -115,5 +117,7 @@ void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe void dcn35_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); +void dcn35_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); +void dcn35_dmub_hw_control_lock_fast(union block_sequence_params *params); #endif /* __DC_HWSS_DCN35_H__ */ -- 2.43.0
