From: Gabe Teeger <[email protected]>

Turn on power gating by default for dcn42b in the following domains:
DPP, HUBP, DSC.

Root clock gating is enabled for the following domains:
DPP, DSC, DPSTREAM, SYMCLK.

Now DCN42b will match the exact PG and CG policies as dcn42.

Reviewed-by: Matthew Stewart <[email protected]>
Signed-off-by: Gabe Teeger <[email protected]>
Signed-off-by: Chenyu Chen <[email protected]>
---
 .../dc/resource/dcn42b/dcn42b_resource.c      | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
index 7b21badf7025..092b61b3fafc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
@@ -802,9 +802,13 @@ static const struct dc_debug_options debug_defaults_drv = {
        .force_abm_enable = false,
        .clock_trace = true,
        .disable_pplib_clock_request = false,
-       .disable_dpp_power_gate = true,
-       .disable_hubp_power_gate = true,
+       .ignore_pg = false,
+       .disable_dpp_power_gate = false,
+       .disable_hubp_power_gate = false,
        .disable_optc_power_gate = true,
+       .disable_dsc_power_gate = false,
+       .disable_dio_power_gate = true,
+       .disable_hpo_power_gate = true,
        .pipe_split_policy = MPC_SPLIT_AVOID,
        .force_single_disp_pipe_split = false,
        .disable_dcc = DCC_ENABLE,
@@ -830,14 +834,14 @@ static const struct dc_debug_options debug_defaults_drv = 
{
                }},
        .root_clock_optimization = {
                .bits = {
-                       .dpp = false,
-                       .dsc = false,/*dscclk and dsc pg*/
+                       .dpp = true,
+                       .dsc = true,/*dscclk and dsc pg*/
                        .hdmistream = false,
                        .hdmichar = false,
-                       .dpstream = false,
-                       .symclk32_se = false,
-                       .symclk32_le = false,
-                       .symclk_fe = false,
+                       .dpstream = true,
+                       .symclk32_se = true,
+                       .symclk32_le = true,
+                       .symclk_fe = true,
                        .physymclk = false,
                        .dpiasymclk = false,
                }
@@ -866,7 +870,6 @@ static const struct dc_debug_options debug_defaults_drv = {
        .min_disp_clk_khz = 50000,
        .static_screen_wait_frames = 2,
        .disable_z10 = false,
-       .ignore_pg = true,
        .disable_stutter_for_wm_program = true,
        .min_deep_sleep_dcfclk_khz = 8000,
        .replay_skip_crtc_disabled = true,
-- 
2.43.0

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