From: Gabe Teeger <[email protected]> pg_cntl42_dsc_pg_status(i) should be bounded by the number of dsc, which is different from the number of DPP on dcn42b.
Reviewed-by: Matthew Stewart <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Chenyu Chen <[email protected]> --- drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c index 78b33b2dbae8..3a0e09ab0d9f 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -6,6 +6,7 @@ #include "core_types.h" #include "dcn42_pg_cntl.h" #include "dccg.h" +#include "resource.h" #define TO_DCN_PG_CNTL(pg_cntl)\ container_of(pg_cntl, struct dcn_pg_cntl, base) @@ -582,7 +583,10 @@ void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl) block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, i); pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled; pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled; + } + /* DSC count can be lower than pipe count (e.g. DCN42B has 4 pipes, 3 DSCs) */ + for (i = 0; i < (unsigned int)pg_cntl->ctx->dc->res_pool->res_cap->num_dsc; i++) { block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, i); pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled; } -- 2.43.0
