From: Alex Hung <[email protected]> [WHAT] Reduce the five KUnit tests for the GFX9 DCC block modes of amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers() to one, and the three for amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers() to one.
[HOW] Drive both from a table of modifier bits and the expected HUBP independent block mode, allocating the device, DC and framebuffer once and resetting the tiling, DCC and address outputs per row. Assisted-by: Copilot:Claude-Opus-5 Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: George Zhang <[email protected]> --- .../amdgpu_dm/tests/amdgpu_dm_plane_test.c | 414 ++++-------------- 1 file changed, 86 insertions(+), 328 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c index 807c91bd8ab1..0d0a3199b464 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c @@ -492,65 +492,6 @@ static void dm_test_format_mod_supported(struct kunit *test) listed_mod)); } -/** - * dm_test_fill_gfx12_plane_attributes_from_modifiers() - Verify GFX12 DCC mapping path. - * @test: KUnit test context. - * - * Verify if GFX12 modifier parsing enables DCC and sets expected DCC block mode. - */ -static void dm_test_fill_gfx12_plane_attributes_from_modifiers(struct kunit *test) -{ - struct amdgpu_device *adev; - struct dc *dc; - struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = { - .callback_ret = true, - .capable = true, - .output_independent_64b_blks = false, - }; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); - - adev->family = AMDGPU_FAMILY_GC_12_0_0; - adev->dm.dc = dc; - adev->gfx.config.gb_addr_config_fields.num_pipes = 2; - adev->gfx.config.gb_addr_config_fields.num_banks = 4; - adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256; - adev->gfx.config.gb_addr_config_fields.num_se = 1; - adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2; - adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1; - dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap; - dm_test_dcc_ctx = &ctx; - - afb->base.modifier = AMD_FMT_MOD | - AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) | - AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | - AMD_FMT_MOD_SET(DCC, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 1); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; - - KUNIT_EXPECT_EQ(test, - amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers( - adev, afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, - ROTATION_ANGLE_0, &plane_size, &tiling_info, &dcc, &address), - 0); - KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxAddr3); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_128b); - - dm_test_dcc_ctx = NULL; -} - /** * dm_test_fill_gfx9_plane_attributes_from_modifiers() - Verify basic GFX9 linear modifier path. * @test: KUnit test context. @@ -1502,148 +1443,36 @@ static void dm_test_fill_gfx9_plane_attributes_validate_fails(struct kunit *test } /** - * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl() - Verify block mode. + * dm_test_fill_gfx9_plane_attributes_dcc_ind_blk() - Verify DCC block modes. * @test: KUnit test context. * - * Verify if a GFX10-RBPLUS modifier with both 64B and 128B independent block - * bits selects the 64B-no-128BCL block mode. + * Verify if the independent 64B and 128B block bits of a GFX9 or GFX10-RBPLUS + * DCC modifier select the matching HUBP independent block mode. */ -static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl(struct kunit *test) +static void dm_test_fill_gfx9_plane_attributes_dcc_ind_blk(struct kunit *test) { - struct amdgpu_device *adev; - struct dc *dc; - struct amdgpu_framebuffer *afb; + static const struct { + const char *name; + u64 tile_version; + bool independent_64b_blks; + bool independent_128b_blks; + int expected_ind_blk; + } cases[] = { + { "rbplus 64B no 128BCL", AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS, true, true, + hubp_ind_block_64b_no_128bcl }, + { "rbplus 128B", AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS, false, true, + hubp_ind_block_128b }, + { "rbplus unconstrained", AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS, false, false, + hubp_ind_block_unconstrained }, + { "gfx9 64B", AMD_FMT_MOD_TILE_VER_GFX9, true, false, hubp_ind_block_64b }, + { "gfx9 unconstrained", AMD_FMT_MOD_TILE_VER_GFX9, false, false, + hubp_ind_block_unconstrained }, + }; struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = {0}; - u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; - int ret; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); - - dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, true); - afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, true, true); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; - - ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, - (int)hubp_ind_block_64b_no_128bcl); - - dm_test_dcc_ctx = NULL; -} - -/** - * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b() - Verify 128B block mode. - * @test: KUnit test context. - * - * Verify if a GFX10-RBPLUS modifier with only the 128B independent block bit - * selects the 128B block mode. - */ -static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b(struct kunit *test) -{ struct amdgpu_device *adev; - struct dc *dc; struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = {0}; - u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; - int ret; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); - - dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false); - afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, false, true); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; - - ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_128b); - - dm_test_dcc_ctx = NULL; -} - -/** - * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained() - Verify block mode. - * @test: KUnit test context. - * - * Verify if a GFX10-RBPLUS modifier without independent block bits selects the - * unconstrained block mode. - */ -static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained(struct kunit *test) -{ - struct amdgpu_device *adev; struct dc *dc; - struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = {0}; - u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; - int ret; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); - - dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false); - afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, false, false); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; - - ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, - (int)hubp_ind_block_unconstrained); - - dm_test_dcc_ctx = NULL; -} - -/** - * dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b() - Verify legacy 64B mode. - * @test: KUnit test context. - * - * Verify if a pre-RBPLUS GFX9 modifier with the 64B independent block bit - * selects the 64B block mode. - */ -static void dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b(struct kunit *test) -{ - struct amdgpu_device *adev; - struct dc *dc; - struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = {0}; - int ret; + unsigned int i; adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); @@ -1652,138 +1481,62 @@ static void dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b(struct kunit *test) KUNIT_ASSERT_NOT_NULL(test, dc); KUNIT_ASSERT_NOT_NULL(test, afb); - dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, true); - afb->base.modifier = dm_test_gfx9_dcc_modifier(AMD_FMT_MOD_TILE_VER_GFX9, - true, false); plane_size.surface_size.width = 1920; plane_size.surface_size.height = 1080; - ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_64b); - - dm_test_dcc_ctx = NULL; -} - -/** - * dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained() - Verify legacy mode. - * @test: KUnit test context. - * - * Verify if a pre-RBPLUS GFX9 modifier without the 64B independent block bit - * selects the unconstrained block mode. - */ -static void dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained(struct kunit *test) -{ - struct amdgpu_device *adev; - struct dc *dc; - struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = {0}; - int ret; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); + for (i = 0; i < ARRAY_SIZE(cases); i++) { + struct dc_tiling_info tiling_info = {0}; + struct dc_plane_dcc_param dcc = {0}; + struct dc_plane_address address = {0}; + struct dm_test_dcc_cap_ctx ctx = {0}; + int ret; - dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false); - afb->base.modifier = dm_test_gfx9_dcc_modifier(AMD_FMT_MOD_TILE_VER_GFX9, - false, false); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; + dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, cases[i].independent_64b_blks); + afb->base.modifier = dm_test_gfx9_dcc_modifier(cases[i].tile_version, + cases[i].independent_64b_blks, + cases[i].independent_128b_blks); - ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, - (int)hubp_ind_block_unconstrained); + ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc, + &address); + dm_test_dcc_ctx = NULL; - dm_test_dcc_ctx = NULL; + KUNIT_EXPECT_EQ_MSG(test, ret, 0, "%s", cases[i].name); + KUNIT_EXPECT_TRUE_MSG(test, dcc.enable, "%s", cases[i].name); + KUNIT_EXPECT_EQ_MSG(test, (int)dcc.dcc_ind_blk, cases[i].expected_ind_blk, + "%s", cases[i].name); + } } /** - * dm_test_fill_gfx12_plane_attributes_block0() - Verify GFX12 64B max-compressed-block path. + * dm_test_fill_gfx12_plane_attributes_dcc_blocks() - Verify GFX12 DCC blocks. * @test: KUnit test context. * - * Verify if a zero max-compressed-block modifier selects the 64B independent - * block mode on GFX12. + * Verify if the max-compressed-block field of a GFX12 DCC modifier selects the + * matching HUBP independent block mode and independent 64B flag, and if the + * GFX addr3 tiling version is reported. */ -static void dm_test_fill_gfx12_plane_attributes_block0(struct kunit *test) +static void dm_test_fill_gfx12_plane_attributes_dcc_blocks(struct kunit *test) { - struct amdgpu_device *adev; - struct dc *dc; - struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; + static const struct { + const char *name; + u64 max_compressed_block; + bool independent_64b_blks; + int expected_ind_blk; + } cases[] = { + { "64B", 0, true, hubp_ind_block_64b }, + { "128B", 1, false, hubp_ind_block_128b }, + { "unconstrained", 2, false, hubp_ind_block_unconstrained }, + }; struct dm_test_dcc_cap_ctx ctx = { .callback_ret = true, .capable = true, .output_independent_64b_blks = false, }; - int ret; - - adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); - dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); - afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL); - KUNIT_ASSERT_NOT_NULL(test, adev); - KUNIT_ASSERT_NOT_NULL(test, dc); - KUNIT_ASSERT_NOT_NULL(test, afb); - - adev->family = AMDGPU_FAMILY_GC_12_0_0; - adev->dm.dc = dc; - dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap; - dm_test_dcc_ctx = &ctx; - - afb->base.modifier = AMD_FMT_MOD | - AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) | - AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | - AMD_FMT_MOD_SET(DCC, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0); - plane_size.surface_size.width = 1920; - plane_size.surface_size.height = 1080; - - ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_TRUE(test, dcc.independent_64b_blks); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_64b); - - dm_test_dcc_ctx = NULL; -} - -/** - * dm_test_fill_gfx12_plane_attributes_block_unconstrained() - Verify block path. - * @test: KUnit test context. - * - * Verify if a max-compressed-block value above one selects the unconstrained - * independent block mode on GFX12. - */ -static void dm_test_fill_gfx12_plane_attributes_block_unconstrained(struct kunit *test) -{ + struct plane_size plane_size = {0}; struct amdgpu_device *adev; - struct dc *dc; struct amdgpu_framebuffer *afb; - struct plane_size plane_size = {0}; - struct dc_tiling_info tiling_info = {0}; - struct dc_plane_dcc_param dcc = {0}; - struct dc_plane_address address = {0}; - struct dm_test_dcc_cap_ctx ctx = { - .callback_ret = true, - .capable = true, - .output_independent_64b_blks = false, - }; - int ret; + struct dc *dc; + unsigned int i; adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); @@ -1795,25 +1548,36 @@ static void dm_test_fill_gfx12_plane_attributes_block_unconstrained(struct kunit adev->family = AMDGPU_FAMILY_GC_12_0_0; adev->dm.dc = dc; dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap; - dm_test_dcc_ctx = &ctx; - - afb->base.modifier = AMD_FMT_MOD | - AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) | - AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | - AMD_FMT_MOD_SET(DCC, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 2); plane_size.surface_size.width = 1920; plane_size.surface_size.height = 1080; - ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc, - &address); - KUNIT_EXPECT_EQ(test, ret, 0); - KUNIT_EXPECT_TRUE(test, dcc.enable); - KUNIT_EXPECT_FALSE(test, dcc.independent_64b_blks); - KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, - (int)hubp_ind_block_unconstrained); + for (i = 0; i < ARRAY_SIZE(cases); i++) { + struct dc_tiling_info tiling_info = {0}; + struct dc_plane_dcc_param dcc = {0}; + struct dc_plane_address address = {0}; + int ret; - dm_test_dcc_ctx = NULL; + afb->base.modifier = AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | + AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, + cases[i].max_compressed_block); + dm_test_dcc_ctx = &ctx; + + ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc, + &address); + dm_test_dcc_ctx = NULL; + + KUNIT_EXPECT_EQ_MSG(test, ret, 0, "%s", cases[i].name); + KUNIT_EXPECT_EQ_MSG(test, (int)tiling_info.gfxversion, (int)DcGfxAddr3, + "%s", cases[i].name); + KUNIT_EXPECT_TRUE_MSG(test, dcc.enable, "%s", cases[i].name); + KUNIT_EXPECT_EQ_MSG(test, (bool)dcc.independent_64b_blks, + cases[i].independent_64b_blks, "%s", cases[i].name); + KUNIT_EXPECT_EQ_MSG(test, (int)dcc.dcc_ind_blk, cases[i].expected_ind_blk, + "%s", cases[i].name); + } } /** @@ -3712,19 +3476,13 @@ static struct kunit_case amdgpu_dm_plane_test_cases[] = { KUNIT_CASE(dm_test_format_mod_supported_d_swizzle_reject), KUNIT_CASE(dm_test_format_mod_supported_gfx6), /* amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers() */ - KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_from_modifiers), - KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_block0), - KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_block_unconstrained), + KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_dcc_blocks), KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_validate_fails), /* amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers() */ KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_from_modifiers), KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc), KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_validate_fails), - KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl), - KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b), - KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained), - KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b), - KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained), + KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_ind_blk), /* amdgpu_dm_plane_helper_check_state() */ KUNIT_CASE(dm_test_helper_check_state_viewport_reject), KUNIT_CASE(dm_test_helper_check_state_small_viewport_width), -- 2.55.0
