From: Taimur Hassan <[email protected]> This version brings along the following updates:
- Refactor DC IP request control in HWSS. - Fix rotate 90 degrees surface corruption issue. - Refactor DPP root clock control in HWSS. - Fix upsampling and linear scaling. - Use aux hw inst if no ddc pin exists. - Directly include compiler_attributes.h. - Fix frac_urg_bw conversion to correct U0.10 format. - Do full link training during HDR/SDR seamless switch. - Fix SPL format handling for linear scaling and upsampling. - Update DCN42 cstate latencies. - Invalidate the DRR shadow after a hardware re-init. - Program HDR visual confirm based on per pipe info. - Split link_set_dsc_on_stream into encoder and DSC components. - Add new config_dsc hwseq function for DCN60. - Program DSC prior to OTG enable starting DCN60. - Improve mandatory pstate optimization and check. - Disable HUBP/DPP power gating on DCN42. Acked-by: Leo Li <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d3c484f45333..9cc90c406d86 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -68,7 +68,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.401" +#define DC_VER "3.2.402" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0
