From: Leo Chen <[email protected]> [Why] Driver-controlled HUBP and DPP power gating can cause display underflow on DCN42.
[How] Set disable_hubp_power_gate and disable_dpp_power_gate in the DCN42 driver debug defaults as a temporary workaround. Reviewed-by: Ovidiu (Ovi) Bunea <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- .../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 7c271dd264c9..a7fdffca8cb9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -745,8 +745,8 @@ static const struct dc_debug_options debug_defaults_drv = { .clock_trace = true, .disable_pplib_clock_request = false, .ignore_pg = false, - .disable_dpp_power_gate = false, - .disable_hubp_power_gate = false, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, .disable_optc_power_gate = true, .disable_dsc_power_gate = false, .disable_dio_power_gate = true, -- 2.43.0
