From: Sridevi Arvindekar <[email protected]>

[Why]
dpp_reset() only clears software state, so CNVC_UPSP_MODE and
PRE_CSC_MODE stay programmed on DCN6 after UPSP was used.

[How]
Add a DCN6 dpp_reset, dcn6_dpp_reset(), which clears both registers
when UPSP was in use and then calls the common dpp_reset().

Reviewed-by: Ilya Bakoulin <[email protected]>
Signed-off-by: Sridevi Arvindekar <[email protected]>
Signed-off-by: Ray Wu <[email protected]>
---
 .../drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c    | 17 ++++++++++++++++-
 .../drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h    |  1 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
index 4218863d2a04..2ba8218e2ac2 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
@@ -316,10 +316,25 @@ void dpp60_full_bypass(struct dpp *dpp_base)
                REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
 }
 
+void dcn6_dpp_reset(struct dpp *dpp_base)
+{
+       struct dcn60_dpp *dpp = TO_DCN60_DPP(dpp_base);
+
+       if (dpp->scl_data.upsp) {
+               if (dpp->tf_mask->UPSP_MODE) {
+                       // Reset dpp registers used for upsp, lls
+                       REG_WRITE(CNVC_UPSP_MODE, 0);
+                       REG_WRITE(PRE_CSC_MODE, 0);
+               }
+       }
+
+       dpp_reset(dpp_base);
+}
+
 static struct dpp_funcs dcn60_dpp_funcs = {
        .dpp_program_gamcor_lut         = dpp6_program_gamcor_lut,
        .dpp_read_state                         = dpp401_read_state,
-       .dpp_reset                                      = dpp_reset,
+       .dpp_reset                                      = dcn6_dpp_reset,
        .dpp_set_scaler                         = 
dpp60_dscl_set_scaler_manual_scale,
        .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
        .dpp_set_pre_degam                      = NULL,
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h
index f12a6061e5fb..7086ff773de8 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h
@@ -522,5 +522,6 @@ bool dpp60_construct(struct dcn60_dpp *dpp60,
 bool dpp6_program_gamcor_lut(
        struct dpp *dpp_base, const struct pwl_params *params);
 
+void dcn6_dpp_reset(struct dpp *dpp_base);
 
 #endif /* __DCN60_DPP_H__ */
-- 
2.43.0

Reply via email to