Hello Martin and fellow AmForthers,
Three interesting questions.
(1) RISC-V
# --------------------------------------
CODEWORD "0<", ZEROLESS # ( n -- ? )
# --------------------------------------
srai x3, x3, 31
NEXT
This is correct for RV32. My RISC-V codebase has the
similar code (different register) and gives the
following for the usual suspects.
AmForth-RV 7.0 RV32IMAFC WCH CH32V307 C+ASM
Tue 15 Oct 2024 11:52:30 BST
1 0< . \ correct
0 ok \ ...
-1 0< . \ correct
-1 ok \ ...
0 0< . \ correct
0 ok \ ...
(2) 32-bit ARM
I don't know enough to comment, hopefully others on the
list will, and already have, thank you :)
(3) What to do with the non-AVR codebase now?
It is still an open question, and one with many
parts. The current SVN RISC-V codebase dates back to
2019. I forked that in Oct 2023 for my own education,
but not in a way that would make updating the official
SVN repo easy. Additionally, whilst there is a good
deal of overlap (the virtues of an ITC VM) between the
AVR and 2019 SVN RISC-V codebases, the differences in
(1) dictionary layout (2) compilation storage media
(RAM, FLASH) mean that some "common" words are quite
different.
Is it time to restructure and have a separate repo
for the 32 bit AmForth?
Best wishes,
Tristan
[1] it has departed significantly elsewhere
On 2025-12-23 03:06, Martin Kobetic wrote:
I got the delays working on the uno r4, but while I was debugging I
noticed
that the word 0< (ZEROLESS) is actually '0 <= tos'. For ARM it's
implemented as
@
-----------------------------------------------------------------------------
CODEWORD "0<", ZEROLESS @ ( n -- ? )
@
-----------------------------------------------------------------------------
movs tos, tos
asr tos, #32 @ Turn MSB into 0xffffffff or 0x00000000
NEXT
(see
https://github.com/mkobetic/amforth/blob/main/arm/words/comparisions.s#L41)
The `asr tos, #32` (arithmetic shift right) shifts the sign bit over
the
entire register, so it does yield 0xffffffff or 0x00000000, but for 0
it
yields 0x00000000, so it says that 0< is true for zero.
I'm also wondering why is the `movs tos, tos` there, but that's
separate
from what seems like a bug to me. Am I correct? Do we want to fix this
separately from my UNO R4 effort or should I just fix it in my fork for
now?
Looking at the RISC-V version it seems it may have the same issue
#
-----------------------------------------------------------------------------
CODEWORD "0<", ZEROLESS # ( n -- ? )
#
-----------------------------------------------------------------------------
srai x3, x3, 31
NEXT
Cheers,
Martin
_______________________________________________
Amforth-devel mailing list for http://amforth.sf.net/
[email protected]
https://lists.sourceforge.net/lists/listinfo/amforth-devel
_______________________________________________
Amforth-devel mailing list for http://amforth.sf.net/
[email protected]
https://lists.sourceforge.net/lists/listinfo/amforth-devel
