Thank you for looking into this, John. Let me respond inline On Tue, Dec 23, 2025 at 1:36 AM John Sarabacha <[email protected]> wrote:
> The code for <0 looks correct for both ARM and RISCV > a 0 value on the tos is not less than zero so the MSB of a 0 value doesn't > generate the true flag which is -1 (all bits set). > Yes this is what I'd expect, but it's not what I'm getting on ARM. I'm getting 0 result when 0 is on TOS. > The ARM movs instruction is just used to set the condition codes without > disturbing the value on tos. > Yup, that makes sense, but it doesn't seem to have any impact on the execution of the rest of the word. That's why I'm wondering why it's there. > The RISCV architecture doesn't use arithmetic condition codes so doesn't > need the equivalent operation (movs). > The RISCV srai instruction does the equivalent by copying the MSB to > generate the true flag which is -1 (all bits set) if the tos value is less > than 0. So a tos value of 0 or greater will generate the false flag which > is 0. > I'm a bit confused by your last sentence. The false flag should be -1, correct? Thank you, Martin _______________________________________________ Amforth-devel mailing list for http://amforth.sf.net/ [email protected] https://lists.sourceforge.net/lists/listinfo/amforth-devel
