Hi Before we decide about FPGA technology, keep in mind that Xilinx and other vendors have pricing policy. It is called step pricing. So the price of the particular component, depends of cumulated order history. That's why I will push towards using same FPGA or SoC in all boards because once you exceed 10 pieces, you get about 30% discount. But once you approach to 101 pieces, such FPGA gets 70% cheaper. So it makes sense to apply bigger FPGA even if you don't want to use all its resources because such solution is cheaper. IF you look at ZynQ 7 chips in Digikey and the price is 5k$ and scares you, I can get such chips about 500..800$ per piece because I used it in several of my designs and long time ago exceeded 100pieces:) Because I will use ZynQ US+ in 3 other projects (Zu7/9 and ZU11), that is the reason I proposed this particular chip for our application because I can get zu11 cheaper than older Kintex 7K325 The same applies to other production companies. You must ask about step pricing before you get an offer for production:) At the moment we have step pricing for FPGAs used in AFC, AFCK, SPEC and WR switch. Sometimes it is cheaper to install bigger chip than smaller one because they belong to different price steps.
Greg -----Original Message----- From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov] Sent: Thursday, March 31, 2016 5:30 PM To: Sébastien Bourdeauducq <s...@m-labs.hk>; Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: Robert Jördens <r...@m-labs.hk>; Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) <david.leibra...@nist.gov>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] TTL + slow DACs > We'll probably want a few dozen TTLs, broken out on SMA, so the FMC > panel is not an option there. > > We can remove PCIe indeed, but keeping the WR oscillators is probably > a good idea as they can be used for clock synchronization with the master. For the purpose of a TTL card, I would recommend that the TTL be broken out to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the ARTIQ hardware. It would be possible to send 64 TTL lines out of a single AMC card of 6 HP width in this manner, much more than you could ever do with SMA, and with vastly cheaper cabling and excellent signal integrity for long cabling runs (tested to work fine with 30 m cable, for example). We have existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS signals on Ethernet cables. This card would not have an FMC mezzanine, but would rather just break things out directly from the FPGA. I would recommend using a similar architecture on the AMC board to our existing TTL riser card that interfaces between TTL at the FPGA and LVDS. I know we could directly drive LVDS to/from the FPGA, but then we don't have any isolation between the FPGA user IO and the end user application, which makes me nervous that users could more easily fry the FPGA. One could use a very inexpensive FPGA for this particular task, although it might be nice to have a hard processor if it is driving so many TTL lines. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
