On Friday, 8 April 2016 11:42:18 PM HKT Slichter, Daniel H. (Fed) wrote: > Greg also points out a number of advantages in terms of > management of bitstreams in a large-scale experimental setting.
We can also design a dynamic bitstream loading scheme with conventional FPGAs. The FPGA reports its current bitstream version, and it if does not match the one stored in the control PC, it downloads a new bitstream, rewrites its flash and reboots. I have already implemented something similar on Spartan-6, and it's pretty straightforward and requires no additional hardware. The Spartan-6 and 7-series also contain a mechanism to automatically fall back to a "golden" bitstream in case the flash becomes corrupted (e.g. due to losing power during reflashing). With the ARTIQ DRTIO protocol, this reflashing can take place during the "discovery" phase where devices are detected and assigned DRTIO addresses. The same software that does the discovery could access a repository of bitstreams and flash the relevant cards (all over the existing DRTIO communication hardware). With Greg's scheme, one would need additional hardware to support Ethernet on every AMC (PHY in the AMCs, backplane connectivity, switch in the MCH), configure it (IP, MAC, etc.), connect every crate to an Ethernet network in addition to the DRTIO fiber, and set up a separate NFS server. > Many potential users might prefer having a Zynq. Is there a good technical argument for Zynq? On the DSP/Sayma card? > We also discussed the advantages of having 24 gigabit transceivers, instead > of 16, in that then we are not reduced to hacks to have gigabit > connectivity (e.g. GbE, potentially PCIe, etc) while keeping the > possibility of using 8 DAC outputs at their full bandwidth. If this is not > a priority, the AD9154 can be run at a reduced instantaneous bandwidth > (e.g. higher interpolation rate) or reduced channel count, both of which > would be satisfactory for some applications, with only 4 lanes connected. > Thus one could connect one FMC with 8 lanes and the other with 4 lanes (4 > lanes is all that is needed for 4 channels of ADC at max data rates), and > have 4 left over. I proposed this idea back some months ago when we were > doing initial discussions. We also thought of those options, and we think that the IOSERDES bandwidth is sufficient for the AMC/MCH communications here. But we have no strong opposition to using transceivers on the backplane. Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
