Hi Dave, On Mon, Aug 1, 2016 at 5:15 PM, Leibrandt, David R. (Fed) <david.leibra...@nist.gov> wrote: > 1. I assume this logic would be followed by some sort of digital filter to > remove the unwanted Nyquist images. Have you thought about how good of > suppression you might be able to achieve, and at what FPGA resource and phase > distortion cost?
That AA filter would be a better interpolator between the summing of the f1/f2 oscilaltors and that data being fed into the f0 oscillator. That filter would suppress the images. Currently there is just a zeroth-order interpolator. I have played with designing a higher order interpolator and for a CIC the math will survive the up to second order but most likely not for third and higher. Same for FIR. > 2. Do you have an idea of the latency of the signal chain? Say I wanted to > do a phase lock by feeding new p1 values into the RTIO. What sort of > bandwidth could I achieve? The p1 latency is about 37 cycles at 5 ns/cycle: a few misc cycles here and there plus two CORDIC's worth of latency, each 16 bits + 3 guard bits. Currently I have the latencies of all components matched so that RTIO events on the different spline interpolators would automatically arrive in the data stream time-aligned. For local feedback in e.g. PID loops I would inject that feedback signal so that there is minimal latency. For e.g. feedback on the p0 term that would be around 20 cycles, also at 5 ns/cycle. The u term can probably be as fast as one or two cycles, the entire signal loop latency limited by other things. Robert. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
