That is true if you KNOW that you are going to only be in AR-mode. In the cases that I have seen in the past, the program was only conditionally in AR-mode. In fact, part of the time it was executing on hardware that did not even have address registers.
My point was: avoid problems downstream and code properly. Lloyd ----- Original Message ---- From: Tom Marchant <[email protected]> To: [email protected] Sent: Thu, August 19, 2010 9:12:46 AM Subject: Re: CDS and alignment question On Thu, 19 Aug 2010 05:32:15 -0700, Lloyd Fuller wrote: >And BOTH of the LA commands shown are bad coding practice >in these days of cross >memory: add the "," to make R11 and R12 be base registers >and not index registers. > >From experience that type of problem is difficult to debug >when a problem occurs >because you are suddenly running in AR mode. If the program is going to be running in AR mode, the LA instructions should probably be LAE. -- Tom Marchant > > >----- Original Message ---- >From: Paul Gilmartin <[email protected]> >To: [email protected] >Sent: Thu, August 19, 2010 1:27:30 AM >Subject: Re: CDS and alignment question > >On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote: > > > >> (------------------ Referenced Note Follows --------------------) >> Sent: Wednesday, August 18, 2010 3:51 PM >> >> QMGREX01 CSECT , >> STM R14,R12,12(R13) >> LR R11,R15 >> USING QMGREX01,R11,R12 >> LA R12,4095(R11) >> LA R12,1(R12) <----------------- noticed that I added 1 to >> the 4095 bump. > >-- gil
