I always like to use a second register with a value of +1
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LR R11,R15
LA R14,1
USING QMGREX01,R11,R12
LA R12,4095(R14,R11)
LR R8,R1
USING WORKAREA,R13
It is even move meaningful if using more base registers.
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LR R10,R15
LA R14,1
USING QMGREX01,R10,R11,R12
LA R11,4095(R14,R10)
LA R12,4095(R14,R11)
LR R8,R1
USING WORKAREA,R13
I always use R14 because I always pick it up using LM before branching
back to the caller so it's always fair game at this point in the
program. Any other register would have to be reloaded because the
program might be expecting them to contain something important.
Tony Thigpen
-----Original Message -----
From: Tom Marchant
Sent: 08/19/2010 10:02 AM
> On Wed, 18 Aug 2010 23:27:30 -0600, Paul Gilmartin wrote:
>
>> On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
>>
>>> I think the original posting was pointing out that you lose only
>>> a single byte of addressability by adding 4095, and that you save
>>> one instruction. The added byte is rarely an issue; whether or not
>>> the extra instruction is important depends on the application.
>>>
>> Making the CSECT 4 bytes longer to gain 1 byte of addressability
>> leaves you 3 bytes worse off.
>
> There are several methods of establishing that second base register. The
> original posted method of using LA to add 4095 is one instruction, four
> bytes. Two LA instructions to get an offset of 4096 is two instructions,
> eight bytes. LAY is one instruction, six bytes. LR and AHI is two
> instructions, six bytes. LARL is one instruction, six bytes.
>
> As David pointed out, sometimes it is better for the second base register to
> be 4096 greater than the first. I'll gladly take a one byte penalty for
> improved maintainability.
>
> --
> Tom Marchant
>
>
