On Aug 24, 2010, at 07:05, David Bond wrote:
> On Tue, 24 Aug 2010 07:50:22 -0500, McKown, John wrote:
>> On the z196, there is a "cache load" type instruction. I can't find the URL
> to the paper, but I vaguely remember it.
>
> Are you thinking of the z10 Prefetch Data instruction? On earlier
> processors the ICM instruction with a mask of zero did the same thing.
>
In PoOp I see:
When the mask is zero ..., the condition code is set to 0.
Might this disrupt pipelineing?
When the mask is zero, access exceptions are recognized for
one byte at the second-operand address.
But I see no mention of the effect on cache.
-- gil
