128K pointers, each of which is 8 bytes long, require 1MB of virtual storage. If there are 128K entries, each of which needs to have its own 4KB page acquired, then 128K*4K more, or 512MB, will be required, for a total of 513 MB. A sparse matrix can be carved up/designed in many different ways. E.g., to support 24-bit addresses in MVS/370, IBM chose a 4K page size (12 of the 24 bits of the address) and a maximum of 4K segments (the other 12 bits) in each address space. They could have used 7 bits for the page size and 17 bits for the segment size. Etc. I am sure they did a lot of modeling before they settled on the 4K page size. I also think that they did choose a different sized page for VSE.
The more information the OP has about the number of input elements and the possible range they will cover in a typical processing run, the better he will be able to design his sparse matrix structure. Not knowing anything about the data other than that it was random (from his first post), I chose the simplest structure, which was a one-level sparse matrix, which resulted in an array size of 512MB, which is not outrageously infeasible these days. Bill Fairchild Rocket Software -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Bob Flanders Sent: Wednesday, August 25, 2010 11:17 AM To: [email protected] Subject: Re: Efficient Memory List Bill, What if he did 128K set of pointers to as set of 4K pages, and allocated them as he found he needed a new page. It would be a max of a 1Mb (w/64bit pointers) overhead and would incur no more paging than if he allocated a single level array, right? The main cost would be the GETMAIN()s. (Once again, it's been a long time since I did any mainframe programming, so I'm rusty.) Sorry about that. And thanks!! Bob On Wed, Aug 25, 2010 at 11:07 AM, Bill Fairchild <[email protected]> wrote: > I don't remember if the OP specified in what respect the suggested... >
