On Tue, 24 Aug 2010 07:53:05 -0600, Paul Gilmartin wrote: >On Aug 24, 2010, at 07:05, David Bond wrote: >> On earlier >> processors the ICM instruction with a mask of zero did the same thing. >> >In PoOp I see: > > When the mask is zero ..., the condition code is set to 0. > >Might this disrupt pipelineing? > > When the mask is zero, access exceptions are recognized for > one byte at the second-operand address. > >But I see no mention of the effect on cache.
The PoOp does not describe everything. There was a change to GCC that added Prefetch Data support when code for the z10 was targeted but used ICM for earlier processors. An IBMer confirmed to me that ICM with a mask of zero performs the prefetch function. That GCC code was later modified to remove prefetch support for earlier processors. But I'm sure you can find the original in the change logs. David
