John,
You technique will work, just as the following technique will --
BASR R15,0
B *+4(R2,R15)
J RTN01
J RTN02
J RTN03
J RTN04
Now, the routine illustrated will modify one register and will execute a
total of three instructions.
Your routine will modify two registers and will execute a total of four
instructions.
The proposed BRUX will modify no registers and will execute a total of two
instructions.
I don't know how the various sequence will impact the instruction pipeline,
but I suspect that because of the register changes, the first two cases will
permit NO parallel processing to occur in the pipeline.
My thought is that the proposed BRUX and EXRX instructions would be much
more pipeline friendly.
Am I somehow misinterpreting the impact of the various instructions on the
pipeline?
John P. Baker
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]]
On Behalf Of John Ehrman
Sent: Monday, December 20, 2010 5:17 PM
To: [email protected]
Subject: Re: Still Needed
There's a simple way to do this without needing an indexed branch
instruction:
replace the indexed branch with these instructions:
LARL 0,BTABLE
AR 2,0
BR 2
You can use a similar technique for "indexing" an EX instruction.
John Ehrman
