John, here is my attempt-
First two stmts: 1.) Interruptable instructions are interrupted by interrupts (this is almost poetry) - by the interrupts enabled (and the non-maskable ones). 2.) Some activities (i.e. device pooling) need to occur within a defined time. These activities might not "be associated with"/tolerate interrupts. and the explanation as I see it: To make sure that no instruction takes longer than 0.nn-microseconds all the new ones (which might take longer) have that (at least to me) mysterious note: The instructions stops when whatever condition is met or a CPU determined time is over. Whoat? The CPU decides "it takes too long" and it stops? I was wondering till I realised the CC indicates why instruction execution was stopped. So conclusion: MVCL and CLCL (which are to my knowledge the only interruptable ones) will never get any brothers/sisters. All new ones will have the CC=3 mechanic for "m_O_re work" -- Martin Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE more at http://www.picapcpu.de
