I like this explanation. If I can rephrase it as a way to understand it, the original interruptible instructions were made interruptible so system processes that are urgent and higher priority could preempt the execution of long running micro/milli-code.
Newer interruptible instructions have a new feature that the unit of work interrupted is also informed of an interruption so it also has the option to do anything it might want to do before restarting the interruptible instruction. Efforts and courage are not enough without purpose and direction. - John F. Kennedy Fasten your seat belts, it's going to be a bumpy ride. - Bette Davis (as character Margo Channing) _All About Eve_1950 Our greatest danger in life is in permitting the urgent things to crowd out the important. - Charles E. Hummel The probability of error in a change is inversely proportional to the size of the change. - B.I Kahn's First Law The probability of error in a one character change is approximately 100%. If the possibility of collateral damage exists, the probably of error can appear to exceed 100%. - corollary to B.I Kahn's First Law From: Martin Truebner <[email protected]> To: [email protected] Date: 01/06/2012 11:56 AM Subject: Re: z/Arch design question. Sent by: IBM Mainframe Assembler List <[email protected]> John, here is my attempt- First two stmts: 1.) Interruptable instructions are interrupted by interrupts (this is almost poetry) - by the interrupts enabled (and the non-maskable ones). 2.) Some activities (i.e. device pooling) need to occur within a defined time. These activities might not "be associated with"/tolerate interrupts. and the explanation as I see it: To make sure that no instruction takes longer than 0.nn-microseconds all the new ones (which might take longer) have that (at least to me) mysterious note: The instructions stops when whatever condition is met or a CPU determined time is over. Whoat? The CPU decides "it takes too long" and it stops? I was wondering till I realised the CC indicates why instruction execution was stopped. So conclusion: MVCL and CLCL (which are to my knowledge the only interruptable ones) will never get any brothers/sisters. All new ones will have the CC=3 mechanic for "m_O_re work" -- Martin Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE more at http://www.picapcpu.de ----------------------------------------- The information contained in this communication (including any attachments hereto) is confidential and is intended solely for the personal and confidential use of the individual or entity to whom it is addressed. If the reader of this message is not the intended recipient or an agent responsible for delivering it to the intended recipient, you are hereby notified that you have received this communication in error and that any review, dissemination, copying, or unauthorized use of this information, or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail, and delete the original message. Thank you
