On 9 January 2012 04:40, Hobart Spitz <[email protected]> wrote: > Suppose you wanted to move a large amount of data, and there are many page > faults involved. If you divide the moves into logical sections, and do > each of the section moves in turn with MVCLE, you could go on to the next > when one is interrupted. Doing this in a round-robin fashion, you could > have your page faults being serviced in parallel. This could cut your move > time by roughly the reciprocal of the number of sections. It's a bit out > there for applications, but program products (like DB2, sort, etc.) might > benefit from such a technique. > > This is just speculation, but given the orders of magnitude difference > between CPU speed and I/O speed could this explain be the reason for the > CC=3 condition?
I don't think it works. You can't both have a CC=3 from the instruction, *and* have it cause a page fault. Even if the hardware/millicode chooses to give you a CC=3 when it can't resolve an address, there is no way for you to know that that's the problem. You could, I suppose, assume that that's what went wrong, and issue your own (async) pagein, but it doesn't sound like a very predictable business. Tony H.
