Edward, I agree that chip real estate is part of the issue. However, I suspect that there is more to it.
If an instruction is interruptible, then we have to ask the question "when is it interruptible?" In the case of MVCL, is it after every character, after every "n" characters, when the source location crosses an alignment boundary (4/8/16/??), when the target location crosses an alignment boundary (4/8/16/??), or some other undisclosed criteria? We also have to consider that if an instruction is interruptible, there is a major context save operation that must occur when the interrupt is recognized, and that additional microcode/millicode or silicon, depending on the implementation, is required to implement all of this within that specific instruction implementation. On the other hand, if the instruction is noninterruptible, but is suspendable, as in the case of MVCLE, only a minor context save is required when the suspension occurs (update the affected registers and set the condition code), which is much faster, and requires less additional microcode/millicode or silicon, depending on the implementation. Interrupt recognition can then occur between instructions, which is much more efficient, in terms of microcode/millicode or silicon, depending on the implementation. Benchmark tests have indicated that MVCL is less efficient than an MVC loop designed to perform the same function. I suggest that the inherent inefficiencies of interruptive instruction design could well be the cause. John P. Baker -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Edward Jaffe Sent: Saturday, January 07, 2012 1:48 AM To: [email protected] Subject: Re: z/Arch design question. On 1/6/2012 8:24 AM, McKown, John wrote: > My curiosity is why MVCLE sets the CC, thus forcing user code to branch back. Why not just not update the PSW instruction address until all the data is processed? Still allow the interrupt like MVCL does, of course. I understand why the interrupt is necessary, especially in a single CP environment. Does anybody know? Is it a "millicode" thing? It is a chip "real estate" thing. The amount of extra silicon used to make an instruction interruptible is extreme. It is a complex undertaking. Using standard, non-interruptible instructions is simpler and allows many more new and useful instructions to be added to the instruction set. -- Edward E Jaffe Phoenix Software International, Inc 831 Parkview Drive North El Segundo, CA 90245 310-338-0400 x318 [email protected] http://www.phoenixsoftware.com/
