OK, what I was thinking of "delay" was that the TBEGIN instruction itself would "stop" for a while with the CPU in a "wait" type state. My misinterpretation.
-- John McKown Systems Engineer IV IT Administrative Services Group HealthMarkets(r) 9151 Boulevard 26 * N. Richland Hills * TX 76010 (817) 255-3225 phone * [email protected] * www.HealthMarkets.com Confidentiality Notice: This e-mail message may contain confidential or proprietary information. If you are not the intended recipient, please contact the sender by reply e-mail and destroy all copies of the original message. HealthMarkets(r) is the brand name for products underwritten and issued by the insurance subsidiaries of HealthMarkets, Inc. -The Chesapeake Life Insurance Company(r), Mid-West National Life Insurance Company of TennesseeSM and The MEGA Life and Health Insurance Company.SM > -----Original Message----- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER- > [email protected]] On Behalf Of Martin Truebner > Sent: Wednesday, September 19, 2012 8:37 AM > To: [email protected] > Subject: Re: The Transaction state (correction) > > John, > > >> I guess "delayed" could mean that the TS code needs to be rerun and > this extra CPU usage "delays" the results. > > The samples given with TBEGIN do show that "delay" in response to a non > 0 CC > > -- > Martin > > Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE > more at http://www.picapcpu.de
