John,
How about an EX(ecute) Relative on Condition (EXRC) instruction?
In assembler, the instruction would be written as --
EXRC M1,R2,I3(X3)
In memory, the instruction would have the following layout --
0-7 Opcode
8-11 R2
12-15 X3
16-31 I3
32-35 M1
36-39 Reserved
40-47 Opcode
M1 is a condition code mask, as is commonly used in a BC or JC instruction.
If the bit contained in the mask corresponding to the current condition code
is set, then the instruction specified by the I3 operand will be executed.
Otherwise, the instruction will act as a NOP (4700 0000).
R2 is a general purpose register. If non-zero, the low-order byte of the
register will be inclusively or'ed into bits 8-15 of the instruction
specified by the I3 operand before it is executed. Like the standard
EX(ecute) instruction, this operation occurs in the instruction processor
and does not affect the memory containing the instruction specified by the
I3 operand.
I3 is a signed displacement, indicating the location of the instruction to
be executed. It is coded as the number of halfwords from the address of the
EXRC instruction.
X3 is a general purpose register. If non-zero, it contains a displacement
offset which is added to the signed displacement specified by the I3
operand. The use of this operand permits the use of an indexed table of
EX(ecutable) instructions.
This instruction will not set a condition code. However, the EX(ecuted)
instruction may set the condition code.
John P. Baker
President
NGSSA, LLC
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]]
On Behalf Of McKown, John
Sent: Monday, November 26, 2012 4:39 PM
To: [email protected]
Subject: Stupid? though on a new "execute" instruction.
It's the holiday season. So be nice.
There currently exist 2 execute variants. The old base+displacement and the
new relative. Now that we have 64 bit registers, why not have an RR
instruction where the first register the modifying value but the second
register contains the actual instruction to be executed. I have no idea how
the hardware actually works internally, so perhaps this would be a huge
kludge. But, then, at present the EX instruction must copy the referenced
instruction "somewhere" and modify it "somehow". So why couldn't it copy
from a register as well as from the D-cache? Or, maybe, how about an EX
which works like EXRL but the relative instruction is "hard coded" to be the
next instruction in line? The problem, of course, is that this new EX would
then need to "skip over" the just executed instruction. And I don't know how
to handle "interruptible" instructions. But EX can do it, so I guess the
same way.
Yes, I realize these are likely not of much importance. It's just that
there's nothing going on and for the rest of the year we are in "don't do
anything" mode so that month-end, quarter-end, and year-end processing will
be smooth.
OK, since I have you here anyway. What about a real weirdie? An instruction
which says whether or not to execute the next instruction, based on the
condition code? That would enable every instruction to be a conditional
instruction. Perhaps EXNC (Execute Next Conditional). What comes to mind?
Perhaps:
SLR R2,R2
LTR R1,R1
EXNC NZ
L R2,0(,R1)
LTR R2,R2
JZ BADADDR
Which would load the contents of R2 with the address contained in R1 unless
it was zero. Or maybe (combining both of the above)
L R1,LEN LENGTH OF FIELD
AHI R1,-1 DECREMENT FOR EX
EXNZ
EXRI R1 EX NEXT INSTRUCTION
MVC RECEIVE(0),FROM
Returning you now to your regularly scheduled, useful, email.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
[email protected] * www.HealthMarkets.com
